JPH02276351A - Fsk demodulating circuit - Google Patents

Abstract

PURPOSE:To make a filter of an FSX demodulating circuit into an IC with a high precision by reducing the number of filters of an SCF(switched capacitor filter) by clock switching. CONSTITUTION:Since a clock frequency is stepwise superposed on the output of the SCF, the offset due to an influence of an operational amplifier of the SCF is eliminated by a buffer 22, a capacitor 23, and a resistance 24 after the output passes a low pass filter consisting of a resistance 20 and a capacitor 21. The clock of the SCF is obtained by an oscillation frequency dividing circuit 30 having two frequency division ratios and a quartz oscillator 29, and frequency division ratios give a divided frequency suitable for a high group or a low group by H/L input. For example, when a ratio of the center frequency of band pass to the clock frequency of the SCF is 58, 62.64kHz which is 58 times as high as 1080Hz and 101.5kHz which is 58 times as high as 1750Hz are given in CCITT standards, and the quartz oscillation frequency is set to 1MHz and the frequency division ratio is set to 16.10, thereby obtaining an about objective clock frequency. Thus, one SCF is enough, and the SCF is used for the high group as well as the low group with a simple logic circuit.

Description

Detailed Description of the Invention The present invention provides an FSK filter using a switched capacitor filter (hereinafter referred to as SCF) as the bandpass filter.
Related to demodulation circuits. FSK demodulation circuits are used as inexpensive low-speed modems, and coupler modems in particular are widely used because they are easy to use. Although the FSX demodulation circuit is slow, it easily divides the frequency and enables full-duplex communication over two wires, which is why the filter is so important. Particularly in coupler modems, since the transmitted signal returns to the receiving side through the handset of the telephone, a highly accurate filter is required to separate the received signal from it. In the past, expensive LC filters were used, and high-order active filters had to be selected and adjusted in a sophisticated manner, resulting in expensive and large products. However, in recent years, IC filters have been developed in which resistors are replaced with operational amplifiers, capacitors, and switching elements, and are called switched capacitor filters. Accuracy is determined by the capacitor ratio and clock frequency, the capacitance is determined by the IC pattern area, and the clock frequency is made highly accurate by a crystal oscillator, making it possible to construct a high-precision, high-order filter without adjustment.

Note that the ratio of the clock frequency to the applied frequency domain is usually several tens of times, and the sampling filter performs sampling. Therefore, the scF has the property that the passband moves depending on the clock frequency, and if the frequency of the bandpass filter is doubled, the passband will also be doubled.

The present invention provides a highly accurate IC as a filter for an FSK demodulation circuit.
S is suitable for reducing the cost and size of modems.
This provides an application method for CF.

An object of the present invention is to reduce the number of scF filters by clock switching. Another object of the present invention is to
The purpose is to realize FSK demodulation circuits with different specifications by switching the CF clock.

The present invention will be explained in detail below with reference to the drawings.

FIG. 1 shows the FSX signal flow of a typical coupler modem as an FSX modem.

A transmitted signal from a speaker 1 is converted into an acoustic signal through a speaker of a handset 3 of the telephone, and is received and demodulated by a modem using a microphone 2 of a coupler.

The problem is that handsets are designed in such a way that the audio signal that enters the microphone is returned to its own speaker.
During a phone call, it is convenient because the person making the call can also hear their own voice, but in data communication, the received signal and the own transmitted signal are mixed, and it is difficult to separate them using a bandpass filter. becomes essential. The received signal is at a low level due to the attenuation of the line, but the transmitted signal that returns is at a high level, equivalent to the self-transmitted level, so the importance of the filter is very large. In the case of a direct connection modem, it is possible to cancel the feedback of the transmitted signal by using a hybrid transformer or the like, but it cannot be made zero due to the effects of impedance mismatch. In addition, the performance of the filter also directly affects the improvement of the demodulation S/N capability. FIG. 2 illustrates the frequency division of the FSK signal. There are various frequency allocations such as standards by CCITT, and as representative ones, the CCITT standard is shown as a dotted line, and the Bell standard is shown as a solid line. The black circle represents the CCITT standard, and the white circle represents the mark or space of the Bell standard. According to the CCITT standard used in Japan, the low group mark is 98QHz and the space is 1180QHz.
Hz, high group mark is 1650Hz, space is 185
It is 0Hz.

In order to separate high group and low group, a bandpass filter is required, and it can be set in the modem in advance, or it can be switched to low group transmission mode or high group transmission mode by switching the modem to match the transmission band of the other modem. It needs to be reversed.

FIG. 3 is a block diagram of a conventional FSK demodulation circuit. It is composed of a microphone 4, a bypass filter 5, an amplifier 6, a bandpass filter 8, a limiter 8, and a demodulation circuit 9. 5 removes shock and vibration noise in the low range, and the demodulation circuit methods include a method that takes the level of a bandpass filter corresponding to marks and spaces, a method that uses PLL and uses the VCO output as demodulation output, and a method that uses a counter. There are methods to measure the period. Regarding the band pass filter No. 7, as mentioned above, it is necessary to switch the passband depending on whether the high group or low group is to be received, and it goes without saying that the band is opposite to the transmitting band. Therefore, two series of LC filters are prepared and input/output is switched, which is very expensive.

There is also a method of switching the constants of the active filter, which is shown in FIG. FIG. 4 shows a second-order RC active bandpass filter, which is connected in a three-stage cascade to realize a sixth-order filter. The characteristics are resistance 11.
12 and the transistor 13, the resistance can be switched between only 11 and a parallel value of 11 and 12. 14 is a base resistor, and H/L is a switching signal that becomes H level when receiving high frequencies, turns on 13, and becomes L level when receiving low frequencies. However, this switching circuit requires 3 stages for the 6th order, and RC
In order to obtain high accuracy as a property of an active filter, R
, C is difficult to select and adjust, and the long-term reliability and temperature characteristics are also poor. In other words, the design must take into account such errors, making it difficult to obtain steep cutoff characteristics.

FIG. 5 is a block diagram of a demodulation circuit using the SCF of the present invention, and by incorporating it into an IC, it is possible to achieve high precision without adjustment, reliability, miniaturization, and cost reduction. Microphone 15, bypass filter with capacitor 16 and resistor 17, amplifier 1
8 and the received signal is input to 5CF19. In SCF, the clock frequency is superimposed on the output in a stepwise manner, so after passing through a low-pass filter with a resistor 20 and a capacitor 21, the SC is output with a buffer 22, a capacitor 23, and a resistor 24.
Remove the offset due to the influence of the F operational amplifier. S
The input of the CF folding noise prevention filter is an acoustic signal passed through a microphone, and the energy in the high frequency folding region is almost non-existent and can be omitted. 25 is the amplifier, 2
6 is a limiter, 27 is a comparator, and 28 is a demodulation circuit. The demodulation circuit measures the period of the square wave output from the comparator using a counter to determine whether it is a mark or space and obtains a digital signal. The counter method can be configured only with logic and is very easy to integrate into an IC, but requires an input with a low noise level. This drawback can be overcome by employing a higher order SCF.

Also, the reason why the amplifiers are distributed before and after the SCF is to use the SCF in a position where the noise is relatively large and the level is high, and to avoid inputting clipped or distorted waveforms due to noise etc. to the SCF input. The goal is to satisfy two contradictory demands, such as using the technology at the smallest possible level. In addition, the bypass filter in 22.23.24 prevents the limiter from operating on the positive and negative sides of the waveform, and also forms an accurate zero and cross comparator as AC coupling between the limiter and comparator, reducing demodulation ability. Try not to. The clock of the SCF is obtained by an oscillation frequency divider circuit 30 and a crystal oscillator 29 having two frequency division ratios, and the frequency division ratios are manually determined by H/L to give a divided frequency suitable for the high group or the low group. As an example, if the ratio of the bandpass center frequency to the SCF clock frequency is 58, CCITT
The standard is 62.64KHz, which is 58 times 1080Hz.
The result is 101.5 KHz, which is 58 times 1750 Hz.If the crystal frequency is set to IMHz and the division ratio of each is set to 16.10, almost the desired clock frequency can be obtained. The operation mode of the variable frequency divider circuit is switching, does not require high-speed operation, and the circuit configuration is easy. According to the present invention, SC
Only one set of F is required, and both high and low groups can be used with only a simple logic circuit. As a result, the operational amplifier portion that occupies a relatively large area on the IC can be reduced, and power consumption can be reduced.

FIG. 6 shows an embodiment of the variable frequency divider circuit of the present invention, and corresponds to 30 in FIG. IMH oscillated by an inverter 33 using a crystal oscillator 31.6MO3, etc., and a feedback resistor 32
z is input to the divider stage.

34-36 of D type FF34-37 are L/8 or 1
This is a frequency division stage that operates at 15, and when H/L is at H level, 34 to 36 are set as LSB by AND gate 38.
It is detected with an advancing force of 101, and the FF is reset to return to 000. If H/L is at L level, no reset operation is performed and the circuit functions as a 1/8 frequency divider. The output is taken from the Q output of 36, and when the frequency is divided by 115, the duty is not 1:1, and only the delay time between the output of binary 100 and the end of the reset of 101 becomes H level. Therefore, the final stage FF3
7, the lock outputs φ and T are symmetrical. 62°5KHz
Or 100KHz is obtained. FIG. 7 shows another embodiment of the present invention, showing an SCF and an SCF clock control circuit. In the case of the method shown in FIG. 6, the band width of the band-pass filter also changes as the SCF clock frequency increases, and this is to improve the problem that the band width becomes somewhat wider in the case of a high group. 2 in total
Switching terminal B/C to accommodate various frequency specifications
has. A high group band pass filter 39 and a low group band pass filter 40 are each constituted by an SCF, which are selected by an analog switch 4L42 and outputted by a buffer 43.

F! is the filter input, and FO is the filter output. 7th
In the method shown in the figure, it is possible to obtain the optimum band width with separate high group and low P1 filters, so each filter is switched to a different specification, such as the CCITT standard or the Bell standard. For example, in the low group reception mode, H/L input, AND gate 44 is not selected by inverter 46, 45 is selected, only 40 is input with clock, and 39 is SC with clock stop.
Prevent noise generation and crosstalk from F. At the same time, the analog switch 42 is also selected.

The output of the variable frequency divider circuit 47 can generate four types of clock frequencies, which are selected by H/LSB/C. This allows the same modem to be used for a variety of purposes, greatly expanding its range of use. Furthermore, when producing modems for individual applications, the same IC can be used, making it possible to reduce costs due to economies of scale. FIG. 8 shows a basic circuit of an SCF according to an embodiment of the present invention. Operational amplifier 48 and capacitors C1 to C
4. Consists of MOS analog switches 49 to 51. vl is an integral input, and an integrator with a large time constant can be configured only by the ratio of the frequency fs and the capacitors C, C4. v2 is a positive-phase integral input and is input to the operational amplifier in the opposite direction by switches 50 and 51, so v2 functions as a negative adder and performs additions with the feedback group that are necessary for the filter configuration.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the flow of data in a general coupler modem. FIG. 2 is a diagram showing the frequency band of a commonly used FSK modem, and FIG. 3 is a block diagram of a conventional FSK demodulation circuit. Figure 4 shows the RC of a conventional FSK demodulation circuit.
FIG. 2 is a basic circuit diagram of an active filter. FIG. 5 is a block diagram of an FSX demodulation circuit according to an embodiment of the present invention. FIG. 6 is a circuit diagram of FIG. 5 30 in an embodiment of the present invention. FIG. 7 is a clock circuit diagram of an SCF according to another embodiment of the present invention. FIG. 8 is a basic circuit diagram used in the SCF of the embodiment of the present invention. 1・φ・・φ・φ Speaker 2.4.5・φ・Microphone 3・・・・・・・・Contact handset・Soto 5・・φ・φ・・−Bypass filter 6.18 .25
...Amplifier 7.19...Band pass filter 8.26・φ
Φ...Limiter 9.28...Demodulation circuit 27, Φ...@φ, Comparator 39.40...5CF 30......Variable frequency divider circuit and above Figure 1 Applicant Seiko Epson Co., Ltd. Agent Patent Attorney Kizobe Suzuki (and 1 other person) Figure 2 Procedural amendment (voluntary) 2゜Name of the invention SK demodulation circuit 3゜Amending party 5゜Specifications subject to amendment Document (Claims) Contents of amendment Claims An FSK demodulation circuit whose purpose is to increase the number of times.

Claims (3)

[Claims] (1) In the FSK demodulation circuit that receives and demodulates Z-value signals using different frequencies corresponding to marks and spaces, an SCF (switched capacitor filter) is used as a bandpass filter that passes the paired mark and space frequencies. ,
An FSK demodulation circuit characterized in that a clock circuit for supplying a clock to the filter has means for selecting and generating one of two or more types of frequencies. (2) The frequency of the clock circuit is 2 in full duplex communication mode.
2. The FSK demodulation circuit according to claim 1, wherein the FSK demodulation circuit selectively generates an SCF clock frequency corresponding to the reception frequency band side of the two frequency bands and switches the passband of the SCF. (3) The SCF is configured separately as a filter for two frequency bands of a full-duplex communication system, and the clock circuit selects the SCF clock frequency on the receiving frequency band side according to the full-duplex communication system with different frequency standards. An FSK demodulation circuit according to claim 1, which generates an FSK demodulation circuit according to claim 1.