JP2993822B2 - Line characteristics measurement device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line characteristic measuring apparatus for measuring an attenuation characteristic and a time delay characteristic at each frequency of, for example, a four-wire telephone line or a data line.

[0002]

2. Description of the Related Art In recent years, various office equipment such as a facsimile machine and a personal computer have been connected to telephone terminals at homes and offices in addition to ordinary telephones for ordinary conversation with the other party. . These devices are connected to a telephone line via a modem.

Therefore, not only ordinary voice but also various data signals are transmitted on a signal line connecting each terminal and a telephone station. Generally, these data signals are transmitted after being modulated in various forms. Therefore, in order for these various digital data signals to be transmitted and received accurately, it is necessary to transmit the signal waveforms accurately.

However, as is well known, the signal lines of general telephones are often simple ones such as paired lines, so if the distance between the signal lines connecting each terminal and the telephone station is long, the signals are not transmitted in the signal transmission process. Decay or delay. In addition, the amount of attenuation and the amount of delay greatly change according to the frequency. In particular, in the case of the QAM modulation method, an increase in the attenuation distortion and the delay distortion causes a significant deterioration in an error rate in data communication.

In order to prevent such signal attenuation and delay, as shown in FIG. 4, an equalizer is provided at an intermediate position of, for example, a four-wire signal line 3 connecting a telephone station 1 and a terminal 2. 4 to compensate for the attenuation and delay of various signals transmitted through the signal line 3. In the equalizer 4, an amplitude compensation circuit and a delay compensation circuit are inserted in series on a signal line 3a from the telephone station 1 to the terminal 2 and a signal line 3b from the terminal 2 to the telephone station 1, respectively. I have.

The amplitude compensating circuit and the delay compensating circuit are used to compensate for the frequency characteristic of the signal line 3.
The frequency characteristics that are the inverse characteristics to the frequency characteristics of are set. Therefore, it is necessary to measure the frequency characteristics of the signal line 3 in advance.

As a general method for measuring the frequency characteristics of the signal line 3, for example, in FIG. 4, an oscillator for outputting a test signal is attached instead of the terminal 2, and a measuring instrument is attached instead of the equalizer 4. . Then, the oscillation frequency of the oscillator is swept over the entire predetermined measurement area. Then, the received signal level at each frequency is observed by the measuring instrument. In general, a flat level meter and a selective level meter can be considered as the type of the measuring device.

The flat level meter is a level meter having the same reception level over the entire measurement frequency range, and can accurately measure the level of the input signal regardless of the frequency of the input signal. . However, since noises of different frequencies other than the signal are also detected at the same time, it is easily affected by external noise, and there is a concern that the S / N of the measurement result is reduced and the reliability of the obtained frequency characteristic is reduced.

On the other hand, the selective level meter extracts only the signal level of the received signal having the same frequency as the oscillation frequency of the oscillator. Therefore, since noise of frequencies other than the measurement frequency is not mixed into the measurement result, the reliability of the obtained frequency characteristics can be improved.

However, in order to extract the oscillation frequency from the received signal and synchronously detect the received signal with this frequency,
The circuit configuration is significantly complicated. FIG. 5 is a block diagram showing a schematic configuration of a selective level meter using a PLL circuit.

A received signal a input from the input terminal 5 and represented, for example, by the equation (1) is a BPF (bandpass filter) 6
Is input to the PLL circuit 7 via the.

A = A sin (2πft + φ) (1) The PLL circuit 7 extracts a synchronous frequency signal from the received signal a and outputs the synchronous frequency signal via the first multiplier 8 and the 90 ° phase shifter 9 to the second.
To the multiplication circuit 10. Therefore, the synchronization detection signals b and c shown in the equations (2) and (3) are applied to the multiplication circuits 8 and 10, respectively.

B = sin2πft (2) c = cos2πft (3) Each of the multipliers 8 and 10 receives the received signal a and each synchronous detection signal b,
c, and is converted to multiplied signals d and e to obtain the next LPF
(Low-pass filter) 11 and 12 are transmitted.

D = A sin (2πft + φ) sin2πft = − (A / 2) cos (4πft + φ) + (A / 2) cosφ (4) e = A sin (2πft + φ) cos2πft = − (A / 2) sin ( 4πft + φ) − (A / 2) sinφ (5) Then, the multiplication signals d,
Only the DC components A cos φ and A sin φ of e are extracted. Each of the extracted DC components is subjected to a square operation by the following squaring circuits 13 and 14. The square values output from the respective squaring circuits 13 and 14 are added by the following adding circuit 15.

Therefore, the output terminal 1
The output signal g output to the signal A6 has the amplitude A as shown in the equation (6).
The square value of

[0016] g = [(A / 2) cosφ] 2 + [(A / 2) sinφ] 2 = A 2/4 ... (6) can only be accurately measured amplitudes A of the thus received signal a.

Therefore, the frequency characteristic of the signal line 3 can be obtained by observing the level of the output signal g of the selective level meter while sweeping the oscillation frequency of the oscillator attached to the terminal 2.

[0018]

However, the line characteristic measuring device employing the selective level meter shown in FIG. 5 still has the following problems to be solved.

That is, the PLL circuit 7 is generally mainly composed of a complex analog circuit such as a phase detection circuit, an LPF, a VCO, and a frequency dividing circuit. Therefore, not only the circuit configuration becomes complicated, but also a large amount of time and labor is required for the adjustment work. Also, the BPF needs to follow the frequency of the received signal a to some extent. Further, a 90 ° phase shifter 9 having a complicated circuit configuration and complicated adjustment is required.

As described above, in the conventional line characteristic measuring apparatus, not only the circuit configuration becomes complicated, but also a great deal of labor is required for adjustment.

The present invention has been made in view of such circumstances, and sequentially reads out a waveform stored at each address of a waveform memory, thereby providing a transmission sine waveform signal to be applied to a line under test. It is another object of the present invention to provide a line characteristic measuring apparatus capable of generating each signal waveform for synchronous detection including a cosine waveform signal and capable of accurately measuring the frequency characteristic of a line to be measured with a simple circuit configuration.

[0022]

In order to solve the above-mentioned problems, in a line characteristic measuring apparatus according to the present invention, an upstream transmission line and a downstream transmission line are set at a predetermined impedance at a far end of a 4-wire measured line. A coupler for terminating and folding each line, a waveform memory for storing a sine waveform, and specifying each address in the waveform memory in an order corresponding to a measurement frequency in synchronization with a read clock signal. A sine waveform counter that outputs a sine waveform signal, a cosine waveform counter that outputs a cosine waveform signal by specifying each address in the waveform memory in an order corresponding to the measurement frequency in synchronization with the read clock signal, and a A first multiplying circuit for calculating a multiplied value of the sine waveform signal output and passed through the line under test and the attenuator and the sine waveform signal output from the waveform memory A second multiplier circuit for calculating a multiplication value of a sine waveform signal output from the waveform memory and passing through the line under test and the attenuator and a cosine waveform signal output from the waveform memory, and first and second multiplication circuits A pair of low-pass filters for extracting a DC component of each multiplied signal output from the circuit, a pair of squaring circuits for calculating a square value of each DC component output from the pair of low-pass filters,
And an adding circuit for adding each square value calculated by the pair of squaring circuits.

[0023]

With the line characteristic measuring device configured as described above, a single waveform memory storing a sine waveform can be used.
By changing the address designation method in the waveform memory, it is possible to arbitrarily change the waveform type such as a sine waveform and a cosine waveform, the phase delay, and the frequency of the output signal. That is, for example, if the address is specified by skipping a plurality of addresses, the frequency of the output signal waveform increases. Also, the waveform reading start address is deliberately set to 90.
A cosine waveform signal is output if it is shifted by an angle of °.

Therefore, in addition to using the sine waveform signal output from the waveform memory as a test signal for the line under test, it can be used as a synchronous detection signal when this test signal is used.

Therefore, the first multiplication circuit generates a multiplication signal of the sine waveform signal passed through the circuit to be measured and the sine waveform signal output from the waveform memory, and generates the second signal.
A multiplication signal of the sine waveform signal passed through the line under measurement and the cosine waveform signal output from the waveform memory is created by the multiplication circuit of (1). Therefore, the DC component of each multiplied signal is extracted by an LPF, a squared value is obtained by each square calculating circuit, and the sum is added by an adder.
The amplitude value of the signal passing through the line under test can be measured.

[0026]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing a schematic configuration of an equalizer in which the line characteristic measuring device of the embodiment is incorporated. This equalizer 21 is interposed, for example, at a substantially intermediate position of a four-wire signal line 3 between the telephone station 1 and the terminal 2 shown in FIG. When measuring the frequency characteristic of the signal line 3, instead of the terminal 2, a resistance attenuator 22 as a coupler is used.
Is connected.

In the equalizer 21, an A / D converter 24a, a digital filter 25a, a changeover switch 26 are connected to a signal line 3a for transmitting a signal from the telephone station 1 to the terminal 2.
a, D / A converter 27a is interposed. On the other hand, an A / D converter 24b, a changeover switch 26b, a digital filter 25b, and a D / A converter are sequentially connected to the signal line 3b through which signals from the terminal 2 to the central office 1 are transmitted. 27b is interposed. Each changeover switch 26
a, 26b are normally connected to the normally closed side,
The terminal is switched to the normally open terminal only when measuring the frequency characteristics of the signal line 3.

Therefore, the signals from the A / D converter 24a to the D / A converter 27a in the signal line 3a are n-bit digital signals. A / D converter 2 in signal line 3b
4b to the D / A converter 27b are the same.

The oscillating unit 28 is connected to the normally open terminal of the changeover switch 26a of the signal line 3a, and the level measurement unit 29 is connected to the normally open terminal of the changeover switch 26b of the signal line 3b. A Fourier operation unit 30 is connected to the level measurement unit 29. Further, a control unit 31 composed of, for example, a microcomputer is incorporated in the equalizer 21. The control unit 31 controls the start / stop of the oscillating unit 28 and the changeover switches 26
Processing tasks such as switching state control of a and 26b are performed.

Each switch 26a, shown in FIG.
26b, each digital filter 25a, 25b, and each A /
D converters 24a, 24b, D / A converters 27a, 27
b etc. are circuit configurations suitable for digitization, and one LS
It is also possible to incorporate it into I.

FIG. 1 is a schematic configuration diagram of a line characteristic measuring device composed of an oscillating unit 28, a level measuring unit 29 and a control unit 31.

The oscillating unit 28 includes a waveform memory 28a formed of a storage element such as a ROM, and a sine waveform counter 2
8b, 28c, a cosine waveform counter 28d, two changeover switches 28e, 28f, a clock oscillator 28g, and a buffer 28h.

[0034] Within the waveform memory 28a, as shown in FIG. 3, each address _{A 0, A 1, ...,} A N / 2, ... of each pulse height is for example n bits of each sine waveform A _M digital It is stored as a value. When the address A is designated from the outside, the n-bit peak value stored at the address A is sent to the common terminal c of the changeover switch 28f. Therefore, when the address A is specified in order to A ₀ to A _M, sine waveform signal is output.

The input terminal of the waveform memory 28a is connected to the common terminal c of the changeover switch 28e. The terminals a, b, and d of the changeover switch 28e are connected to a sine waveform counter 28b for transmission, a sine waveform counter 28c for synchronous detection, and a cosine waveform counter 28d for synchronous detection, respectively. Further, each terminal a of the changeover switch 28f,
b and d are respectively connected to a buffer 28h connected to the normally open contact of the changeover switch 26a, one buffer 32a of the level measurement unit 29, and the other buffer 32b.

When the frequency f is designated by the control unit 31, the sine waveform counter 28b for transmission receives the clock
Each time a clock signal is input from the 8g, the waveform memory 28
The address _{AS in a} is increased.

A _S = A _S + Nf (7) Specifically, as shown in equation (7), each time a clock signal is input, the designated address A _S increases by Nf.
Therefore, when the designated frequency f is high, the number of samples of the sine waveform of FIG. 3 decreases, and when the designated frequency f is low, the number of samples of the sine waveform of FIG. 3 increases. Therefore, the sine waveform signal corresponding to the designated frequency f is stored in the waveform memory 28a.
Output from

A sine waveform counter 2 for synchronous detection
8c also performs the same operation as the transmission sine waveform counter 28b. Further, a cosine waveform counter 28 for synchronous detection
d is a sine waveform counter 28 as shown in equation (8).
b, phase by 90 ° degrees to the address A _S designated by 28c specifying the address A _C advanced.

A _C = A _C + Nf + A _{M / 4} (8) Accordingly, a cosine waveform signal corresponding to the designated frequency f is output from the waveform memory 28a.

The changeover switches 28e and 28f are connected to the control unit 3
By means of 1, the terminals a, b and d are sequentially switched and controlled in synchronization with the switching signal earlier than the clock oscillator 28g. Accordingly, the sine waveform signal a ₁ for transmission, the sine waveform signal b ₁ for synchronous detection, and the cosine waveform signal c ₁ for synchronous detection are time-divided from the waveform memory 28 a and transmitted to the buffers 28 h, 32 a, and 32 b. Is done.

A ₁ = b ₁ = sin2πft (9) c ₁ = cos2πft (10) The amplitude is normalized to [1].

The sine waveform signal a ₁ for transmission is stored in the buffer 2
Switch 26a switched to the normally open side via 8h
Is converted into an analog sine waveform signal a ₁ by a D / A converter 27 a via a signal line 3 a and a resistance attenuator 2.
2. The signal is again converted into a digital value by the A / D converter 24b via the signal line 3b. And the changeover switch 26
The signal is input into the level measuring unit 29 via the normally open terminal b.

When the sine waveform signal a ₁ is input to the level measuring section 29, the signal lines 3a. To via the signal line 3 consisting 3b, the signal waveform indicated by (9) in order to attenuate and delay, and changes in the received signal a ₂ shown by (11).

A ₂ = A sin (2πft + φ) (11) Second multiplication circuits 33a, 33
b, a pair of LPFs 34a and 34b, a pair of squaring circuits 35a and 35b, and one adding circuit 36.

The first multiplier circuit 33a is a multiplication value of a sine wave signal b ₁ for synchronous detection output from the reception signal a ₂ and a buffer 32a which receives digitally calculating the output as a multiplication signal d ₁ I do.

D ₁ = A sin (2πft + φ) sin2πft = − (A / 2) cos (4πft + φ) − (A / 2) cosφ (12) Similarly, the second multiplier circuit 33b receives the received signal a ₂
And a multiplication value of the cosine waveform signal c ₁ for synchronous detection output from the buffer 32b and digitally computing, and outputs as a multiplication signal e _1.

E ₁ = A sin (2πft + φ) cos2πft = − (A / 2) sin (4πft + φ) + (A / 2) sinφ (13) Then, the LPFs 34a,
34b, only the DC components A cos φ and A sin φ of the multiplied signals d ₁ and e ₁ are extracted. Each of the extracted DC components is converted into a squaring circuit 35 constituted by the following digital circuit.
a and 35b are also squared. Each squaring circuit 35
The square values output from a and 35b are added by an adding circuit 36 constituted by the following digital circuit.

Therefore, the n-bit digital output signal g ₁ output from the excitation circuit 36 to the next Fourier transform unit 30 has the square value of the amplitude A as shown in the equation (14).

[0049] _{g 1 = [(A / 2} ) cosφ] 2 + [(A / 2) sinφ] 2 = A 2/4 ... (14) only precisely measured amplitude A of the received signal a ₁ thus it can.

Therefore, when the control unit 31 changes the frequency f designated to each of the waveform counters 28b to 28d from the lower limit frequency to the upper limit frequency of the measurement frequency range, the Fourier transform unit 30 sets the signal line 3 as the line to be measured. Frequency characteristics can be obtained.

When the Fourier transform unit 30 obtains the frequency characteristic for the signal line 3, the frequency characteristic is converted into the inverse characteristic, the frequency characteristic of the inverse characteristic is inversely Fourier-transformed, and the time response characteristic corresponding to each frequency is obtained. calculate. Then, this time response characteristic is set in each digital filter 25a, 25b inserted in each signal line 3a, 3b.

As described above, since the frequency characteristic setting processing for the equalizer 21 is completed, the resistance attenuator 22 is replaced with the original terminal 2, and the changeover switches 26a and 26b are returned to the normally closed contact side. Thus, normal communication work is performed between the telephone station 1 and the terminal 2 via the signal line 3.

In the line characteristic measuring device having such a configuration, a sine waveform signal a ₁ for transmission for transmission to the signal line 3 output from the oscillator 28 and a sine waveform signal b ₁ for synchronous detection. and cosine waveform signal c ₁ of the synchronous detection is generated by reading the peak value stored in each address of one of the waveform memory 28a sequentially in synchronization with the clock signal.

Therefore, the above three waveform signals a ₁ and b
_Since the frequency f and phase of ₁ and c ₁ are digitally determined, no error occurs between the signals and no beat is generated. As a result, a stable digital high-precision level measuring unit 29 can be obtained without generating circuit noise or heat. Therefore, a Fourier transform unit 30 performs an inverse Fourier transform using the digital frequency characteristic data obtained from the level measuring unit 29, and sets the frequency characteristics of the equalizer 21 to the digital filters 25a and 25b. It is the line characteristic measuring device most suitable for processing.

Further, since the PLL circuit 7 composed of a large number of analog circuit members is not used unlike the conventional selective level meter shown in FIG. 5, the equalizer 21 is used as shown in FIGS. Can be constituted by digital circuits. Therefore, complicated adjustment work before measurement, which is necessary for the analog circuit, can be greatly reduced. Therefore, the work efficiency of the measurement can be greatly improved.

Further, as compared with the conventional measuring device shown in FIG. 5, the circuit configuration is simplified by removing the analog circuit. Further, by digitizing the circuit, a large number of circuits can be incorporated into one LSI or the like, and the size and weight of the entire device can be reduced.
As a result, manufacturing costs can be reduced.

The present invention is not limited to the above embodiment. For example, in the embodiment, the sine waveform counter 28b for transmission and the sine waveform counter 28c for synchronous detection are separately provided. However, by using one sine waveform signal in common, these can be combined by one counter. It is possible to realize.

[0058]

As described above, according to the line characteristic measuring apparatus of the present invention, a signal for transmission and a signal for synchronous detection to be applied to a line to be measured are realized by one waveform memory. I have. Therefore, no beat is generated between these signals, and no noise or the like of the circuit is generated. Therefore, the measurement accuracy can be greatly improved. In addition, since it can be realized by a digital circuit, complicated adjustment work before operation can be simplified, and measurement work efficiency is greatly improved. Furthermore, each circuit can be integrated, and the entire device can be reduced in size and weight.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a line characteristic measuring device according to one embodiment of the present invention.

FIG. 2 is a block diagram showing an equalizer into which the device of the embodiment is incorporated.

FIG. 3 is a view showing storage contents of a waveform memory in the apparatus of the embodiment.

FIG. 4 is a schematic diagram showing a general telephone line.

FIG. 5 is a block diagram showing a conventional level measuring device.

[Description of Signs] 1 ... Telephone office, 2 ... Terminal, 3 ... Signal line, 3a, 3b ...
Signal line, 21: equalizer, 22: resistance attenuator (coupler),
25a, 25b ... digital filters, 26a, 26b,
28e, 28f: changeover switch, 28a: waveform memory,
28b, 28c: sine waveform counter, 28d: cosine waveform counter, 33a: first multiplier circuit, 33b: second multiplier, 34a, 34b: LPF, 35a, 35b
... a squaring circuit, 36 ... an adding circuit.

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hitoshi Hiraike 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Keiichi Shibata 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Inside Nippon Telegraph and Telephone Corporation (72) Kazuhide Tokumaru 1-6-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Isao Ishikura 4-19-7 Kamata, Ota-ku, Tokyo Ando (56) References JP-A-57-147361 (JP, A) JP-A-60-58728 (JP, A) JP-A-3-96870 (JP, A) (58) Fields studied (Int .Cl. ⁶ , DB name) G01R 27/28 H04B 17/02

Claims (1)

(57) [Claims] 1. A connection for terminating an upstream transmission line (3b) and a downstream transmission line (3a) with a predetermined impedance at the far end of a four-wire circuit under test (3), and folding each line. Table (22)
And a waveform memory (28a) for storing a sine waveform, and a sine for outputting a sine waveform signal by designating each address in the waveform memory in an order corresponding to the measurement frequency (f) in synchronization with the read clock signal. A cosine waveform counter (28b, 28c) for outputting a cosine waveform signal by specifying each address in the waveform memory in an order corresponding to the measurement frequency in synchronization with the read clock signal;
d) and a first multiplication circuit (33a) for calculating a multiplication value of the sine waveform signal output from the waveform memory and passing through the circuit under test and the coupler and the sine waveform signal output from the waveform memory. And output from the waveform memory,
A second multiplication circuit (33b) for calculating a multiplication value of a sine waveform signal passed through the circuit under test and the coupler and a cosine waveform signal output from the waveform memory;
A pair of low-pass filters (34a and 34b) for extracting a DC component of each multiplied signal output from the second multiplication circuit, and a pair of low-pass filters for calculating a square value of each DC component output from the pair of low-pass filters A squaring circuit (35a, 35b) and an adding circuit for adding each square value calculated by the pair of squaring circuits
(36) A line characteristic measuring device comprising: