JPH044633A - Clock extraction circuit - Google Patents

Abstract

PURPOSE:To realize digital communication with less error by using a band pass filter passing a frequency component in the vicinity of a clock frequency in addition to a surface acoustic wave filter extracting the clock frequency component. CONSTITUTION:One of data signals inputted from a data signal input terminal 1 is inputted as it is to an exclusive OR element 3, and the other is inputted to the exclusive OR element 3 with a delay of a minute time DELTAt with respect to one data length T. A signal C being an output of the exclusive OR element 3 is an edge pulse signal. Only the frequency component in the vicinity of the clock frequency is extracted by giving the edge pulse signal to a band pass filter 4. When the signal is given to a surface acoustic wave filter 5, a sinusoidal wave signal of the clock frequency with less phase jitter is obtained. An excess sinusoidal frequency component is eliminated by giving the sinusoidal wave signal to an amplifier 6 snd a band pass filter 7, then the sinusoidal wave signal of the clock frequency with less jitter is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a clock extraction circuit used in digital communications and the like.

BACKGROUND OF THE INVENTION In recent years, digital communications have become widespread to the consumer level, including the practical use of 15DN. In digital communication, in order to identify a sent data signal, a clock signal synchronized with the transmission speed and phase of the data signal is required. If the phase of the clock signal is temporally unstable, the data signal cannot be accurately identified.

For the reasons mentioned above, there is a need for a technique for extracting from the data signal a clock signal that is synchronized with the phase of the data signal and has a temporally stable phase.

An example of a conventional clock extraction circuit will be described below with reference to the drawings. Figure 8 shows the circuit configuration of a conventional black/7 extraction circuit, and Figures 9 (a) to (f)
is a signal waveform diagram showing the operation.

In FIG. 8, 19 is an input terminal for a data signal, and 20 is an input terminal for inputting the input data signal for a minute time Δt with respect to the data period T.
21 is an exclusive OR element, 22
23 is an amplifier for amplifying the clock frequency component; 24 is a minter for limiting the amplitude of the clock frequency component; 25 is a surface acoustic wave filter for extracting the frequency component;
is a clock signal output terminal.

The operation of the clock extraction circuit configured as above will be described below with reference to FIGS. 8 and 9. The input signal is the NrZ code (hereinafter N
RZ code). One of the signal I, which is the data signal shown in FIG. 9, inputted from the data signal input terminal 19 shown in FIG. The signal is input to the exclusive OR element 21 with a delay of Δt. The output of the exclusive OR element 21 is a signal such that a pulse signal is generated at a change point of the signal I, as shown in FIG. (hereinafter referred to as an edge pulse signal) The edge pulse signal has an emission line spectrum of a necessary lock frequency, and by passing the edge pulse signal through a surface acoustic wave filter 22, a sine wave signal of a desired clock frequency synchronized with the phase of the data signal is generated. can be extracted. The sine wave signal is passed through the amplifier 23 to increase the amplitude as signal M, and then the limiter 2
By limiting the amplitude with 4, the desired clock signal N
can be obtained. The clock signal N is output from the clock signal output terminal 25 (for example, see "Digital Communication Technology" by Kimio Tanaka, Tokai University Press, pages 165-168).

Problems to be Solved by the Invention The surface acoustic wave filter 22 used here is necessary, and is a bandpass filter with a relatively high Q and narrow passband width near the frequency of the lock signal, but due to its structure. Due to this characteristic, it is not possible to sufficiently attenuate the signal in frequency components other than the vicinity of the clock frequency, and extra frequency components leak. This poses a problem in that extra frequency components are added to the extracted sine wave signal, resulting in increased phase jitter. In view of the above-mentioned problems, the present invention prevents the mixing of extra frequency components into the clock signal by using a band-pass filter whose purpose is to extract frequency components near the lock frequency and attenuate the extra frequency components when necessary. The purpose is to obtain a clock signal with less jitter.

Means for Solving the Problems In order to solve the above problems, the clock extraction circuit of the present invention includes a bandpass filter that extracts a frequency component near the clock frequency, a surface acoustic wave filter that extracts the clock frequency component, and a clock frequency component of the clock frequency. This device is characterized by being comprised of an amplifier that increases the amplitude of the component and a limiter that limits the amplitude of the amplified clock frequency component.

Effect of the Invention With the above-described configuration, the present invention can remove extra frequency components from the extracted clock signal using a band-pass filter, and extract a clock signal with less jitter. As a result, by using the clock signal for data identification, identification errors are reduced and data signals can be accurately transmitted.

Embodiments Hereinafter, embodiments of the clock extraction circuit of the present invention will be described with reference to the drawings.

Embodiment 1 First, FIG. 1 shows the circuit configuration of a clock extraction circuit according to an embodiment of the present invention. FIG. 2 is a signal waveform diagram showing the circuit operation of FIG. 1. Figure 3 is a frequency characteristic diagram of the surface acoustic wave filter in Figure 1, Figure 4 is a frequency amplitude characteristic diagram of the bandpass filter in Figure 1, and Figure 5 is a diagram of the bandpass filter and surface acoustic wave filter in Figure 1. FIG. In FIG. 1, 1 is a data signal input terminal, 2 is a delay element that delays the data cycle length T by a minute time Δt, 3 is an exclusive OR element, and 4 is a bandpass filter that extracts frequency components near the clock frequency. , 5 is a surface acoustic wave filter for extracting the clock frequency component, 6 is an amplifier for amplifying the clock frequency component, and 7 is a band pass filter, which is the same as 4. A limiter 19 8 limits the amplitude of the amplified clock frequency component is a clock signal output terminal. In FIGS. 3, 4 and 5, fo is the frequency of the necessary lock signal.

The operation will be explained below with reference to FIGS. 1, 2, 3, 4, and 5.

The data signal input now is an NR signal like signal A in Figure 2.
Suppose it is a Z code signal. In FIG. 1, one of the data signals shown as signal A in FIG. As shown in FIG. 3, the signal is input to the exclusive OR element 3 with a delay of a minute time Δt. Signal C, which is the output of exclusive OR element 3, becomes an edge pulse signal. The edge pulse signal has an emission line spectrum with a lock frequency as required, and is passed through a bandpass filter 4 having frequency characteristics as shown in FIG.
Only frequency components near the clock frequency are extracted, and a sine wave of the clock signal frequency becomes a signal with some phase jitter, like a signal. When this signal is passed through the surface acoustic wave filter 5, the surface acoustic wave filter becomes a high-Q bandpass with an extremely narrow passband width centered around the clock frequency in the vicinity of the lock frequency, as shown in section A in Figure 3. It is a filter, and the output signal is a sine wave signal of a clock frequency with little phase jitter, such as signal E. After passing the sine wave signal through an amplifier 6 to make it into a sine wave signal with a large amplitude such as signal F, the signal is passed through a band pass filter 7 to remove the extra frequency components remaining in the signal F and create a clock with even less jitter. The signal G is a sine wave signal of the frequency. By limiting the amplitude level of the signal G, a clock signal, like the signal H, with less phase jitter and matching the phase of the data signal can be obtained. The clock signal is output from the clock signal output terminal 9.

As shown in the frequency amplitude characteristic diagram of FIG. 3, the surface acoustic wave filter 5 has excess signal leakage in frequency components other than the vicinity of the clock frequency, which causes jitter. On the other hand, the frequency and amplitude characteristics of the bandpass filters 4 and 7 are as shown in Fig. 4, and they have a relatively low Q and a slight passband width centered around the necessary long signal frequency, but for other frequencies. has sufficient stopping power. FIG. 5 is a comprehensive frequency and amplitude characteristic diagram of the bandpass filter 4.7 and the surface acoustic wave filter 5 in FIG. As shown in FIG. 5, it is a bandpass filter with a narrow bandwidth at the clock frequency, and other frequency components are sufficiently attenuated. By having such characteristics, a pure sine wave signal having only lock frequency components can be extracted. By amplifying and limiting the amplitude of this sine wave signal, a clock signal with less phase jitter can be extracted.

Embodiment 2 An embodiment of a double-tuned circuit used as a bandpass filter of a clock extraction circuit according to the present invention will be described below with reference to the drawings.

FIG. 6 shows the circuit configuration of the double-tuned circuit. 7th
The figure shows the frequency characteristics of a double-tuned circuit. In the seventh time, fo is the necessary lock frequency. In Figure 6, 10.11 is a signal input terminal, 12 is an inductance of 1 and has a value of Ll (H), 13 is a capacitance of 1 and has a value of 01 (F), 14 is a capacitance M, and 15 is a capacitance. 2 has a value of C2 (F), 16 has an inductance of 2 and has a value of L2 (F), and 17.18 is a signal output terminal.

Inductance 1 and capacitance 1. Inductance 2 and capacitance 2 each constitute a parallel resonant circuit, and its resonant frequency f. is f0=1/2πf〒4下11/2π■Katana]〒7, and the above f. matches the clock frequency. The two coupled parallel resonant circuits are coupled by a capacitance M, and their frequency characteristics are as shown in FIG. As shown in FIG. 7, the frequency amplitude characteristics within the band can be flattened, and frequency components outside the band can be sufficiently attenuated.

Therefore, when used in the clock extraction circuit of the present invention, it does not affect the frequency characteristics near the clock frequency of the surface acoustic wave filter, and can sufficiently block extra frequency components, reducing the phase jitter of the reproduced clock signal. can be done.

Effects of the Invention As described above, in the present invention, in addition to the surface acoustic wave filter that extracts the clock frequency component, a bandpass filter that passes frequency components near the clock frequency is used, thereby eliminating the excess frequency of the extracted clock signal. It is possible to remove the components and extract a clock signal with less phase jitter.

As a result, by using the clock signal for data identification, digital communication with fewer errors can be realized, and its industrial value is extremely large.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a clock extraction circuit according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram showing the operation of a clock extraction circuit according to an embodiment of the present invention, and FIG. 3 is a diagram showing the elasticity in FIG. 1. The frequency amplitude characteristic diagram of the surface wave filter, Fig. 4 is the frequency amplitude characteristic diagram of the band pass filter in Fig. 1, and Fig. 5
The figures are a comprehensive frequency amplitude characteristic diagram of the surface acoustic wave filter and bandpass filter in Fig. 1, Fig. 6 is a circuit diagram of an embodiment of the double-tuned circuit used in the bandpass filter of the clock extraction circuit of the present invention, and Fig. 7 8 is a diagram showing the frequency amplitude characteristic of the double-tuned circuit, FIG. 8 is a circuit configuration diagram of a conventional clock extraction circuit, and FIG. 9 is a signal waveform diagram showing the operation of the conventional clock extraction circuit. 1...Data signal input terminal, 2...Delay element, 3...Exclusive OR element, 4...
... Bandpass filter, 5 ... Surface acoustic wave filter, 6 ... Amplifier, 7 ... Bandpass filter, 8 ... Riminter, 9.
... Clock signal output terminal, 10 ... Signal input terminal, 11 ... Signal input terminal, 12 ...
...Inductance 1.13 ... Capacitance 1.14 ... Capacitance M, 15.
...Capacitance 2.16...Inductance 2.17...Signal output terminal, 18...
...Signal output terminal, 19...Data signal input terminal, 20...Delay element, 21...
Exclusive OR element, 22...Surface acoustic wave filter, 23...Amplifier, 24...Limiter-125...Clock signal output terminal. Name of agent: Patent attorney Shigetaka Awano Haka1 person t-4
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Claims (2)

[Claims] (1) In a clock extraction circuit that extracts a clock signal from a data signal, a bandpass filter that extracts frequency components near the clock frequency, a surface acoustic wave filter that extracts the clock frequency component, and an amplifier that amplifies the clock frequency component. and a limiter that limits the amplitude of the clock frequency component. (2) Claim (1) characterized in that the bandpass filter is composed of one or more double-tuned circuits.
The clock extraction circuit described.