JPH02276065A - Spindle servo circuit - Google Patents

Abstract

PURPOSE:To satisfactorly control a spindle motor with high accuracy in synchronization with a video signal to be recorded by multiplying a frequency signal from a frequency signal generator by means of a phase locked loop circuit, then dividing it, and obtaining the rotational error information from the spindle motor based on the phase difference between a frequency divided signal and a horizontally synchronizing signal or a vertically synchronizing signal. CONSTITUTION:A PLL circuit 30, which multiplies a frequency signal from a frequency signal generator 21 by a value corresponding to a horizontal scanning period for one field of the video signal, and frequency dividers 24 and 25, which divide the output signal of the PLL circuit, are provided. Further as the output signals of the frequency dividers 24 and 25, the signal in the prescribed cycle synchronizing with the horizontally or vertically synchronizing period of the video signal, is obtained. In addition, the phase difference between the signal in the prescribed cycle and the horizontally synchronizing signal or the vertically synchronizing signal to be the reference of the video signal is detected by comparators 8 and 9, and the rotational error information of a spindle motor 2 is obtained. Thus the spindle motor can be controlled with high accuracy in synchronization with the video signal to be recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video disc recording device that records video signals on a disc, and particularly to a spindle servo circuit that controls a spindle motor that rotates the disc.

[Summary of the invention]

The present invention provides a spindle servo circuit for a video disk recording device that generates frequency signals from a frequency signal generator that generates frequency signals synchronized with the rotation of a spindle motor in a number corresponding to the horizontal scanning period of one field of a video signal. The frequency is multiplied by a phase-locked loop circuit and then divided, and spindle motor rotation error information is obtained from the phase difference between the frequency-divided signal and the reference horizontal or vertical synchronization signal. Using the output frequency signal generator, it is possible to control the spindle motor with high precision and in synchronization with the video signal to be recorded.

[Conventional technology]

Conventionally, in the case of recording devices that record video signals on disks such as optical disks and magneto-optical disks, in order to align the recording state of video signals on each track on the disk, a rotational phase is set on the rotating shaft of a spindle motor that rotates the disk. A frequency signal generator was installed to detect the frequency signal, and video signals were recorded while controlling the rotational phase of the disk based on the frequency signal from the frequency signal generator.

FIG. 2 is a diagram showing a spindle servo circuit of this conventional video disk recording apparatus, and (1) in the figure shows an optical disk on which a video signal is recorded by a laser beam. This optical disc (1) records video signals on each track at a constant rotational speed, and records one frame (two fields) of video signals in one track (one round). The optical disc (1) is placed on a turntable connected to the rotating shaft (3) of a spindle motor (2), and the optical disc (1) is rotated at a predetermined speed. In this case, a frequency detection annular member (4a) constituting a frequency signal detector (4) is fixed to the rotating shaft (3) of the spindle motor (2), and the circumferential surface of this annular member (4a) Magnetic materials and the like are arranged at predetermined intervals. Then, this annular member (4
A signal generating section (4b) of this frequency signal generator (4) is arranged close to the circumferential surface of a). By doing this, when the optical disc (1) is rotated by the drive of the spindle motor (2), the annular member (4a) rotates in conjunction, and the signal generator (4b) is activated by the optical disc (1). A frequency signal is output in which one cycle is a rotation of a predetermined angle. In this case, the frequency signal generator (4) is the disk (1).
A device that outputs a frequency signal of about 300 cycles per revolution is used.

Then, the output signal of this frequency signal generator (4) is converted into a phase-locked loop circuit (hereinafter referred to as PLL circuit).
(5), and this PLL circuit (5) increases the frequency of the signal supplied from the frequency signal generator (4) several times. The output signal of the 20 PLL circuit (5) is supplied to the first frequency divider (6) and frequency-divided by a predetermined ratio, and a frequency approximately equal to the horizontal synchronization signal of the video signal to be recorded as a frequency-divided signal is obtained. Get a signal. Further, this frequency-divided signal is supplied to a second frequency divider (7), and is subjected to second frequency division to obtain a signal having a frequency substantially equal to the frequency of the vertical synchronization signal of the frame period of the video signal to be recorded.

Then, the frequency-divided signal of the first frequency divider (6) is supplied to the first phase comparator (8), and the frequency-divided signal of the second frequency divider (7) is supplied to the second phase comparator ( 9). In addition, a horizontal synchronization signal H, which serves as a reference output from a time base collector (10) that performs time axis correction of a video signal to be recorded on an optical disc (1), is supplied to a first phase comparator (8), and this time A vertical synchronization signal (2) with a reference frame period output from the base collector (10) is supplied to the second phase comparator (9).

Then, the first phase comparator (8) compares the phase difference between the frequency-divided signal and the horizontal synchronization signal H, and converts the error signal into a phase compensation circuit (
11) and then supplied to one input terminal of an adder (13). In addition, the second phase comparator (9) compares the phase difference between the frequency division signal and the vertical synchronization signal (■) of the frame period, and after the error signal is phase compensated by the phase compensation circuit (12), the adder (13 ) to the other input terminal. Then, the adder (13) adds both error signals,
The addition signal is supplied to the motor drive circuit (14). This motor drive circuit (14) adjusts the rotational phase of the optical disk (1) by the spindle motor (2) based on the amount of error indicated by the addition signal of the error signals.

With this configuration, the rotational phase of the optical disc (1) is synchronized with the horizontal synchronization signal and vertical synchronization signal of the video signal to be recorded, and the recording of the video signal on the optical disc (1) can be performed in a good manner in a predetermined state. It will be done.

[Problem to be solved by the invention]

However, when realizing such a spindle servo circuit, one of the disks (1) is transmitted from the frequency signal generator (4).
It is necessary to generate a frequency signal of about 300 cycles per rotation. For example, if the optical disk (1) is rotated approximately 30 times per second, it is necessary to generate a frequency signal of approximately 9 kHz, and a frequency signal generator (4) is required to generate such a high frequency signal with high precision. This requires special equipment, which is very expensive and requires a lot of effort to adjust.

The reason why the frequency is increased by the PLL circuit (5) and then divided by the first frequency divider (6) is that the horizontal synchronization of the video signal is performed as the output of the first frequency divider (6). This is because a signal synchronized with the signal is required, and the horizontal scanning period is not an integer every time the disk (1) rotates half a rotation and one field period elapses.

For example, in the case of the NTSC system, the horizontal scanning period of one field is 262.5, and if the frequency signal generator (4) outputs a signal with 300 periods per rotation, the frame frequency is 29.97 Hz, so the frequency The output frequency of the signal generator (4) is 300x29.97=8991 seconds. This approximately 9kHz signal is processed by the PLL circuit (5) by 3
By increasing the frequency of the signal five times (315 kHz) and then dividing this signal by one, a signal having the same frequency as the horizontal synchronization signal of 15.734 kHz can be obtained.

Here, for example, if the frequency signal generator (4) can output a signal with a period that is not an integer multiple in one rotation, the frequency of the output signal can be lowered, but the frequency signal generator (4) with a period that is not an integer ratio can be configured. It is difficult to do so.

In view of the above, it is an object of the present invention to provide a spindle servo circuit of this type that can be well controlled using a frequency signal generator with a low output frequency.

[Means to solve the problem]

The spindle servo circuit of the present invention is a spindle servo circuit that controls a spindle motor (2) that rotates a disk (1) on which a video signal is recorded, as shown in FIG. a frequency signal generator (21) that generates a synchronized frequency signal;
A PLL circuit (30) that multiplies the frequency signal from the frequency signal generator (21) by a number corresponding to the horizontal scanning period of one field of the video signal, and a PLL circuit (30) that divides the frequency of the output signal of the PLL circuit (30). A frequency divider (24), (25) is provided, and a signal of a predetermined period synchronized with the horizontal period or vertical period of the video signal is obtained as an output signal of the frequency divider (24), (25). A comparator (8
) and (9), and rotation error information of the spindle motor (2) is obtained from the detected phase difference.

[Effect]

According to such a configuration, one of the video signals in the PLL circuit (30)
Since the frequency is multiplied by a number corresponding to the horizontal scanning period of the field, even if the frequency of the signal generated by the frequency signal generator (21) is lowered, the horizontal period is still the same as the frequency divided signal by the frequency dividers (24) and (25). Or, the frequency of the vertical period can be obtained.

[Embodiment] Hereinafter, an embodiment of the spindle servo circuit of the present invention will be described with reference to FIG. In this Figure 1, the second
Portions corresponding to those in the figures are given the same reference numerals, and detailed explanation thereof will be omitted.

In FIG. 1, (21) indicates a frequency signal generator,
In this example, the rotating shaft (3) of the spindle motor (2)
a frequency signal generating annular member (21a) attached to the annular member (21a), and a signal generating part (21a) adjacent to the annular member (21a).
The frequency signal generator (21) consisting of (b) is configured to output a frequency signal of 32 cycles per rotation of the disk (1).

Then, the output signal of this frequency signal generator (21) is
PL via the amplifier (22) and waveform shaping circuit (23)
It is supplied to the phase comparator (31) of the L circuit (30).

This PLL circuit (30) supplies the output signal of the phase comparator (31) to a voltage controlled oscillator (33) via a low-pass filter (32), and converts the oscillation signal of this voltage controlled oscillator (33) into a counter ( 34) and this PL
This is the output signal of the L circuit (30). And the counter (
34) supplies a count signal obtained by counting the oscillation signals to the gate circuit (35), and when the gate circuit (35) detects that this count value has reached a predetermined number, supplies a reset signal to the counter (34). . This gate circuit (3
5) The detection of the count value is controlled by the broadcasting system switching signal obtained at the terminal (36), and when the signal obtained at the terminal (36) indicates that the video signal to be recorded is of the JITsc system, the count value is detected by the signal obtained at the terminal (36). A reset signal is output every time the count value reaches 262, and when the PAL system is indicated, a reset signal is output every time the count value reaches 312. Then, the counter (34) is activated by the reset signal.
Each time the counter (34) is reset, this counter (34) outputs a pulse signal once, and this pulse signal is sent to the phase comparator (31).
), and a phase comparator (31) compares the phase of this pulse signal with the output signal of the waveform shaping circuit (23).

In this case, the reset signal output by the gate circuit (35) is also supplied to the flip-flop (37), and each time the reset signal is supplied, the high-level signal "'1" is output as the output signal of this flip-flop (37). The change between ``'' and the low level signal ``0'' is repeated. The counter (34) stops counting the oscillation signal only once every time the high level signal "1"' is supplied from the flip-flop (37). In this way, the PLL circuit (30) is activated. By configuring this, for example, when the NTSC system is instructed by the signal obtained at the terminal (36), the pulse signal output from the counter (34) will be the oscillation signal of the voltage controlled oscillator (33) with 262 cycles. Tokito, 26
Output is performed alternately with the output when three cycles have been reached. That is, a pulse signal is outputted once every 262.5 periods on average. Furthermore, when the PAL system is instructed by the signal obtained at the terminal (36), the pulse signal output from the counter (34) is such that the oscillation signal of the voltage controlled oscillator (33) is
Output is performed alternately when 2 cycles have been reached and when 313 cycles have been reached. That is, a pulse signal is outputted once every 312.5 periods on average.

The PLL circuit ( 30) is this frequency signal generator (21)
A signal with a frequency 262.5 times or 312.5 times that of the output signal is output.

(2) The output signal of this PLL circuit (30) is then supplied to a first frequency divider (24) which divides the frequency into - to obtain a -frequency-divided signal. Furthermore, this -frequency-divided signal is supplied to a second frequency divider (25), and switching of this second frequency divider is performed to broadcast the video signal to be recorded on the disk (1). If the broadcast system of the video signal to be recorded is PAL, the frequency-divided signal of the first frequency divider (24) is supplied to the first phase comparator (8), and the frequency-divided signal of the second frequency divider (25) is The frequency signal is supplied to a second phase comparator (9). And the timebase collector (1
The reference horizontal synchronization signal H output by the time base collector (8) is supplied to the first phase comparator (8), and the time base collector (
A vertical synchronizing signal (2) with a frame period as a reference outputted by the device (10) is supplied to the second phase comparator (9).

Then, the first phase comparator (8) compares the phase difference between the frequency-divided signal and the horizontal synchronization signal H, and converts the error signal into a phase compensation circuit (
11) and then supplied to one input terminal of an adder (13). In addition, the second phase comparator (9) compares the phase difference between the frequency division signal and the vertical synchronization signal (■) of the frame period, and after the error signal is phase compensated by the phase compensation circuit (12), the adder (13 ) to the other input terminal. Then, the adder (13) adds the difference signals between the two prefectures,
The added signal is supplied to the motor drive circuit (14), and based on the amount of error indicated by the added signal, the spindle motor (
The rotational phase of 1) is adjusted on the optical disc according to 2).

Next, the operation when performing spindle servo using such a configuration will be explained. For example, if an NTSC video signal with a frame frequency of 29.97 Hz is recorded on the optical disc (1), the PLL circuit (30) has a frame frequency of 262.5 Hz. A double frequency signal is output, and the second frequency divider (25) is set to perform frequency division. In this state, the frequency signal generator (2
1) outputs a frequency signal of 32 cycles per revolution of the disk (1), so the output signal frequency of this frequency signal generator (21) is 29.97X32=959.041(z
becomes. And the PLL circuit (30) is 262.5
Since the frequency is doubled, the frequency divider number of the first frequency divider (24) is 959.04 X 262.5 X-= 1
The frequency is 5734.25Hz, which is the frequency of the horizontal synchronization signal of the NTSC system. Then, divide this horizontal period by a frequency divider (2
A highly accurate error signal is obtained based on the phase difference between the output signal of step 4) and the reference horizontal synchronization signal from the time base collector (10).

Further, the output signal of the first frequency divider (24) is multiplied by a second frequency, which becomes the frequency of the vertical synchronization signal of the frame period of the NTSC system. Then, the output signal of the frequency divider (25) of this frame period and the time base collector (1
A highly accurate error signal can be obtained based on the phase difference between the frame period and the reference vertical synchronization signal of 0).

Then, spindle servo for recording an NTSC video signal is performed using the sum signal of each error signal.

In addition, when recording a PAL video signal with a frame frequency of 25] (z on the optical disc (1), the PLL circuit (30) outputs a frequency signal 312.5 times as high as the frequency signal, and in this state, the second frequency signal is generated. The container (21) is the disk (1)
Since a frequency signal of 32 periods is output in one rotation of the frequency signal generator (21), the output signal frequency of this frequency signal generator (21) is 25
X 32 = 800Hz. Then, the PLL circuit (30) converts the frequency to 312°5 times, so the first
The frequency divided signal of the frequency divider (24) is 800 x 312.
5 x −=156257, which is the frequency of the horizontal synchronizing signal of the PAL system. Then, the output signal of this horizontal period frequency divider (24) and the time base collector (10
) A highly accurate error signal can be obtained based on the phase difference with the reference horizontal synchronization signal.

Further, a second signal is obtained from the output signal of the first frequency divider (24), and becomes the frequency of the vertical synchronization signal of the frame period of the PAL system. Then, a frequency divider (2
A highly accurate error signal is obtained based on the phase difference between the output signal of 5) and the reference vertical synchronization signal of the frame period from the time base collector (10).

Then, spindle servo for recording a PAL video signal is performed using the sum signal of each error signal.

In this way, according to the spindle servo circuit of this example, PL
Since the L circuit (30) performs multiplication that is not an integer multiple corresponding to the horizontal scanning period of one frame of the video signal, the output frequency signal of the frequency signal generator (21) can be set low; A general-purpose device with a simple configuration and easy adjustment can be used as the spindle servo circuit, and the manufacturing cost of the spindle servo circuit can be reduced.

Furthermore, the PLL circuit (30) has a simple configuration in which the count value of the counter (34) is controlled by a flip-flop (37), and outputs a frequency signal of 262.5 times or 312.5 times. , the circuit configuration is simple.

Furthermore, in this example, by simply switching the count value to be reset by this PLL circuit (3o) and the frequency division ratio of the second frequency divider (25), the video signal to be recorded can be set to the NTSC format or the PLL format.
It is possible to handle both AL system signals. Alternatively, video signals other than those of both types can be handled by changing the count value and the setting value of the frequency division ratio.

In the above embodiments, an optical disc is used as the disc on which video signals are recorded, but it goes without saying that the present invention can be applied to spindle servo circuits of recording devices for various discs on which video signals are recorded. Furthermore, the present invention is limited to the above-described embodiments, and it goes without saying that various other configurations can be taken without departing from the gist of the present invention.

〔Effect of the invention〕

According to the present invention, there is an advantage that a spindle motor can be controlled with high precision and in good synchronization with a video signal to be recorded with a simple configuration using a normal frequency signal generator that generates a relatively low frequency signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a spindle servo circuit of the present invention, and FIG. 2 is a block diagram showing an example of a conventional spindle servo circuit. (1) is an optical disk, (2) is a spindle motor, (2)
1) is a frequency signal generator, (24) is a first frequency divider, (
25) is a second frequency divider, and (30) is a PLL circuit.

Claims (1)

[Scope of Claim] A spindle servo circuit that controls a spindle motor that rotates a disk on which video signals are recorded, comprising: a frequency signal generator that generates a frequency signal in synchronization with the rotation of the spindle motor; a phase-locked loop circuit that multiplies the frequency signal from the video signal by a number corresponding to the horizontal scanning period of one field of the video signal, and a frequency divider that divides the output signal of the phase-locked loop circuit; A signal with a predetermined period synchronized with the horizontal period or vertical period of the video signal is obtained as the output signal of the frequency generator, and from the phase difference between the signal with the predetermined period and the horizontal synchronization signal or vertical synchronization signal that is the reference of the video signal. , a spindle servo circuit configured to obtain rotation error information of the spindle motor.