JP2773224B2 - Spindle servo circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video disk recording apparatus for recording a video signal on a disk, and more particularly to a spindle servo circuit for controlling a spindle motor for rotating a disk.

[Summary of the Invention]

According to the present invention, in a spindle servo circuit of a video disk recording device, frequency signals from a frequency signal generator for generating a frequency signal synchronized with rotation of a spindle motor are generated by a number corresponding to a horizontal scanning period of one field of a video signal. After multiplying by the phase locked loop circuit and dividing,
The rotation error information of the spindle motor is obtained from the phase difference between the frequency-divided signal and the reference horizontal synchronization signal or vertical synchronization signal, and recording is performed using a frequency signal generator that outputs a relatively low frequency signal. This makes it possible to perform high-precision and good control of the spindle motor in synchronization with a video signal to be synchronized.

[Conventional technology]

2. Description of the Related Art Conventionally, in the case of a recording device that records a video signal on a disk such as an optical disk or a magneto-optical disk, in order to align the recording state of the video signal on each track on the disk, a rotation phase of a spindle motor for rotating the disk is used. A frequency signal generator for detecting the video signal is mounted, and the video signal is recorded while controlling the rotation phase of the disk based on the frequency signal from the frequency signal generator.

FIG. 2 is a diagram showing a spindle servo circuit of the conventional video disk recording apparatus. In FIG. 2, (1) shows an optical disk on which a video signal is recorded by a laser beam. This optical disk (1) records video signals on each track at a constant rotation speed, and records one frame (two fields) of video signals on one track (one round). The optical disk (1) is mounted on a turntable connected to a rotating shaft (3) of a spindle motor (2), and rotates the optical disk (1) at a predetermined speed. In this case, an annular member (4a) for frequency detection constituting a frequency signal detector (4) is fixed to the rotating shaft (3) of the spindle motor (2), and is mounted on the peripheral surface of the annular member (4a). Are magnetic materials arranged at predetermined intervals. And this annular member (4a)
The signal generator (4b) of the frequency signal generator (4) is arranged close to the peripheral surface of the signal generator. With this configuration, the optical disk (1) is rotated by the drive of the spindle motor (2), so that the annular member (4a) rotates in conjunction with the rotation,
The signal generator (4b) outputs a frequency signal having one cycle of rotation of the optical disc (1) at a predetermined angle. In this case, as the frequency signal generator (4), one that outputs a frequency signal of about 300 cycles in one rotation of the disk (1) is used.

Then, the output signal of the frequency signal generator (4) is
Phase locked loop circuit (hereinafter referred to as PLL circuit)
(5), and the frequency of the signal supplied from the frequency signal generator (4) is increased several times by the PLL circuit (5). The output signal of the PLL circuit (5) is supplied to a first frequency divider (6) to divide the signal by a predetermined ratio, and a signal having a frequency substantially equal to the horizontal synchronizing signal of the video signal to be recorded as the divided signal. Get. Then, the frequency-divided signal is further supplied to a second frequency divider (7), and the frequency-divided signal of the first frequency divider (6) is reduced to 1/525 by the second frequency divider (7). A signal having a frequency substantially equal to the frequency of the vertical synchronization signal in the frame period of the video signal to be divided and recorded is obtained.

Then, the frequency-divided signal of the first frequency divider (6) is supplied to the first phase comparator (8), and the frequency-divided signal of the second frequency divider (7) is supplied to the second phase comparator (8). 9). Further, a horizontal synchronizing signal H serving as a reference output from a time base collector (10) for correcting a time axis of a video signal recorded on the optical disk (1) is supplied to a first phase comparator (8). A vertical synchronizing signal V having a frame period serving as a reference and output from the base collector (10) is supplied to a second phase comparator (9).

Then, the first phase comparator (8) compares the phase difference between the frequency-divided signal and the horizontal synchronizing signal H, and after compensating the error signal by the phase compensation circuit (11), one of the adders (13) Supply terminal. Further, the second phase comparator (9) compares the phase difference between the frequency-divided signal and the vertical synchronizing signal V of the frame period. After compensating the error signal by the phase compensating circuit (12), the adder (13) ) To the other input terminal. Then, the two error signals are added by the adder (13), and the added signal is supplied to the motor drive circuit (14). The motor drive circuit (14) adjusts the rotation phase of the optical disc (1) by the spindle motor (2) based on the error amount indicated by the error signal addition signal.

With this configuration, the rotation phase of the optical disk (1) is synchronized with the horizontal synchronization signal and the vertical synchronization signal of the video signal to be recorded, and the recording of the video signal on the optical disk (1) can be performed in a predetermined state. Done.

[Problems to be solved by the invention]

However, when realizing such a spindle servo circuit, it is necessary to generate a frequency signal of about 300 cycles per rotation of the disk (1) from the frequency signal generator (4). For example, if the optical disk (1) is rotated about 40 times per second, it is necessary to generate a frequency signal of about 9 kHz, and a frequency signal generator (4) for generating such a high frequency signal with high accuracy Requires a special device, which is very expensive and requires a lot of trouble in adjustment.

The reason why the frequency is increased by the PLL circuit (5) and then divided by the first frequency divider (6) is that the horizontal frequency of the video signal is output as the output of the first frequency divider (6). This is because a signal synchronized with the signal is required, so that the horizontal scanning period does not become an integer every time one field period elapses by the half rotation of the disk (1).

For example, in the case of the NTSC system, the horizontal scanning period of one field is 262.5, and the frequency signal generator (4) operates three times per rotation.
If a signal with a period of 00 is output, the frame frequency is 2
Since the frequency is 9.97 Hz, the output frequency of the frequency signal generator (4) is 300 × 29.97 = 8991 Hz. After converting this 9kHz signal into a 35 times frequency signal (315kHz) by PLL circuit (5), this signal is divided into 1/20 to obtain a signal with the same frequency as the 15.734kHz horizontal synchronization signal. Can be

Here, for example, if the frequency signal generator (4) can output a signal having a period that is not an integral multiple in one rotation, the frequency of the output signal can be reduced, but a frequency signal generator having a period that is not an integer ratio can be configured. It is difficult to do.

SUMMARY OF THE INVENTION In view of the foregoing, an object of the present invention is to provide a spindle servo circuit of this kind which can perform good control by using a frequency signal generating signal having a low output frequency.

[Means for solving the problem]

As shown in FIG. 1, for example, a spindle servo circuit of the present invention controls a spindle motor (2) for rotating a disk (1) on which a video signal is recorded by controlling the rotation of the spindle motor (2). A frequency signal generator (21) for generating a synchronized frequency signal;
A PLL circuit (30) for multiplying the frequency signal from the frequency signal generator (21) by the number corresponding to the horizontal scanning period of one field of the video signal, and a component for dividing the output signal of the PLL circuit (30) Frequency dividers (24) and (25) are provided.
4) A signal of a predetermined cycle synchronized with the horizontal cycle or the vertical cycle of the video signal is obtained as the output signal of (25), and the position of the signal of the predetermined cycle and the horizontal synchronization signal or the vertical synchronization signal serving as the reference of the video signal is obtained. The phase difference is detected by the comparators (8) and (9), and rotation error information of the spindle motor (2) is obtained from the detected phase difference.

[Action]

According to such a configuration, the PLL circuit (30) performs multiplication by the number corresponding to the horizontal scanning period of one field of the video signal.
Even if the frequency of the signal generated by the frequency signal generator (21) is lowered, the frequency of the horizontal period or the vertical period can be obtained as a frequency-divided signal by the frequency dividers (24) and (25).

〔Example〕

Hereinafter, an embodiment of the spindle servo circuit of the present invention,
This will be described with reference to FIG. In FIG. 1, parts corresponding to those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 1, (21) shows a frequency signal generator,
In this example, the rotating shaft (3) of the spindle motor (2)
A frequency signal generating annular member (21a) attached to the
The frequency signal generator (21) composed of the annular member (21a) and the signal generator (21b) in proximity to the ring member (21a)
It is configured to output a frequency signal of 32 cycles per rotation.

Then, the output signal of this frequency signal generator (21) is
The signal is supplied to the phase comparator (31) of the PLL circuit (30) via the amplifier (22) and the waveform shaping circuit (23).

The PLL circuit (30) supplies an output signal of the phase comparator (31) to a voltage-controlled oscillator (33) via a low-pass filter (32), and outputs an oscillation signal of the voltage-controlled oscillator (33) to a counter ( 34) and the output signal of this PLL path (30). The counter (34) supplies a count signal obtained by counting the oscillation signal to the gate circuit (35). When the gate circuit (35) detects that the count value has reached a predetermined number, the counter (34) outputs a reset signal to the counter (34). ). The detection of the count value by the gate circuit (35) is controlled by the broadcast system switching signal obtained at the terminal (36), and indicates that the video signal recorded by the signal obtained at the terminal (36) is the NTSC system. When the count value is 26
A reset signal is output every time the count reaches 2, and when the PAL system is indicated, a reset signal is output every time the count value reaches 312. Each time the counter (34) is reset by the reset signal, this counter (34) becomes 1
A pulse signal is output, and the pulse signal is supplied to a phase comparator (31). The phase comparator (31) compares the phase of the pulse signal with the output signal of the waveform shaping circuit (23).

In this case, the reset signal output from the gate circuit (35) is also supplied to the flip-flop (37), and as the output signal of the flip-flop (37), every time the reset signal is supplied, the high-level signal "1" is output. And low level signal “0”
And so on. And the counter (34)
Is a high-level signal “1” from this flip-flop (37).
Is supplied once, the counting of the oscillation signal is stopped only once.

By configuring the PLL circuit (30) in this manner, for example, when the signal obtained at the terminal (36) indicates the NTSC system, the output of the pulse signal from the counter (34) is
The output when the oscillation signal of the voltage controlled oscillator (33) reaches 262 cycles and when it reaches 263 cycles are alternately performed. That is, a pulse signal is output once every 262.5 cycles on average. When the signal obtained at the terminal (36) indicates the PAL method, the pulse signal output from the counter (34) is output when the oscillation signal of the voltage-controlled oscillator (33) reaches 312 cycles. The output when the cycle is reached is performed alternately. That is, a pulse signal is output once every 312.5 cycles on average.

The phase comparator (31) compares the phase of the pulse signal with the frequency signal from the frequency signal generator (21) once every 262.5 cycles or 312.5 cycles, so that the PLL circuit (3
0) outputs a frequency signal 262.5 times or 312.5 times the output signal of the frequency signal generator (21).

The output signal of the PLL circuit (30) is supplied to a first frequency divider (24) that divides the frequency by 1/16 to obtain a signal that is 1/16 frequency-divided. Further, the 1/16 frequency-divided signal is supplied to a second frequency divider (25).
Frequency division or 1/625 frequency division is performed. This switching of the frequency division ratio is performed by dividing the video signal to be recorded on the disk (1) by 1/525 when the broadcast system of the video signal is the NTSC system and by the PAL system by the broadcast system of the video signal to be recorded on the disk (1). At some point, 1/625 frequency division is performed.

The frequency-divided signal of the first frequency divider (24) is supplied to the first phase comparator (8), and the frequency-divided signal of the second frequency divider (25) is supplied to the second phase comparator (8). 9). Then, a reference horizontal synchronizing signal H output from the time base collector (10) is supplied to the first phase comparator (8), and the vertical synchronization of the reference frame period output from the time base collector (10) is provided. The synchronization signal V is supplied to a second phase comparator (9).

Then, the first phase comparator (8) compares the phase difference between the frequency-divided signal and the horizontal synchronizing signal H, and after compensating the error signal by the phase compensation circuit (11), one of the adders (13) Supply terminal. Further, the second phase comparator (9) compares the phase difference between the frequency-divided signal and the vertical synchronizing signal V of the frame period. After compensating the error signal by the phase compensating circuit (12), the adder (13) ) To the other input terminal. The adder (13) adds the two error signals, supplies the added signal to the motor drive circuit (14), and, based on the error amount indicated by the added signal, the optical disk (1) by the spindle motor (2). Adjustment of the rotation phase of.

Next, the operation when the spindle motor is operated by the above configuration will be described. For example, assuming that an NTSC video signal having a frame frequency of 29.97 Hz is recorded on the optical disc (1), the PLL circuit (30) has a 262.5-fold increase. A frequency signal is output, and the second frequency divider (25) is set to perform 1/525 frequency division. In this state, since the frequency signal generator (21) outputs a frequency signal of 32 cycles in one rotation of the disk (1), the output signal frequency of the frequency signal generator (21) is
29.97 × 32 = 959.04 Hz. And the PLL circuit (30)
First frequency divider (24) to convert to 262.5 times frequency
The divided signal of And the frequency of the horizontal synchronization signal of the NTSC system. Then, a highly accurate error signal is obtained based on the phase difference between the output signal of the frequency divider (24) having the horizontal period and the reference horizontal synchronization signal from the time base collector (10).

Further, by dividing the output signal of the first frequency divider (24) by 1/525 with the second frequency divider (25), the second frequency divider (25) Is obtained, which is the frequency of the vertical synchronization signal of the frame period of the NTSC system. Then, the output signal of the frequency divider (25) of this frame period and the time base collector (1
A highly accurate error signal is obtained based on the phase difference from the reference vertical synchronizing signal of the frame period from 0).

Then, a spindle servo for recording a video signal of the NTSC system is performed by an addition signal of each error signal.

The optical disk (1) has a PAL with a frame frequency of 25 Hz.
When recording video signals of the standard system, the PLL circuit (30)
12.5 times frequency signal is output, and the second frequency divider (25) is 1 /
It is set to divide by 625. In this state, the frequency signal generator (21) outputs a frequency signal of 32 cycles in one rotation of the disk (1).
The output signal frequency of 1) is 25 × 32 = 800 Hz. And the PLL circuit (30) converts to 312.5 times the frequency,
The frequency-divided signal of the first frequency divider (24) is And the frequency of the horizontal synchronization signal of the PAL system. Then, a highly accurate error signal is obtained based on the phase difference between the output signal of the frequency divider (24) having the horizontal period and the reference horizontal synchronization signal from the time base collector (10).

Further, by dividing the output signal of the first frequency divider (24) by 1/625 with the second frequency divider (25), the second frequency divider (25) Is obtained, and becomes the frequency of the vertical synchronizing signal of the frame period of the PAL system. Then, the output signal of the frequency divider (25) of this frame period and the time base collector (1
A highly accurate error signal is obtained based on the phase difference from the reference vertical synchronizing signal of the frame period from 0).

Then, the spindle servo for recording the video signal of the PAL system is performed by the addition signal of each error signal.

Thus, according to the spindle servo circuit of this example, the PL
Since the L circuit (30) performs non-integer multiplication corresponding to the horizontal scanning period of one frame of the video signal, the output frequency signal of the frequency signal generator (21) can be set low, and this frequency signal generator (21) A general-purpose device having a simple configuration and easy adjustment can be used, and the manufacturing cost of the spindle servo circuit can be reduced.

Further, the PLL circuit (30) has a simple configuration in which the count value of the counter (34) is controlled by the flip-flop (37) and outputs a frequency signal of 262.5 times or 312.5 times. Easy.

Further, in this example, by simply switching the count value to be reset by the PLL circuit (30) and the frequency division ratio of the second frequency divider (25), both the NTSC system and the PAL system can be used as video signals to be recorded. Can be dealt with. Alternatively, video signals other than both types can be dealt with by changing the set values of the count value and the frequency division ratio.

In the above-described embodiment, an optical disk is used as a disk for recording video signals. However, it goes without saying that the present invention can be applied to a spindle servo circuit of a recording device for various disks on which video signals are recorded. Further, the present invention is not limited to the above-described embodiment, without departing from the gist of the present invention.
Of course, other various configurations can be adopted.

〔The invention's effect〕

According to the present invention, there is an advantage that the spindle motor can be controlled with high accuracy and high precision synchronized with a video signal to be recorded with a simple configuration using a normal frequency signal generator for generating a signal of a relatively low frequency.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a spindle servo circuit of the present invention, and FIG. 2 is a block diagram showing an example of a conventional spindle servo circuit. (1) optical disk, (2) spindle motor, (2)
1) is a frequency signal generator, (24) is a first frequency divider, (2)
5) is a second frequency divider, and (30) is a PLL circuit.

Claims (1)

(57) [Claims] 1. A spindle servo circuit for controlling a spindle motor for rotating a disk on which a video signal is recorded, comprising: a frequency signal generator for generating a frequency signal in synchronization with the rotation of the spindle motor; A phase-locked loop circuit for multiplying the frequency signal by the number corresponding to the horizontal scanning period of one field of the video signal, and a frequency divider for dividing the output signal of the phase-locked loop circuit. Obtain a signal of a predetermined cycle synchronized with the horizontal cycle or the vertical cycle of the video signal as an output signal of the device, from the phase difference between the signal of the predetermined cycle and a horizontal synchronization signal or a vertical synchronization signal as a reference of the video signal, A spindle servo circuit for obtaining rotation error information of the spindle motor.