JPH0227598A - Shift register - Google Patents

Abstract

PURPOSE:To increase the maximum operating frequencies and to decrease the minimum operating frequencies by driving a circuit having the output of a ratio-less type inverter as an output signal on one stage of a shift register in an E/E (enhancement/enhancement) constitution on a special condition. CONSTITUTION:An input signal Vin is inputted to the drain of a switch TFTQ1 to be controlled by a clock pulse phi1, the source of Q1 is connected to the input part of a ratio type inverter INV 1 in the E/E constitution between a supply voltage VDD1 and a ground and the input part of a ratio-less type inverter INV 2 in the E/E constitution between a supply voltage VDD2 and the ground, the output of the INV 1 is connected to the gate of a TFTQ5 on the power source side of the INV 2, and the output of the INV 2 is inputted to the drain of a switch TFTQ5 controlled by a clock pulse phi2. In the shift register, when the VDD1 is increased, the high voltages are impressed to the gates of transistors Q5 and Q10, and the circuit is driven on the condition of [VDD1]>[VDD2]. Thus, the maximum operating frequencies can be increased, and the minimum operating frequencies can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor circuit, and particularly to a shift register suitable for increasing the maximum operating frequency and decreasing the minimum operating frequency of the shift register.

[Conventional technology]

Conventionally, when constructing a shift register using thin film MIS transistors, for example, a two-phase dynamic shift register described in Chapter 5 of Integrated Circuit Engineering (2), Corona Publishing, ie, the circuit shown in Fig. 2 was used. was. here,
To explain the operation of the circuit shown in FIG. 2 using the timing chart shown at the bottom of the figure, the input signal V 1n is taken into the gate of the transistor Q2 at the rising edge of the clock pulse φ1, and the inverted signal V t of vln is immediately taken in. n is input to the drain of the transistor Qe, and then at the rising edge of the clock pulse φ2, V i n is taken into the gate of the transistor Q7, so that the inverted signal v of vlfi is immediately inputted to the drain of the transistor Qe.
1. is output as the output signal V out .

That is, vIll is controlled by Glock pulses φl and φ2.

By the way, one way to operate the circuit shown in FIG. 2 at high speed is to increase the power supply voltage VOO. This is because by increasing Voo, that is, by increasing the gate voltage of transistors Qa and Qa, the on-resistance of Qs and Qa is lowered, so the time to charge the input capacitance of the next stage inverter through Qa and QB is shortened. This is due to the following reasons.

[Problem to be solved by the invention]

By the way, it has been found that the thin film transistor circuit shown in FIG. 2 easily malfunctions when the power supply voltage Voo is made higher than the normal driving voltage. In terms of operation, even though Qz or Ql is off and the switch transistor transistor 1 is off, Ql or Ql increases as VDD increases due to the increase in leakage current of Ql or QB. This is a phenomenon where the device turns on.

The above phenomenon occurs at the source of a thin film MIS transistor.

This is because the drain breakdown voltage is extremely low compared to that of a single crystal MoS transistor. This is because current thin film MIS transistors do not have a perfect PN junction to suppress leakage current between the source and drain.

Therefore, if Voo is increased, the load transistor Qa,
Switch transistor Ql via Qa etc.

Since the voltage applied to the drains of Qa, etc. increases, as a result, leakage currents of switch transistors Qs, Qθ, etc. increase.

The above results mean an improvement in the minimum operating frequency of a shift register formed using thin film transistors.

An object of the present invention is to improve the maximum operating frequency and lower the minimum operating frequency of a shift register formed using thin film transistors.

[Means to solve the problem]

The above purpose is to input the input signal vln to the drain of the switch transistor Q1 controlled by the clock pulse φ1 in a circuit configuration of one stage of shift register formed by thin film MIS transistors, and the source of Ql is connected to the power supply voltage Voor-
Ratio type inverter INVI with E/E (enhancement/enhancement) configuration configured between ground
The input part of INVI is connected to the input part of a ratioless type inverter INV2 in an E/E configuration configured between the input part of the power supply voltage VDD2 and the ground, and the output of INVI is connected to the gate of the transistor Q6 on the power supply side of INV2. The output of switch transistor Q controlled by clock pulse φ2
6, and the source of Qa is the input part of the ratio type inverter INV3 with an E/E configuration configured between VDDl and ground, and the input part of the ratio type inverter INV3 is configured between V oox and ground. Type of inverter INV4
The output of INV3 is connected to the gate of transistor Q10 on the power supply side of INV4, and the output of INV4 is used as the output signal V out of one stage of the shift register. I > l
This is achieved by forming a shift register that is driven under the condition of VDD21.

[Effect]

In the above shift register, as VDDI increases, a higher voltage is applied to the gate of the transistor Qs t Qlo, so the on-resistance of Qs + Qzo becomes smaller, and as a result, the load capacitance of the next stage increases through Qs, Ql (1). In other words, the maximum operating frequency of the shift register is improved.Also, VC+01 I
> Since the above circuit is driven under the condition of I VDD2 l, even if VDDI is increased, the switch transistor Q
Maximum VDD2 L/ between the source and drain of r, Qs
Since no voltage is applied, there is no sudden increase in the leakage current of Qt and Qe.In other words, the minimum operating frequency of the shift register does not improve.Furthermore, if VDD2 is made low enough to turn on the next stage transistor, Ql, Qe The leakage current becomes even smaller.

That is, the minimum operating frequency of the shift register decreases.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

Figure 1 shows a polycrystalline silicon thin film transistor (hereinafter referred to as pol).
This is a one-stage structure of the shift register of the present invention formed using y-Si TFT).

The circuit configuration is to input an input signal Vsn to the drain of a switch TFTQ1 controlled by a clock pulse φ1,
The source of l is configured between the power supply voltage Voos and ground.
/E (enhancement/enhancement) configuration, connect to the input part of the ratio type inverter INV1, and connect to the input part of the ratioless type inverter INV2, configured between the power supply voltage VDDZ and ground, and the E/E configuration.
The output of NVI is connected to the gate of TFTQs on the power supply side of INV2, and the output of INV2 is input to the drain of switch TFTQs controlled by clock pulse φ2.
The source of Qa is the input part of the ratio type inverter INV3 with an E/E configuration configured between VDDI and ground, and the input part of the ratioless type inverter INV4 with an E/E configuration configured between VDD2 and ground. Connect and INV
The output of INV4 (7) is connected to the gate of TFTQro on the power supply side, and the output of INV4 is used as the output signal V out of the first stage of the shift register.

Here, TPT is an n-channel TFT and VDD2 = 40
V, VDD2=15V, TFT threshold voltage VT=5
It is V.

Next, φ1 shown at the bottom of the figure. φ2. v51. vouu
The circuit operation will be explained based on the timing chart.

For example, assuming that v1n=Ov, when φ1 rises from OV to 30V, vln is TFTQzt and Qa
is transferred to the gate of T F T even if φt=OV.
It is held at the gates of Qz and Qa.

Therefore, since INVI and INV2 are in the off state, TF
Voot -VT: 40 V -5 at the gate of TQ8
V=35V is applied, T F T Qa (7) 0th order φ2 where VDD2=15V is applied to the drain
When TFTQs rises from 0 to 30V, TFTQs turns on, so the drain voltage of TFTQe is 15V.
is transferred to the gates of TFTQ7 and TFTQe, and φ2
= o v 2 is also held at the gate of TFT Q71 Q9. Therefore, INV3. Since INV4 is turned on, a voltage close to Ov is applied to the gate of TFTQ10, and Ov is output as the output V out of the first stage of the shift register.

Here, under the above conditions, since VDD2 is as low as 15V, only a maximum of 15V is applied between the source and drain of the switch transistor Qs.

Leakage current when TFTQe is off is small.

Therefore, the minimum operating frequency of the shift register is relatively low, and under the above conditions, 35V is applied to the gate of TFTQII, so the on-resistance of TFTQa becomes sufficiently low. Therefore, T through T F T Q s e Q e
The time for accumulating charge on the gate of F T Q 7 t Q 9 becomes shorter. Therefore, the maximum operating frequency of the shift register is relatively high.

FIG. 3 shows the structure of a one-stage shift register of the present invention formed by combining enhancement type and depletion type Po1y-3i TFTs.

The circuit configuration is such that an input signal vl is input to the drain of a switch TFT Q1 controlled by a clock pulse φ1, and the source of Ql is an E/D connected between the power supply voltage VDD2 and ground.
(enhancement/depression) configuration and a ratioless type inverter INV2 configured between power supply voltage VDD2 and ground.
The output of INV2 is connected to the gate of TFTQs on the power supply side of INV2, the output of INV2 is input to the drain of switch TFTQe controlled by clock pulse φ2, and the source of Qe is connected to the E/D configured between VDDI and ground. Input section of ratio type inverter INV6 and VDD2-
It is connected to the input part of a ratioless type inverter INV4 in an E/E configuration configured between ground, and the output of INV6 is connected to the gate of TFTQzo on the power supply side of INV4.
Output of NV4 is output signal of one stage of shift register Vout
It is said that

Here, TPT is an n-channel TFT and VDD2=40
V, VDD2= 15 V, T F T (7) VT
For E type, Vt=5V and for D type, VT=-3V.

Next, φ1 shown at the bottom of the figure. φ2* Vt++@V
The circuit operation will be explained based on the out timing chart.

For example, assuming that vLll=Ov, φl is Ov
When the voltage rises from 30 V, the voltage is TFTQ2.
．． is transferred to the gate of Ql, and even if φ1=Ov, TF
It is held at the gates of TQz and Qa. Therefore, INV5
．． Since INV2 is in the off state, Voot=40 V is applied to the TFTQll(7) gate, and TFTQa
(7) VDD2=15V is applied to the drain. Next, when φ2 rises from Ov to 30V, TFTQ
Since s is turned on, the drain voltage L5 of TFTQa
V is TFTQ7. Qeo) is transferred to the gate, $z=O
Even if the voltage becomes V, it is held at the gate of T F T Q 7 t Q s. Therefore, since INV 6 and INV4 are in the on state, a voltage close to Ov is applied to the gate of TFTQlo, and the output vou of the first stage of the shift register
Ov is output to t.

22. Under the above conditions, since VDD2 is as low as 15V, only a maximum of 15V is applied between the source and drain of the switch transistor Qe. Therefore, the leakage current when the TFTQa is in the off state is small.

Therefore, the minimum operating frequency of the shift register is relatively low, and under the above conditions, 40V is applied to the gate of TFTQa, so the on-resistance of TFTQs becomes sufficiently low. Therefore, TFTQ7. through TFTQ5sQa. The time for accumulating charge on the gate of Qll becomes shorter. Therefore, the maximum operating frequency of the shift register is relatively high.

By the way, the shift register of the present invention is most effective when used in the peripheral circuit of an active matrix liquid crystal display with a built-in peripheral circuit.

FIG. 4 shows the configuration of one stage of a scanning side drive circuit which is a part of the peripheral circuit of an active matrix liquid crystal display with a built-in peripheral circuit. Here, 1 is a level shifter,
2 is the buffer, and 3 is the capacity of one line as seen from the scanning side. Also, φ1. φ2゜V ine Vuc, Vout
The timing chart is shown at the bottom of the figure.

As for the operation of the circuit, the input signal VIR is converted to Vot+t by the operation of the shift register described above, and V o
u i is level shifter 1. By buffer 2, V ou
The signal is amplified to t and applied to the capacitor 3 of one line viewed from the scanning side.

〔Effect of the invention〕

According to the present invention, it is possible to improve the maximum operating frequency and lower the minimum operating frequency of a shift register formed of thin film transistors, resulting in effects such as expanding the operating frequency range and increasing the noise margin.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a shift register of the present invention. Fig. 2 is a circuit diagram of a conventional shift register, Fig. 3 is a circuit diagram of a shift register of the present invention, and Fig. 4 is an application of the shift register of the present invention to a peripheral circuit of an active matrix liquid crystal display with a built-in peripheral circuit. FIG. DESCRIPTION OF SYMBOLS 1... Level shifter, 2... Buffer, 3... Capacitance of 1 line seen from the scanning side, Ql to Q12... Thin film transistor. Figure 3 Figure 3 Or.

Claims (1)

[Claims] 1. Thin film MIS (Metal Insulator Sem)
In a one-stage shift register circuit configuration formed by (conductor) transistors, the input signal V_i_m
is input to the drain of a switch transistor Q_1 controlled by a clock pulse φ_1, and the source of Q_1 is an input part of a ratio type inverter INV1 with an E/E (enhancement/enhancement) configuration configured between the power supply voltage V_D_D_1 and ground. and power supply voltage V_D_D
It is connected to the input part of a ratioless type inverter INV2 in an E/E configuration configured between _2 and ground, the output of INV1 is connected to the gate of transistor Q_5 on the power supply side of INV2, and the output of INV2 is connected to the clock pulse φ_2. The source of Q_■ is configured between V_D_D_1 and ground in an E/E configuration, and the input part of ratio type inverter INV3 is configured between V_D_D_2 and ground. E/
E configuration is connected to the input part of ratioless type inverter INV4, the output of INV3 is connected to the gate of transistor Q_1_0 on the power supply side of INV4, and the output of INV4 is the output signal V_o_u_t of one stage of shift register. The circuit shown on the left is |V_D_D_1|>|V_D_
A shift register characterized by being driven under the condition of D_2. 2. In a one-stage shift register circuit configuration formed by thin film MIS transistors, at least two power supply voltages are applied to the shift register 1 when driving the shift register.
A shift register characterized in that a power supply voltage is applied separately to a group of inverters configured within a stage, and the lowest power supply voltage is applied to an inverter in an output stage. 3. In a one-stage shift register circuit configuration formed by thin film MIS transistors, an input signal V_i_n is input to the drain of a switch transistor Q_1 controlled by a clock pulse φ_1, and the source of Q_1 is configured between the power supply voltage V_D_D_1 and ground. E
/D (enhancement/depression) configuration and the input of a ratioless type inverter INV5, and an E/E configuration configured between the power supply voltage V_D_D_2 and ground. is the transistor Q on the power supply side of INV2
The output of INV2 is input to the drain of switch transistor Q_6 controlled by clock pulse φ_2, and the source of Q_6 is connected to the gate of ratio type inverter INV6 in an E/D configuration between V_D_D_1 and ground. Ratioless type inverter I with E/E configuration configured between input section and V_D_D_2-ground
The output of INV6 is connected to the input part of NV4, and the output of INV6 is connected to the gate of transistor Q_1_0 on the power supply side of INV4.
The output of V4 is the output signal of one stage of shift register V_o_u
With the circuit configuration set to _t, the circuit shown on the left is |V_D_D_1>|
A shift register characterized in that it is driven under the condition of V_D_D_2|. 4. A shift register according to claim 1, 2, or 3, characterized in that the shift register is made of polycrystalline silicon. 5. A shift register according to claim 1, 2, 3, or 4, wherein the shift register is formed on a glass substrate. 6. An active matrix display according to any one of claims 1 to 5, characterized in that a shift register is used in a peripheral circuit of an active matrix display with a built-in peripheral circuit.