JPH02275638A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02275638A
JPH02275638A JP9795389A JP9795389A JPH02275638A JP H02275638 A JPH02275638 A JP H02275638A JP 9795389 A JP9795389 A JP 9795389A JP 9795389 A JP9795389 A JP 9795389A JP H02275638 A JPH02275638 A JP H02275638A
Authority
JP
Japan
Prior art keywords
emitter
region
corners
emitter region
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9795389A
Other languages
Japanese (ja)
Inventor
Norio Kususe
楠瀬 典男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP9795389A priority Critical patent/JPH02275638A/en
Publication of JPH02275638A publication Critical patent/JPH02275638A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To relax the concentration of large currents at the corner sections of an emitter region by forming the emitter region of a bipolar transistor in a plane shape that the corners of a rectangle are rounded. CONSTITUTION:A collector region 2, a base region 3 and an emitter region 4 are shaped to a silicon substrate 1, an oxide film is applied, a collector- electrode leading out window 5, a base-electrode leading-out window 6 and an emitter-electrode leading-out window are bored, and a collector wiring 8, a base wiring 9 and an emitter wiring 10 are formed through the evaporation of Al and selective etching. The emitter region 4 and an emitter-electrode leading-out window 7 are formed in an octagonal shape that corners are rounded. Consequently, corners are rounded when a photo-resist is patterned and etched on actual manufacture, and gentle curves are shaped substantially. Accordingly, an electric field is not concentrated, thus preventing electrostatic breakdown.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特にバイポーラトランジス
タを静電保護素子として使用した半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device using a bipolar transistor as an electrostatic protection element.

〔従来の技術〕[Conventional technology]

従来の半導体装置について図面を参照して説明する。 A conventional semiconductor device will be explained with reference to the drawings.

第2図は従来のバイポーラトランジスタの一例の平面図
である。
FIG. 2 is a plan view of an example of a conventional bipolar transistor.

NPNバイポーラトランジスタを静電保護素子使用する
場合、マスク設計時には、瞬間的に流される大電流を考
慮してエミッタ領域4の面積を大きな面積となるように
設計されていた。エミッタ領域4の面積が異なるのみで
平面形状その他は、半導体装置を構成する他のトランジ
スタと同じように作成されていた。
When an NPN bipolar transistor is used as an electrostatic protection element, when designing a mask, the emitter region 4 is designed to have a large area in consideration of the large current that is instantaneously passed. The only difference was the area of the emitter region 4, and the planar shape and other aspects were manufactured in the same manner as other transistors constituting the semiconductor device.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の半導体装置において、DC法・Cチャー
ジ法等での破壊試験を実施した場合、MIL規格(例え
ば、2000V以上)を満足しないものが発生する。近
年、特に高性能化が要求されるようになり、このためバ
イポーラトランジスタのコレクターベース接合、エミッ
ターベース接合を浅くすることにより高性能化が図れる
ようになってから、静電破壊による不良の発生頻度が多
くなっている。第2図に示したように、静電破壊破壊部
分11は矩形エミッタ領域4の角部分の電界が集中する
場所に起りやすい。即ち、矩形工ミッタ領域4の角部に
電界集中が発生し、ジュール熱等によりアルミニウムが
シリコン基板1にもぐり込む所謂アルミスパイクによっ
てベース−エミッタ接合及びコレクターベース接合が破
壊されるからである。
When the conventional semiconductor devices described above are subjected to a destructive test using the DC method, C charge method, etc., some devices do not satisfy the MIL standard (for example, 2000 V or more). In recent years, there has been a particular demand for higher performance, and for this reason, it has become possible to achieve higher performance by making the collector base junction and emitter base junction of bipolar transistors shallower. are increasing. As shown in FIG. 2, the electrostatic breakdown portion 11 tends to occur at the corners of the rectangular emitter region 4 where the electric field is concentrated. That is, electric field concentration occurs at the corners of the rectangular emitter region 4, and the base-emitter junction and collector-base junction are destroyed by so-called aluminum spikes in which aluminum sinks into the silicon substrate 1 due to Joule heat or the like.

このように、従来のバイポーラトランジスタでは、保護
作用を行う前に、静電界によって破壊してしまうという
欠点があった。
As described above, conventional bipolar transistors have the disadvantage that they are destroyed by the electrostatic field before they have a protective effect.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、バイポーラトランジスタを静電保護素子とし
て使用している半導体装置において、前記バイポーラト
ランジスタのエミッタ領域の平面形状が鈍角の多角形で
あることを特徴とする。
The present invention is a semiconductor device using a bipolar transistor as an electrostatic protection element, characterized in that the planar shape of the emitter region of the bipolar transistor is an obtuse polygon.

〔実施例〕〔Example〕

本発明の実施例について図面を参照して説明する。 Embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例の平面図である。FIG. 1 is a plan view of one embodiment of the present invention.

従来と同じ技術によってシリコン基板1にコレクタ領域
2、ベース領域3、エミッタ領域4を形成し、酸化膜を
被着した後、コレクタ電極取出し窓5、ベース電極取出
し窓6、エミッタ電極取出し窓をあける。A1の蒸着と
選択エッチによりコレクタ配線8、ベース配線9、エミ
ッタ配線10を設ける。
After forming a collector region 2, a base region 3, and an emitter region 4 on a silicon substrate 1 using the same technique as before and depositing an oxide film, a collector electrode extraction window 5, a base electrode extraction window 6, and an emitter electrode extraction window are opened. . Collector wiring 8, base wiring 9, and emitter wiring 10 are provided by vapor deposition of A1 and selective etching.

この実施例においては、エミッタ領域4及びエミッタ電
極取出し窓7の角が落とされた六角形になっている。
In this embodiment, the emitter region 4 and the emitter electrode extraction window 7 have rounded hexagonal corners.

数値例を挙げると、エミッタ領域4の寸法を10μm×
20μmとするとき、−辺を3μmとする直角二等辺三
角形で角落とした形状にする。
To give a numerical example, the dimensions of the emitter region 4 are 10 μm×
When the thickness is 20 μm, the shape is a right-angled isosceles triangle with a negative side of 3 μm and a rounded corner.

この形状にすると、実際の製造時にはホトレジストのパ
ターニングとかエツチング時に角がなくなり、実質的に
は緩やかな曲線となる。角がなくなるので、電界集中が
起らず、従って、静電破壊が防止される。
With this shape, during actual manufacturing, there will be no corners during photoresist patterning or etching, and the shape will essentially become a gentle curve. Since there are no corners, no electric field concentration occurs, and therefore electrostatic damage is prevented.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、エミッタ領域を矩形の
角落としされた平面形状にしたので、エミッタ領域の角
部での大電流集中を緩和することができ、エミッターコ
レクタ電極間あるいは配線層間での短絡を防ぐことがで
きるという効果を有する。
As explained above, in the present invention, since the emitter region has a rectangular planar shape with rounded corners, it is possible to alleviate large current concentration at the corners of the emitter region, and it is possible to reduce the concentration of large currents at the corners of the emitter region. This has the effect of preventing short circuits.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の平面図、第2図は従来のバ
イポーラトランジスタの一例の平面図である。 1・・・シリコン基板、2・・・コレクタ領域、3・・
・ベース領域、4・・・エミッタ領域、5・・・コレク
タ電極取出し窓、6・・・ベース電極取出し窓、7・・
・エミッタ電極取出し窓、8・・・コレクタ配線、9・
・・ベース配線、10・・・エミッタ配線、11・・・
静電破壊部分。 )1因
FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is a plan view of an example of a conventional bipolar transistor. 1... Silicon substrate, 2... Collector region, 3...
・Base region, 4... Emitter region, 5... Collector electrode extraction window, 6... Base electrode extraction window, 7...
・Emitter electrode extraction window, 8...Collector wiring, 9・
...Base wiring, 10...Emitter wiring, 11...
Electrostatic damage part. )1 cause

Claims (1)

【特許請求の範囲】[Claims] バイポーラトランジスタを静電保護素子として使用して
いる半導体装置において、前記バイポーラトランジスタ
のエミッタ領域の平面形状が鈍角の多角形であることを
特徴とする半導体装置。
1. A semiconductor device using a bipolar transistor as an electrostatic protection element, wherein an emitter region of the bipolar transistor has an obtuse polygonal planar shape.
JP9795389A 1989-04-17 1989-04-17 Semiconductor device Pending JPH02275638A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9795389A JPH02275638A (en) 1989-04-17 1989-04-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9795389A JPH02275638A (en) 1989-04-17 1989-04-17 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02275638A true JPH02275638A (en) 1990-11-09

Family

ID=14206037

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9795389A Pending JPH02275638A (en) 1989-04-17 1989-04-17 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02275638A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6838699B2 (en) 2002-02-12 2005-01-04 Seiko Epson Corporation Electro-optical device with undercut-reducing thin film pattern and reticle

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6838699B2 (en) 2002-02-12 2005-01-04 Seiko Epson Corporation Electro-optical device with undercut-reducing thin film pattern and reticle

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