JPH02268348A - Data processing system - Google Patents

Abstract

PURPOSE:To quickly save and restore a memory mapper value to secure relations between the memory mapper value and the processing even at the time of multiple interrupts or the like by saving and restoring the memory mapper value by hardware independently of a CPU. CONSTITUTION:When a save instruction is issued, a transfer control part 16 independent of a hardware device 11 only for save and restore of a data processing system reads the memory mapper value from a memory mapper register 10 and stores it in a FIFO buffer 14. This memory mapper value is written in the position pointed by a pointer part 13 of the memory part 14 and the value of the pointer value 13 is incremented by one. The memory mapper value is saved and restored independently of a CPU 1 and software at a high speed which is not restricted by the instruction execution speed of the CPU 1 and is determined by the hardware device 11.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data processing system that expands memory by memory mapping, and more particularly to saving and restoring memory manoper values for memory mapping.

BACKGROUND ART FIG. 2 is a schematic configuration diagram of a conventional example of this type of data processing system, in which 1 is a CPU, 2 is a local bus, and 3 is a C
4 is the keyboard, 5 is the system bus, 6 and 7 are the system memory located in the extended memory space, and the frame memory of display 8, respectively. be. 9 is a memory mapper for mapping the extended memory space to the CPU physical address space.

CPU physical address space is IME, extended memory space is 2
The memory mapper 9 in the case of 56 MB will be explained with reference to FIG. In this case, the memory mapper 9 includes, for example, 16 12-bit memory mapper registers 10, and each memory mapper register 10 is accessed by the CPU as an I10 device.

When accessing the extended memory (system memory 6 or frame memory 7) from the CPU, the upper 4 bits of the address signal on the local bus 2 (A16, ..., A1
9) is decoded into one memory mapper register l.
If O is enabled, the memory mapper value (12 pits) written in it is the upper 12 pits of the 4-pit address signal on the system bus 5) (A16..., A
27). The lower 16 bits (AOl..., A15) of the address signal on the local bus 2 are directly used as the lower 16 bits of the address signal on the system bus 5) (
AO,...A15).

Now, the value of the memory mapper register 10, that is, the memory mapper value, often needs to be saved and restored. For example, in interrupt processing, the memory mapper
Since changing the value is generally necessary, the memory mapper value is saved at the beginning of the interrupt handling program so that processing interrupted by an interrupt can be resumed normally.
Next, it is necessary to set the memory mapper value used in the interrupt processing in the memory mapper register IO and restore it to the memory mapper value saved at the last stage of the interrupt processing program.

Conventionally, such saving and restoring of memory mapper values has been performed by software. A save area for the memory mapper value is secured on the local memory 3, its address is stored at the time of save, and at the time of restore, the memory mapper value is read from the save area based on the address and written to the memory mapper register IO.

Problems to be Solved by the Invention However, a large number of instruction steps are required to save and restore memory mapper values, which places a heavy burden on the software, and the speed of the save and restore operations is limited by the instruction execution speed. There was a problem in that interrupt processing was delayed due to the operation time. In particular, with regard to interrupt processing, the probability of multiple interrupts occurring increases due to the delay due to the save/restore operation time, resulting in a vicious cycle in which interrupt processing is further delayed.

FIG. 4 is a flowchart showing an example of such multiple interrupts (quadruple interrupts).

When the first interrupt ■ occurs, the process to save the memory mapper value is executed at the beginning of the interrupt processing program, then the process to write the memory mapper value used in the interrupt processing to the memory mapper register, and then Substantive interrupt processing is then executed, and finally memory mapper value restoration processing is executed. However, it takes time to save and restore the memory mapper value depending on the software, and as the interrupt processing time increases, the probability that another interrupt (2) will occur at the timing shown in the figure increases, for example. Even during the processing of this interrupt (2), the probability that another interrupt (2) will occur increases, and another interrupt (2) will occur in the same way.

As described above, when the interrupt processing time increases due to the operation of saving and restoring the memory mapper value, multiple interrupts are less likely to occur, and the processing of early-occurring interrupts (such as ■) becomes extremely slow.

The present invention provides memory mapper value saving and
The purpose is to solve problems such as the delay in interrupt processing described above due to restoration operations, and to reduce the burden on software.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a data processing system that expands memory by memory mapping.
In addition to providing a buffer (first-in, last-out, last-in, first-out) for storing memory mapper values, a memory mapper value save or restore instruction is
When issued by the PU, it operates independently of the CPU, reads the memory mapper value held in the memory mapper register in response to the save command, stores it in the first-in/last-out buffer, and also responds to the restore command. In response, a hardware means is provided for fetching a memory mapper value from the first-in/last-out buffer and setting it in the memory mapper register.

Since the operation of saving and restoring the working memory manoper value is performed by hardware independent of the CPU, the operation can be easily speeded up. In addition, since memory mapper values are accumulated using a first-in, last-out method, even when memory mapper values are saved and restored multiple times, such as in the case of multiple interrupts, the software is aware of the relationship between the save and restore. Instead, it is sufficient to simply issue an evacuation command and a restore command. Therefore, it is possible to speed up interrupt processing, etc. that require operations to save and restore memory manoper values, and to reduce the burden on software.

Embodiment FIG. 1 is a schematic configuration diagram of a data processing system according to an embodiment of the present invention, and the same reference numerals as those in FIG. 2 indicate equivalent parts.

This data processing system is similar to the conventional data processing system shown in FIG. It is similar to the system hardware configuration.

In this hardware device 11, 12 is a memory section for saving memory mapper values, and 13 is a pointer section for managing the storage position and retrieval position of the saving memory section 12, and these are first-in/last-out. This constitutes the buffer 14 (last in/first out).

15 is a local path 2 (CPU bus) interface register section, and 16 is a transfer control section.

The interface register unit 15 performs transfer control to determine whether the instruction issued by the CPUI (by software) is a save instruction or a restore instruction by setting a mapping compatible bit in the input/output register from the CPUI. Notify Department 16. Note that when the save command and the restore command are issued, the CPUI releases the local bus 2 until the execution of the commands is completed.

When an evacuation command is issued, the transfer control unit 16 performs control to read the memory mapper value from the memory mapper register IO (which has been declared in use in advance) and store it in the first-in/last-out buffer 14. conduct. This memory mapper value is stored in the pointer section 13 of the save memory section 14.
is written to the position indicated by the pointer section 13.
The value of is incremented by 1.

When a save instruction is issued, the transfer control unit 16 takes out one memory mapper value from the first-in/last-out buffer 14 and controls writing it into the memory mapper register 10 (which has been declared for use). The memory mapper value taken out from the first-in/last-out buffer 14 at this time is the one stored in the location immediately before the location indicated by the pointer section 13 of the save memory section 12, and this is the last one. This is the memory mapper value stored in .

After this extraction, the value of the pointer section 13 is decremented by 1.

This kind of memory management value saving/restoring operation is performed by CP
It is executed independently of U1, ie independently of the software. Therefore, it is possible to perform fast saving and restoring at a speed determined by the hardware device 11 without being restricted by the instruction execution speed of the CPU 1, and to speed up processing that involves saving and restoring memory manoper values such as interrupt processing. can.

Further, the software only needs to issue an evacuation command and a restore command. This is the same in the case of multiple interrupt processing as shown in Figure 4, and if the program side simply issues save and restore instructions without being aware of the multiple interrupts or the destination of the interrupt, good. Even if you do this,
Since the memory mapper value saved later is restored at some point, the correspondence between the memory mapper value and the process is guaranteed.

In this way, the burden on the software is also reduced.

Note that the save memory section 12 may be provided on the local memory 3.

Effects of the Invention As is clear from the above explanation, the present invention saves and restores memory mapper values using hardware independent of the CPU, so it can save and restore at high speed and speed up interrupt processing. Also, put the memory mapper in advance.
Because it is stored in the post-output buffer, the relationship between the memory matsuba value and processing is guaranteed even in the case of multiple interrupts, and the burden on software is reduced because it only needs to issue save and restore instructions. It has the following effects.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a data processing system according to an embodiment of the present invention, FIG. 2 is a schematic configuration diagram of an example of a conventional data processing system, FIG. 3 is an explanatory diagram of a memory manoper, and FIG.
The figure is a flowchart for explaining multiple interrupts. 1...CPU, 2...Local bus, 5...System bus, 6...System memory, 9...Memory mapper 10...Memory mapper register, 11...
Hardware device dedicated to saving and restoring, 12... Memory unit for saving, 13... Pointer unit, 14... First-in/last-out buffer, 15° pint face register unit,
16...Transfer control unit. Name of agent: Patent attorney Shigetaka Awano and one other person

Claims (1)

[Claims] A hardware first-in/last-out buffer for storing memory mapper values for mapping the extended memory space to the physical address space of the CPU, and a memory mapper value save or restore instruction are issued by the CPU. and the CPU operate independently of the CPU, and read the memory mapper value held in the memory mapper register in response to the save instruction and store it in the first-in/last-out buffer, and in response to the restore instruction. A data processing system for expanding memory by memory mapping, comprising: hardware means for extracting a memory mapper value from the first-in/last-out buffer and writing it into the memory mapper register.