JPH02268019A - Logic circuit - Google Patents

Abstract

PURPOSE:To constitute the circuit with less number of transistors(TRs) by connecting a 1st input terminal to the source of a 1st MOS TR and the gate of a 2nd TR, connecting a 2nd input terminal to the source of the 2nd TR and a gate of the 1st TR and connecting drains of the two TRs. CONSTITUTION:With inputs signals I1, I2 set to both a low level in a logic circuit forming a dissidence circuit or a coincidence circuit, a TR TP1 is set to a high level at the point of time of precharge. Since both MOS TRs TN1, TN2 are not energized at an output period TD1 successively, the level of the TR TP1 remains at a high level and an output signal O goes to a low level. The input signals I1, I2 are respectively at a low level and a high level at a data output period TD2, the TR TN1 is energized, the TR TP1 goes to a low level and the output signal O goes to a high level. Thus, the output signal O is exclusive OR of the input signals I1, I2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to logic circuits realized by semiconductor integrated circuit technology, and particularly to logic circuits such as mismatch circuits and -number circuits.

[Prior Art] A conventional mismatch circuit (exclusive OR circuit) is shown in FIG. As shown in the figure, this mismatch circuit consists of a P-channel MOS transistor (hereinafter referred to as PMO8).
) TP7, Tp8 and N-channel MO3) transistor (hereinafter referred to as NMO3) TN7, TN, NAND gate, PM○5TPIO, TpH and NM
NOR gate and PMO consisting of O5TNIO, TNI,
NOR-NA consisting of 3TP9 and NMO3TN9
ND composite gate, PMO3Tp+□ and NMO8TN
It is composed of an inverter based on I2. The two input signals 11 and 2 are connected to the NAND gate and NO
Input to NOR gate of R-NAND composite gate, N
The output of the AND gate is input to the NAND gate of the composite gate, and the output of the NOR-NAND composite gate is inverted by an inverter and taken out as an output signal ○.

In this circuit, input signal wire 1 and wire 2 are both high.
If the level is high, NMOST N7 and TN8 become conductive, the output section 28 of the NAND gate becomes low level, and PMO3TP9 becomes conductive.

Therefore, 2, which is the output part of the NOR and NAND composite gate.
Part 4 becomes high level, and the inverter's NMOS
T N12 becomes conductive, and the output signal ◯ becomes low level.

When input signals 11 and I2 are at high and low levels, respectively, PMOS T ps and NMO8T and F are conductive, and part 23 is at high level, so NMo8
TN9 becomes conductive. At this time, since NMO8TNil is also conductive, part 21 becomes low level, and P M O
When S and T p1□ are conductive, the output signal ◯ becomes high level. Similarly, when the input signals 1 and 2 are at low and high levels, respectively, the output signal ○ is at high level.

When input signals I, I2 are both at low level,
PMO8T2□ of NOR-NAND composite gate. Since TPll and TPll are conductive, the section 24 is at a high level and the output signal 0 is at a low level.

[Problems to be Solved by the Invention] In the conventional mismatch circuit described above, it is necessary to use as many as 12 transistors, so if this was implemented on an integrated circuit, the LSI chip would be large and the cost would be high. Conventional matching circuits similarly require a large number of transistors.

[Means for Solving the Problems] In the logic circuit according to the present invention, the first input terminal is connected to the first MO
The second input terminal is connected to the source of the second MOS transistor and the gate of the first MOS transistor, and the second input terminal is connected to the source of the second MOS transistor and the gate of the first MOS transistor. The drains are wired together, and the drain of a third MOS transistor for precharging (or predischarging) is wired to the wired connection.

[Embodiments] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention, and is an example of a mismatch circuit (exclusive OR circuit). Of the two input signals 1 and 2 to be operated, one input signal 1 is input to the source of NMo5TN1 and the gate of NMo3TN2, and the other input signal Izi, t, NMo
The source of 3TN2 is input to the gate of NMo5TN1. Further, the source of PMOSTp+, which is a precharge transistor to which the precharge signal 3 is inputted to the gate, is connected to the positive power supply VDD, and the drains of these three transistors TN1, TN2, and TPl are wire-connected. The output signal from the above circuit is output to the P+ section which is the wired connection point, and this signal is input to the inverter consisting of PMOS Tp□ and NMo8TN3, where it is inverted and output as the output signal O. Ru.

Next, the operation of the circuit shown in FIG. 1 will be explained with reference to FIG. 2, which is a timing chart of the circuit shown in FIG. In this circuit, while the precharge signal 3 is at a low level (precharge period [rpc), the P+ section is precharged, and when this precharge period ends, the data output device 1m (To+, TD2, TD3, ).

First, a case where both input signals 11 and I2 are at low level will be described. At the end of the precharge period Tpo, part 21 is set to high level. Subsequently, the output period TD starts, but N M OS T
Since both Nt and TN2 are not conductive, the P section remains at a high level, and the output signal O becomes a low level.

When the input signals I, I2 are at low and high levels (data output period TD2), NMO3T becomes conductive,
The section 21 becomes low level, and the output signal ◯ becomes high level. Similarly, when the input signals r, I2 are at high level and low level (data output period TD3), the output signal ○ is at high level. Both input signals It and I2 are at high level (output period T
oa), since NMOS T N 1 and TN2 are not conductive, the section 21 remains at high level, and the output signal becomes low level.

As described above, the output signal ◯ is the exclusive OR of the input signals 1 and I2.

Next, another embodiment of the present invention will be described with reference to FIG. In this example, the N M OS of the previous example
T N I and TN2 are replaced with PMOS TP3 and Te3, and PMO 3 TP1 for precharging is replaced with N MOS T N4 for precharging. In addition, the PMO is connected to part 22, which is the wired connection point.
3T3. , N M OS T N 5 and an inverter formed of P M OS Te6 and N M OS T N6 are connected.

In this embodiment, NMO8TN4 for bridge discharge is made conductive by the bridge discharge signal 4, and 22
The data output period begins after the signal goes low. When the input signals I+ and I2 are both low level (or high level), P M OST P3,
Since both Te3 are not conductive, portion 22 remains at a low level, and the output signal also becomes a low level. On the other hand, when the input signals I and I2 are at low and high levels (or high and low levels), P M OS T
Since e4 (or P M OS Te3) is conductive,
The section 22 becomes high level, and the output signal ◯ also becomes high level. Therefore, exclusive OR operation is performed in this circuit as well.

In the above embodiments, a mismatch circuit has been described, but a match circuit can be constructed by removing or adding one stage of inverters from the embodiment circuit.

[Effects of the Invention] As explained above, according to the present invention, a mismatch circuit or a match circuit can be constructed using three to five transistors, which is half of the 10 to 12 transistors required in the prior art. The following transistors can be used. Therefore, when this type of logic circuit is integrated, LSI
Chip size can be reduced and costs can be reduced. Or if the chip size is constant,
Larger scale circuits can be integrated.

[Brief explanation of drawings]

1 and 3 are circuit diagrams showing embodiments of the present invention, FIG. 2 is an explanatory diagram of the operation of the circuit shown in FIG. 1, and FIG. 4 is a circuit diagram showing an embodiment of the present invention.
FIG. 2 is a circuit diagram showing a conventional example. It, 12... Input signal, ■,... Precharge signal, I4... Bridischarge signal, O
・・Output signal, TN1~TN12 ・・N channel MOS transistor, TP1~TPI2...P
Channel MOS transistor, 'T'pc...Precharge period, TD1~To4...Data output period. GnD Figure 1

Claims (1)

[Claims] a first MOS transistor having a source connected to a first input terminal, a gate connected to a second input terminal, and a drain connected to an output terminal; a source connected to the second input terminal and a gate connected to the first MOS transistor; a second MOS transistor connected to the first input terminal and having a drain connected to the output terminal; and presetting means for setting the potential of the output terminal to a constant potential prior to a logic operation period. logic circuit.