JPH02267946A - Package for semiconductor device - Google Patents

Abstract

PURPOSE:To enable the performance of WSI(Wafer Scale Integration) to be enhanced by a method wherein inner lead parts conforming to the outer peripheral shape of a semiconductor substrate to be internally mounted are formed. CONSTITUTION:The title package for semiconductor device is provided with a die pad part 5 for mounting a semiconductor substrate 1, inner lead parts 6a, 6b formed around and inside the die pad part 5 so as to be engaged with the notch parts of the semiconductor substrate 1 and to be bonded onto the specific positions of the semiconductor substrate 1 and outer pins 8 electrically connected to the inner lead parts 6a, 6b. Then, the inner lead parts 6a, 6b formed in the package are formed on the positions to be engaged with the WSI wafer whereon various notch parts, etc., are formed. Through these procedures, inner lead parts 6a, 6b corresponding to the numbers of the parts 3 of the WSI wafer 1 can be formed, thereby enabling the performance of the WSI to be enhanced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a package for a semiconductor device, and in particular to a WS package.
This invention relates to an improvement in the bonding structure of a semiconductor device package for loading an I-wafer.

[Conventional technology] LSI (Large 5cale Integ)
By further developing the concept of
2. Description of the Related Art There are semiconductor devices configured as integrated circuits having one integrated function, such as microprocessors and microprocessors. Such semiconductor devices are WSI
(Wafer 5cale 1ntegrati
on).

An example of a conventional WSI is shown in FIGS. 13 and 14.

FIG. 13 is a schematic plan view of the wafer 1 of WSI. Further, FIG. 14 is a schematic perspective view of the WSI package 2 into which the wafer 1 is loaded. The WSI wafer 1 has a circular cross-sectional structure.

On the main surface of the WSI wafer 1, many integrated circuits such as logic circuits are formed. Further, a plurality of wire bonding pads 3 are provided on the outer peripheral edge thereof.

The WSI package 2 has a WS in the center of the package body 4.
A die pad section 5 on which an I-wafer 1 is placed is provided. The package body 4 is composed of a multilayer substrate mainly made of ceramic. A plurality of inner leads 6 are formed around the die pad portion 5 . The inner leads 6 are formed so as to face the wire bonding pads 3 of the WSI wafer 1 when the WSI wafer 1 is loaded on the die pad portion 5 . Then, the inner lead 6 and the wire bonding pad 3 are wired. Furthermore, a seal ring 7 is formed on the outer periphery of the inner lead 6. The seal ring 7 maintains airtightness when the lid (not shown) and the package body 4 are attached. A plurality of external pins 8 are formed below the package body 4. This external pin 8 is electrically connected to the wire bonding pad 3 of the WSI wafer 1 via the inner lead 6.

Further, other examples of conventional WSI are shown in FIGS. 15 and 16. In this example, a WSI formed on a wafer having a substantially square main surface is shown.

Its basic structure is similar to the above example.

When the structural features of such WSI are listed in comparison with LSI, the following points can be mentioned.

(1) Because it has many logic circuits and memory circuits,
It requires a large number of pads for inputting and outputting signals to and from the outside.

(2) It is difficult to shorten the wire length between the pad and the pad in order to reduce the access time on the wafer.

(3) Individual WSIs are expensive and require high manufacturing yields.

(4) Since it has many functions, circuit tests for each functional unit are performed in multiple steps.

[Problems to be Solved by the Invention] As described above, in the WSI, an integrated circuit having many functions is configured. Therefore, many input/output units are required for input/output with the outside.

That is, on the WSI wafer 1 side, it is necessary to arrange many wire bonding pads 3 around the WSI wafer 1. Further, in the WSI package 2, it is necessary to form a large number of inner leads 6 and external pins 8 in an array.

On the other hand, the area required for wire bonding of the wire bonding pad 3 or the inner lead 6 has a minimum value. That is, a gold wire or the like is used as the bonding wire. Then, this wire is welded to the surface of the bonding pad 3 or the surface of the inner lead 6 for bonding. For this reason, there is a minimum surface area of the wire bonding pad 3 or inner lead 6 that can process this welded portion. On the other hand, WS
The outer peripheral length of the I-wafer 1 is determined by the size of the wafer. Therefore, the number of wire bonding pads 3 that can be arranged around the outer periphery of the WSI wafer 1 is necessarily limited. Further, the number of inner leads 6 on the WSI package 2 side is also regulated for the same reason. Therefore, WSIs having high-performance logic circuits or integrated logic circuits and memory circuits that require a larger number of pads than the regulated number have the problem that their formation is restricted due to the limit on the number of pads. Ta.

Therefore, the present invention has been made to solve the above-mentioned problems, and is a WSI with an increased number of pads.
An object of the present invention is to provide a package for a semiconductor device in which a wafer can be loaded and signals can be completely exchanged with the outside.

[Means for Solving the Problems] A package for a semiconductor device according to the present invention has a wafer scale size, and a peripheral saw is integrated into a main surface of a semiconductor substrate having a cutout inside. This device houses a semiconductor device on which an integrated circuit with a specified function is formed, and includes a die pad section on which the semiconductor substrate is placed, and a die pad section around and inside the die pad section that fits into the notch of the semiconductor substrate. The semiconductor device includes an inner lead portion formed and bonded to a predetermined position of a semiconductor substrate, and an external pin electrically connected to the inner lead portion.

[Function] The inner lead portion formed in the semiconductor device package is formed at a position where it fits into the WSI wafer in which various cutouts and the like are formed. This makes it possible to form inner lead parts corresponding to the number of pad parts of the WSI wafer, and it is possible to configure input/output leads according to the functions of the integrated circuit of the WSI wafer.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is an exploded structural diagram of a WSI according to a first embodiment of the present invention. The WSI includes a WSI wafer 1 and a WSI package 2. The WSI wafer 1 has a circular opening 12 formed in its center. Furthermore, a plurality of wire bonding pads 3 are formed around the outer periphery of the WSI wafer 1 and the outer periphery of the circular opening 12. A test pad 3a used only for circuit testing is formed at a predetermined location among the plurality of wire bonding pads 3.

The WSI package 2 includes a package body 4 made of a multilayer substrate made of ceramic.

A die pad portion 5 on which the WSI wafer 1 is placed is formed in the center of the package body 4 . A convex portion 13 a that fits into the opening 12 of the WSI wafer 1 is formed at the center of the die pad portion 5 . A plurality of inner leads 6a and 6b are formed on the outer surface of the convex portion 13a and the outer peripheral surface of the die pad portion 5. Inner leads 6a, 6
The number of pads b corresponding to the number of wire bonding pads 3 on the WSI wafer 1 is formed. Furthermore, the inner leads 6a and 6b are each connected to a plurality of external pins 8 protruding from the lower surface of the package body 4. Further, a seal ring 7 is formed on the upper surface of the package body 4.

The WSI wafer 1 is assembled into a predetermined position of the WSR package 2 and wire bonded.

After that, the upper surface is sealed with M14.

FIG. 2 is a structural perspective view showing a state in which the WSI wafer 1 is assembled into the WSI package 2 and wire-bonded. Wire bonding pads 3 formed on the outer or inner periphery of the WSI wafer 1 are wired to inner leads 6a and 6b of the WSI package 2, respectively. In the case where the WSI wafer 1 has a circular opening 12 in the center, the number of pads can be increased by the number of wire bonding pads 3 formed near the circular opening 12.

A second embodiment of the invention is shown in FIGS. 3 and 4. FIG.

FIG. 3 is a plan view of the structure of the WSI wafer 1. Figure 4 shows a WSI for loading the WSI wafer 1 shown in Figure 3.
FIG. 2 is a structural perspective view of a package 2. FIG. Referring to Figure 3,
The WSI wafer 1 in this example has a plurality of notches 15 on its outer periphery. Furthermore, a plurality of wire bonding pads 3 are formed along the outer periphery of the WSI wafer 1 in which the notch 15 is formed. The area where the wire bonding pad 3 is formed is formed by forming a notch 15 around the outer periphery of the WSI structure/11, so that the area where the wire bonding pad 3 is formed is different from the conventional circular WS.
■Increased compared to wafer 1.

For this reason, the number of wire bonding pads 3 can be increased. At the same time, test pads 3a for circuit testing are formed on the outer periphery of the WSI wafer 1.

The WSI package 2 includes a package body 4, a die pad section 5 on which the WSI wafer 1 is placed, inner leads 6a, s, 6b and external pins 8 for electrical connection to the wire bonding pads 3 of the WSI wafer 1. ing. Further, at a predetermined position on the outer peripheral edge of the die pad portion 5, a convex portion 13 that fits into the notch 15 of the WSI wafer 1 is provided.
b is formed. Furthermore, inner leads 6b are formed on the upper surface of the convex portion 13b. In the assembled state of the device, the protrusion 13b of the WSI package 2 fits into the notch 15 of the WSI wafer 1. Then, the wire bonding pads 3 of the WSI wafer 1 adjacent to each other and the WS
The inner lead 6b of the protrusion 13b of the I package 2 is wire-bonded.

5 and 6 show a third embodiment of the invention.

This embodiment has a structure in which the first embodiment and the second embodiment are mutually combined. That is, the WSISl wafer 1 has a notch 15 and a circular opening 12 formed at its circular outer periphery and at its center, respectively. The wire bonding pad 3 is formed along the periphery of the notch and the circular opening 12 of the WS1 wafer 1. Furthermore, test pads 3a for circuit testing are appropriately arranged within the wire bonding pads 3.

In addition, in the WSI package 2, the die pad portion 5
Convex portions 13b and 13a are formed at positions corresponding to the cutout portion 15 of the WSISl wafer 1 and the circular opening portion 12, respectively.

Furthermore, a fourth embodiment of the present invention is shown in FIGS. 7 and 8. FIG. 7 shows the WSISl of this embodiment.
FIG. 1 is a structural diagram of one side of a wafer. Figure 8 shows the WSI of this invention.
FIG. 2 is a structural perspective view of a package 2. FIG. Referring to Figure 7,
A circular opening 12 is formed in the center of the WSISl wafer 1 of this embodiment.
Furthermore, a notch 12a extending in a cross direction from this circular opening is formed. A plurality of wire bonding pads 3 are formed along the circular opening 12, the notch 12a, and the circular outer peripheral edge. Furthermore, a test pad 3a for circuit testing is appropriately formed within this wire bonding pad 3.

Referring to FIG. 8, the WSI package 2 has a convex portion 13a formed in the center of the die pad portion 5 to fit into the WSISl wafer 1 type opening 12 or the like.

A fifth embodiment of the invention is shown in FIGS. 9 and 10. FIG. 9 is a structural diagram of one side of a WSISl wafer according to this embodiment. FIG. 10 is a structural perspective view of the WSI package 2 of this embodiment.

Referring to FIG. 9, WS4 wafer 1 has a square shape. A circular opening 12 is formed in the center of the WSISl wafer 1. Wire bonding pad 3 is WSISl
They are formed in alignment with the periphery of the wafer 1 and the outer periphery of the circular notch 12 .

Circuit test pads 3a are formed at predetermined positions in the array of wire bonding pads 3.

Referring to FIG. 10, the WSI package 2 includes a square die pad portion 5 on which a square WSISl wafer is placed. A convex portion 13g having a shape that fits into the WSISl wafer 1 type opening 12 is formed in the center of the die pad portion 5. Inner leads 6a are formed on the outer surface of this circular convex portion 13a. Furthermore, the die pad section 5
Similarly, a plurality of inner leads 6b are formed on the outer periphery of the inner lead 6b.

Furthermore, a sixth embodiment of the present invention is shown in FIGS. 11 and 12. Figure 11 shows the WS of this embodiment.
FIG. 1 is a structural diagram of one side of an ISL wafer.

FIG. 12 is a structural perspective view of the WSI package 2 of this embodiment.

Referring to FIG. 11, the WSISl wafer has a rectangular shape. A circular opening 12 and a notch 12a extending in a cross direction from the circular opening 12 are formed in the center thereof. Wire bonding pad 3 is WSISl
A plurality of them are formed in alignment on the outer peripheral edge of the rectangular shape of the wafer, the circular opening 12, and the outer peripheral edge of the notch 12a.

Test pads 3a for circuit testing are formed at predetermined positions in the array of a plurality of wire bonding pads 3.

Referring to FIG. 12, WSI package 2 includes a square die pad portion 5 on which WSI wafer 1 is placed. A convex portion 13a is formed in the center of the die pad portion 5 and has a shape that fits into the WSISl wafer 1 type opening 12 and the notch 12a. Inner leads 6a and 6C are formed on the outer peripheral surface of the convex portion 13a. Further, inner leads 6b are similarly formed on the outer peripheral surface of the die pad portion 5. Each inner lead 6a, 6b, 6c is connected to an external pin 8, respectively.

In the above embodiments, the shape of the WSI wafer 1 is circular or square, but the shape is not limited to this, and other shapes such as a rectangular shape may be used.

[Effects of the Invention] As described above, since the semiconductor device package according to the present invention has an inner lead portion formed in accordance with the outer peripheral shape of the semiconductor substrate placed inside the package, the required number of input/output leads required for WSL can be formed. This makes it possible to realize higher performance of the WSI loaded in a semiconductor device package.

[Brief explanation of drawings]

FIG. 1 is an exploded perspective view of a WSI according to a first embodiment of the present invention. FIG. 2 is a structural perspective view showing the wire bonding state of the WSI shown in FIG. 1. Third
4 is a plan structural view of a WSI wafer according to a second embodiment of the present invention, and FIG. 4 is a structural perspective view of a WSI package for loading the WSI wafer shown in FIG. 3. FIG. 5 is a plan structural view of a WSI wafer according to a third embodiment of the present invention, and FIG. 6 is a structural perspective view of a WSI package for loading the WSI wafer shown in FIG. FIG. 7 is a plan structural view of a WSI wafer showing a fourth embodiment of the present invention, and FIG. 8 is a structural perspective view of a WSI package for loading the WSI wafer of FIG. FIG. 9 is a plan structural view of a WSI wafer showing a fifth embodiment of the present invention, and FIG. 10 is a structural perspective view of a WSI package for loading the WSI wafer of FIG. 9. FIG. 11 is a WSI diagram showing a sixth embodiment of the present invention.
12 is a plan view of the wafer, and FIG. 12 is a plan view of the wafer.
FIG. 2 is a structural perspective view of a WSI package for loading an SI wafer. FIG. 13 is a plan view of a conventional WSI wafer. FIG. 14 is a structural perspective view of the WSI package for loading the WSI wafer of FIG. 13. FIG. 15 is a plan view of a WSI wafer showing another conventional example, and FIG. 16 is a WSI wafer shown in FIG.
FIG. 2 is a structural perspective view of an SI package. In the figure, 1 is a WSI wafer, 2 is a WSI package, 3 is a wire bonding pad, 3a is a test pad, 6.6a, 6b, and 6c are inner leads, 12 is a circular opening, and 12a is a circular opening 12. Continuous cross notches, 13a and 13b are convex portions, and 15 is a notch. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A semiconductor device having a wafer scale size and having an integrated circuit with one integrated function formed on the main surface of a semiconductor substrate having a notch on its outer periphery or inside. A package for a semiconductor device, comprising: a die pad portion on which the semiconductor substrate is placed; and a die pad portion formed around or inside the die pad portion so as to fit into a notch of the semiconductor substrate; A package for a semiconductor device, comprising: an inner lead portion bonded to a predetermined position on a substrate; and an external pin electrically connected to the inner lead portion.