JPH022655A - Method and apparatus of cooling integrated circuit package - Google Patents
Method and apparatus of cooling integrated circuit packageInfo
- Publication number
- JPH022655A JPH022655A JP63321855A JP32185588A JPH022655A JP H022655 A JPH022655 A JP H022655A JP 63321855 A JP63321855 A JP 63321855A JP 32185588 A JP32185588 A JP 32185588A JP H022655 A JPH022655 A JP H022655A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- peg
- integrated circuit
- circuit package
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001816 cooling Methods 0.000 title claims description 13
- 238000000034 method Methods 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims abstract description 55
- 229910000679 solder Inorganic materials 0.000 claims abstract description 33
- 239000011248 coating agent Substances 0.000 claims abstract description 25
- 238000000576 coating method Methods 0.000 claims abstract description 25
- 238000005476 soldering Methods 0.000 claims abstract description 17
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000007747 plating Methods 0.000 claims abstract 8
- 230000017525 heat dissipation Effects 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 230000005855 radiation Effects 0.000 abstract 1
- 239000000919 ceramic Substances 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000005219 brazing Methods 0.000 description 2
- 229920000742 Cotton Polymers 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000005028 tinplate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
- H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/06—Thermal details
- H05K2201/066—Heatsink mounted on the surface of the PCB
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09572—Solder filled plated through-hole in the final product
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10727—Leadless chip carrier [LCC], e.g. chip-modules for cards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10954—Other details of electrical connections
- H05K2201/10969—Metallic case or integral heatsink of component electrically connected to a pad on PCB
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/0455—PTH for surface mount device [SMD], e.g. wherein solder flows through the PTH during mounting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
Abstract
Description
【発明の詳細な説明】
本H,明は集積回路パッケージの冷却、特にハイブリッ
ド回路に表面配置する目的のパッケージに関する。ハイ
ブリッド回路は「基板」と呼ばれる平J1.Iな支持体
上に高い部品密度で電子部品を組立てたちのである。基
板はその一面または両面にd3いて抵抗体や導電路の印
刷ネットワークで被覆された酵いセラミック板であり、
ネットワークは任意的にガラス化絶縁層で保護され、導
電路はパッドに至るが、該パッドはすすめつきされ旦つ
ハイブリッド回路部品やピンを外部装置に連続する役目
を覆る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to cooling integrated circuit packages, particularly packages intended for surface placement in hybrid circuits. The hybrid circuit uses a plain J1. Electronic components can be assembled with high component density on a rigid support. The substrate is a hardened ceramic plate coated on one or both sides with a printed network of resistors and conductive tracks;
The network is optionally protected by a vitrified insulating layer, and conductive paths lead to pads which, once attached, serve to connect the hybrid circuit components and pins to external devices.
北門の昔日
この種の目的に用いられる集積回路パッケージは通常セ
ラミックカップの形であり、該カップは金属の蓋で閉鎖
され且つ表面配置の目的でその外部の回りに外部接続パ
ッドを有する。前記バッド締
はカップの壁を通過する供rA路を介して内部接続パッ
ドに接続する。内部接続パッドは集積回路チップに接続
し、該チップはカップの内部に設けられた金属化領域に
固定され、その底においてろう付けまたははんだ付けで
固定される。Integrated circuit packages used for this type of purpose in the Beimen era were usually in the form of a ceramic cup, which was closed with a metal lid and had external connection pads around its exterior for surface placement purposes. The pad fasteners connect to the internal connection pads via a supply line passing through the wall of the cup. Internal connection pads connect to the integrated circuit chip, which is secured to a metallized area provided inside the cup and secured by brazing or soldering at its bottom.
この型の集積回路パッケージの冷却法の1例は、熱放散
金属部分を集積回路と直接熱的接触にあるセラミックカ
ップの底の外部に接着またはスナップ0
1止めすることである。パッケージをハイブリッド回路
の上に逆さまに配置する。この方式の欠点はラジェータ
の質量を集積回路パッケージにより支持しなければなら
ぬ点で、より脆くなりまた外部接続パッドと基板の4電
路との間のはんだ付けをより脆くする。弛の欠点は基板
を熱放散体として用いてない点であり、同時に一般的に
よく印刷回路に配lりされるハイブリッド回路の高さを
苔しく」(1加することである。One example of a method for cooling this type of integrated circuit package is to glue or snap a heat dissipating metal part to the outside of the bottom of the ceramic cup in direct thermal contact with the integrated circuit. Place the package upside down on top of the hybrid circuit. A disadvantage of this approach is that the mass of the radiator must be supported by the integrated circuit package, making it more fragile and making the soldering between the external connection pads and the four circuits on the board more fragile. The drawback of this is that it does not use the substrate as a heat dissipator, and at the same time it increases the height of hybrid circuits that are commonly installed in printed circuits.
本発明はこれらの欠点を除去することである。The present invention is to eliminate these drawbacks.
発明の概要
本発明は、基板の上に配置するため集積回路パッケージ
を冷IIする方法であって、該り法は、集積回路パッケ
ージの底の外側表面に、はんだ付けによる固定に適当な
すずめつき被覆領域を設c) 、
末梢回路パッケージが位置づけられるべきゾーンで、す
板には法基板の両面に2つのすずめつさ゛被覆領域を相
互に重ねて設Cプ、その第1のすずめつき被覆領域は集
積回路パッケージの底の゛す゛ずめっぎ被覆領域と対面
して配置され、またその第2のすずめつき被覆領域は基
板を貫通する少なくとも1つの被覆貫通孔を介して第1
の領域と連通するものであり、
更に、集積回路パッケージの底をづ1fめっき被覆領域
が面と面とが向ぎ合うような仕方です板の1油
靴へはんだ(=Jけし、またペグを基板の下のレベルに
Jりいて集積回路パッケージとはんだ伺けし、該ペグは
基板の第2のずずめっき被覆にそれ自体かはIνだ付け
できるようなすずめつき被゛C表面を有しており、さら
に該ペグは、づザめつき被覆表面内に開口する毛細管に
その一端が終結し且つはんだ受容部によってその他端が
終結する少なくとも1つの金属檗の通路により孔があけ
られてJjす、萌記通路が基板と集積回路パンク−−ジ
との間の過剰はんだを被覆貫通孔を互いに経由して吸収
する役目をなしている方法である。SUMMARY OF THE INVENTION The present invention is a method of cooling an integrated circuit package for placement on a substrate, the method comprising: attaching a tin plate to the bottom outer surface of the integrated circuit package suitable for fixation by soldering; C) A coating area is provided in the zone where the peripheral circuit package is to be located, and the base board is provided with two tin-covered areas on both sides of the base board, one over the other, the first tin-covered area being placed on top of the other. is disposed opposite a tin plated coating area on the bottom of the integrated circuit package, and the second tin plated coating area is connected to the first tin plated coating area through at least one coating through hole through the substrate.
Furthermore, the plated areas on the bottom of the integrated circuit package are placed face to face. The integrated circuit package and solder are mounted at the lower level of the substrate, and the peg has a tinned surface such that it can be attached to the second tinned coating of the substrate. and the peg is perforated by at least one metal hollow passageway terminating at one end in a capillary opening into the serrated coating surface and terminating at the other end in a solder receptacle; In this method, the solder passage serves to absorb excess solder between the substrate and the integrated circuit puncture through the coating through-holes.
基板がもし集積回路パッケージから発生する熱を放散す
るのに足るものであれば、ペグは基板とはほんの小さい
接触領域で配置されるようにされ、従ってはんだ付は後
にペグは容易に分離し且つ集積回路パッケージの底と基
板との間の過剰はんだは吸収され、それはペグを基板に
固定するはんだを破壊するだけで行なわれる。If the board is sufficient to dissipate the heat generated by the integrated circuit package, the pegs can be placed with only a small contact area with the board, so that after soldering the pegs can easily separate and Excess solder between the bottom of the integrated circuit package and the board is absorbed, simply by breaking the solder that secures the pegs to the board.
本発明は上記方法を実施するための冷ムlI装置をも提
供する。The invention also provides a cold brew apparatus for carrying out the above method.
もしペグが除かれないと、基板は集積回路パッケージと
熱放散金属ペグとの間にはさまれる事になる。このため
機械的力がペグから集積回路パッケージまたはその外側
接続パッドでのはんだ付は接続へ伝わるのが妨げられる
。加うるに集積回路パッケージの冷却が基板それ自体で
または他に基板の下にはんだ付けされた金属ペグにより
行なわれるかのいずれかによらず、主に印刷回路に配置
されるハイブリッド回路の全体の8槓を小さくすること
は可能である。何とならば印刷回路にとにかく設けられ
る空虚なスペース内の孔にペグを収めるからである。If the pegs are not removed, the board will become wedged between the integrated circuit package and the heat dissipating metal pegs. This prevents mechanical forces from being transferred from the peg to the soldering connections at the integrated circuit package or its external connection pads. In addition, whether the cooling of the integrated circuit package is carried out either on the board itself or by means of metal pegs soldered underneath the board, the entire hybrid circuit is primarily placed on a printed circuit. It is possible to make the size smaller than 8. This is because the pegs fit into holes in empty spaces that would otherwise be provided in the printed circuit.
集積回路パッケージを基板にろう付(プすれば、パッケ
ージと基板との間の熱的接触は接着やスナップ固定手段
のfill立てに比べて茗しく向上づ゛る。Brazing an integrated circuit package to a substrate provides much improved thermal contact between the package and the substrate compared to adhesive or fill-in snap fasteners.
しかしこの種の組立てははんだの過剰の問題に苦しみ、
それはすずめつき1!2覆操作時の堆積はんだ向の制御
が困難であることから起こる。この1結果、集積回路パ
ッケージが基板に対してその高さが不適切なものになり
、ためにその外側接続パッドと基板導電路上のパッドと
のはんだ(4けを妨げ、または種々のパッド間に短絡の
架橋が生ずる。この問題はべlグをパッケージをはんだ
付は覆るのと同時に基板の他の端にはんだト1けするこ
とで解決され、その場合は基板に設けられた1つ以上の
被覆貫通孔を通って過剰はんだが吸込まれる。それは通
路の毛III管部分のはんだに作用する表面張力のため
であり、一方はんだによって集積回路パッケージとペグ
は良い熱的接触を保持している。However, this type of assembly suffers from the problem of over-solder,
This occurs because it is difficult to control the direction of the deposited solder during the 1!2 stacking operation. The result of this is that the integrated circuit package is at an inappropriate height relative to the board, thus preventing the solder between its outer connection pads and the pads on the board's conductive tracks, or between the various pads. This problem can be solved by soldering the bell over the package at the same time as placing a solder on the other end of the board, in which case one or more Excess solder is sucked through the sheathing perforations due to surface tension acting on the solder in the capillary portion of the passageway, while the solder maintains good thermal contact between the integrated circuit package and the peg. .
本発明の具体例は、添イ4の図面と参照することにより
よ<Fl解されるであろう。Embodiments of the present invention will be better understood with reference to the drawings in Attachment A4.
具体例
第1図はハイブリッド回路を示し、該回路は低抗体と電
子部品13を表明配置するづずめっき被覆の接続パッド
12に通ずる導電路11との印刷ネットワークを支持す
る基板10を合み、さらに集積回路パッケージ14、端
子パッド15への接続を合み、該端子パッドはハイブリ
ッド回路を外部接続するためにはんだ付けした電気接続
ピン16を備える。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a hybrid circuit which combines a substrate 10 supporting a printed network of conductive tracks 11 leading to tin plated connection pads 12 on which electronic components 13 are disposed. It also includes connections to the integrated circuit package 14 and terminal pads 15, which include soldered electrical connection pins 16 for externally connecting the hybrid circuit.
基板10は薄いセラミックの仮で、その−面または両面
が、シルクスクリーン印側法による低抗体と導電路11
のネットワークで被覆されている。ネットワークは任意
的にガラス化した絶縁層(不図示)で保護されているが
、すずめつきの目的で接近可能に残して置く接続パッド
12.15は例外とする。The substrate 10 is a thin ceramic temporary, and its negative side or both sides are coated with a low antibody and conductive path 11 by a silk screen printing method.
covered by a network of The network is optionally protected by a vitrified insulating layer (not shown), with the exception of connection pads 12.15, which are left accessible for tinting purposes.
表面装置のための集積回路パッケージ14は、金属の監
21にJ:って閉鎖される長り形のセラミックカップ2
0の形をしてJ3す、またその周辺には、第2図で示す
長方形接触領域23の形でパッケージの下に伸びる外部
接続パッド22を右する。The integrated circuit package 14 for the surface device is an elongated ceramic cup 2 that is closed by a metal cap 21.
J3 in the shape of a 0, and around its periphery are external connection pads 22 extending under the package in the form of a rectangular contact area 23 shown in FIG.
ピン16はそれぞれヘッド17を有する。該ヘッドはだ
の縁端子バッド15において、基板の縁部上に配置され
るべくつめを介してはめ合わされる。ピンは基板10に
対して垂直に延び、ハイブリッド回路が次により大面積
の印11回路上に配置できるようにするが、該ハイブリ
ッド回路は印刷回路の少し上方に位置することになる。Each pin 16 has a head 17. The head is fitted onto the edge terminal pad 15 via a pawl to be placed on the edge of the board. The pins extend perpendicular to the substrate 10, allowing the hybrid circuit to then be placed on the larger area of the mark 11 circuit, but the hybrid circuit will be located slightly above the printed circuit.
ハイブリッド回路部品は、基板10が裸でいる間にそれ
をすずめつきすることから成る通常の「リフロー」技術
を用いて組立てられる。それによると接続パッド12.
15の上にはんだの小片を形成せしめ、それ自身の接続
バンドを有する部品や基板10上のピンを基板10のパ
ッド上のはんだ小片と接触丈るように配置し、それらを
接着剤または−・時的支持手段を介して適所に保持し、
続いて組立体を加熱して部品やピンのすべてを同時には
んだ付けするが、基板上のはんだ片が溶融し且つはんだ
が毛管作用により部品のパッド並びにピンのつめの上に
移動するまで実施する。The hybrid circuit components are assembled using conventional "reflow" techniques that consist of bonding the board 10 while it is bare. According to it, connection pad 12.
15, place a pin on the component or board 10 with its own connection band in contact with the solder patch on the pad of the board 10, and bond them with adhesive or... held in place via temporary support means;
The assembly is then heated to solder all of the components and pins simultaneously until the solder strips on the board melt and the solder migrates by capillary action onto the pads of the components and onto the pin tabs.
通常の電子部品の他に、熱放散体を41¥4成する切頭
円錐形金属ペグ30が、果梢回路パッケージ14の位瞠
″C:基板10の底面下に配置される。リフロー操作の
間において、この金属ペグは集積回路パッケージ14の
底と同時的に基板10にはんだ付けされ、また他の部品
もそれにはんだ付けされる。ペグとパッケージに関して
はんだ付けされるのは3つのすずめつき被覆領域で(第
1図では見えない)、その1つは集積回路パッケージ1
4の上にあってその底の外側表面の中央′C−あり、そ
の他の2つは基板10の両面で一致した位置である。In addition to the usual electronic components, a frusto-conical metal peg 30 forming a heat dissipator is placed under the bottom surface of the substrate 10 of the circuit package 14. In between, this metal peg is soldered to the substrate 10 simultaneously with the bottom of the integrated circuit package 14, and other components are also soldered thereto.Soldered with respect to the peg and package are three tinned sheaths. (not visible in Figure 1), one of which is integrated circuit package 1
4 at the center of its bottom outer surface; the other two are at coincident positions on both sides of the substrate 10.
第2図は集積回路パッケージ14を構成し且つその周辺
に長方形の接触領域23を含む長方形カップの底部外側
を示す。接触領域は外側接続バラ[S22へ伸び、該パ
ッドはカップの側壁に受納され基板上の接続パッド12
にはんだ付けされる。カップの中央にはこの場合は円形
で示されたすずめつき被覆領域24を含み、それは長方
形の接触領域とは電気的に絶縁されており、またカップ
20の底を基板10にはんだ付けし得るようにするもの
である。FIG. 2 shows the bottom exterior of the rectangular cup that constitutes the integrated circuit package 14 and includes a rectangular contact area 23 around its periphery. The contact area extends to the outer connection pad [S22, which pad is received in the side wall of the cup and connects to the connection pad 12 on the substrate.
to be soldered. The center of the cup includes a tinted covering area 24, shown in this case as a circle, which is electrically insulated from the rectangular contact area and which allows the bottom of the cup 20 to be soldered to the substrate 10. It is something to do.
第3図は基板の被覆具通孔31の位置での断面である。FIG. 3 is a cross section of the substrate at the position of the covering through hole 31.
該ホールは集積回路パッケージ14を受入れる位置のほ
ぼ中央にある。同図にはまた基板10の上方の集積回路
パッケージ14の側面図と、基板の下方に熱放散金属ペ
グ40だ断面で示される。The hole is approximately centrally positioned to receive integrated circuit package 14. The figure also shows a side view of the integrated circuit package 14 above the substrate 10 and a cross section of the heat dissipating metal peg 40 below the substrate.
基板10はすずめつき状態で示されている。集積回路パ
ッケージ14に隣接するその面上で、基板は、集積回路
パッケージ14の長方形接触領域23と外部接続パッド
22との間の交差点に面して接続パッド12を有する。Substrate 10 is shown tinted. On its side adjacent to integrated circuit package 14 , the substrate has connection pads 12 facing the intersection between rectangular contact area 23 of integrated circuit package 14 and external connection pads 22 .
長方形の周辺を形成する接続パッド12の中央に(よ、
対面するパッケージ14の底におけるすずめつき被覆領
域24とその形と寸法においで相応するすずめつき被覆
領域32を有する。集積回路パッケージ14から離れて
面する基板10の反対面は、別のすずめつき被覆領域3
3を持ち、この領域は被覆貫通孔31を介しおよび選択
的には他の被覆貫通孔を介し第1領域32と連絡するが
、それは領1戎32と33の寸法に依存する。すずめつ
きによって被覆貫通孔31ははんだで充填され、接続パ
ッド12やすずめつき被覆領域32.33の各々ははん
だ片35゜41においで基板10のすずめつき被覆領域
33(この場合円形)にはんだ付けされる。ペグには軸
方向通路が設けられ、1つの毛細管42を介して底面4
1ル
内で終端し且つ該管は基板10内の被覆貫通崩31の近
傍に開[]シ、該通路は他方では反対底面近く開口し、
毛細管よりは大きい直径のはんだ受容部43に通ずる。In the center of the connection pad 12 forming the perimeter of the rectangle (
It has a tinted covering area 24 on the bottom of the facing package 14 and a tinted covering area 32 corresponding in shape and size. The opposite side of the substrate 10 facing away from the integrated circuit package 14 has another tinted coating area 3.
3, and this region communicates with the first region 32 via a sheathing through-hole 31 and optionally through other sheathing through-holes, depending on the dimensions of the regions 1 and 32 and 33. By tinting, the coating through-hole 31 is filled with solder, and each of the connecting pads 12 and the tinted coating area 32,33 is soldered to the tinned coating area 33 (in this case circular) of the board 10 at the solder piece 35°41. be done. The peg is provided with an axial passage through one capillary tube 42 to the bottom surface 4.
1, and the tube opens in the vicinity of the coating penetration 31 in the substrate 10, and the passage, on the other hand, opens close to the opposite bottom surface;
It leads to a solder receptacle 43 having a larger diameter than the capillary tube.
リフロー操作の間において、集積回路パッケージ14と
熱放散ペグ40が、すずめつき被覆領域32゜cプる。During the reflow operation, integrated circuit package 14 and heat dissipating pegs 40 are pulled over tinted coverage area 32°c.
熟成VAペグは適当な洗浄フラックスで予め処理されて
いるので、小片36.37に含まれる過剰はんだは、ペ
グを1通る通路の毛細管部42による表面張力現象のた
めに吸引され、第4図の受容部43内の位置を占めるよ
うになる。このために集積回路パッケージ14は基板表
面に対し密接に押圧され、またその外部接続パッドの長
方形接触順VA23のずべては基板10の接続パッド上
のはんだ小片35に接触するようになり、接続パッドが
適当にすべての場合にはんだ付けされるのを保証し、パ
ッドとすずめつき被覆領域24または32との間に現れ
る該ペグは小面積の底面を持つ直径の小さいもので、従
って集積回路パッケージ14から発生する熱を基板10
が放rllするのにそれ自体で足りる場合は、1.4板
10へのはんだ付は接続は脆くかつ容易にこわれる。Since the aged VA peg has been pre-treated with a suitable cleaning flux, the excess solder contained in the pieces 36,37 will be sucked out due to surface tension phenomena by the capillary section 42 of the passage through the peg, as shown in FIG. It now occupies a position within the receiving part 43. This causes the integrated circuit package 14 to be pressed tightly against the substrate surface, and the rectangular contact order VA23 of its external connection pads all come into contact with the solder strips 35 on the connection pads of the substrate 10, so that the connection pads The pegs appearing between the pads and the tinted covering area 24 or 32 are of small diameter with a small area of the bottom surface and are therefore soldered properly in all cases, so that the integrated circuit package 14 The heat generated from the substrate 10
If the soldering to the 1.4 board 10 is sufficient on its own to release the rll, the connection is brittle and easily broken.
第6、第7、第8図は円筒形また(よ切頭円錐形の熱放
散ペグの別のタイプである。これらは角度を持つ1つ以
上の通路で穴がおいてσ)って、基板から最も離れたペ
グ面を占有するのを販けるようにしてあり、従って加工
に対して自由性を残し、例えば増加する半径方向領域の
ために熱放散プレートを固定する手段を備える。Figures 6, 7 and 8 are another type of cylindrical or frusto-conical heat dissipation pegs. These are perforated with one or more passages with an angle σ It is possible to occupy the peg face furthest from the substrate, thus leaving freedom for processing, e.g. with means of fixing the heat dissipation plate for increased radial area.
第6図は底面51を介しV板10にはんだ付けするため
の円筒形熱放散ペグ50の断面を示す。該ペグ50は角
度づけされた4つの通路(その内3つが見えている)を
有し、4角形の隅で底面51内に開口する毛細管部分5
2.53または54を各々の通路が持ち、また側面に開
口するtまんだ受容部55.56.57をそれぞれが有
している。基板から最ち遠いペグの底面51−にはねじ
切りされた目孔58があけられ、熟成1タブレート59
を固定するためのねじ58−を受取る。FIG. 6 shows a cross section of a cylindrical heat dissipating peg 50 for soldering to the V-plate 10 through the bottom surface 51. The peg 50 has four angled passages (three of which are visible) with a capillary section 5 opening into the bottom surface 51 at the corner of the square.
2.53 or 54, and each has a side-opening T-shaped receptacle 55.56.57. A threaded hole 58 is drilled in the bottom surface 51- of the peg furthest from the substrate, and a maturing 1 table plate 59 is formed.
Receives screws 58- for fixing.
第7図と第8図は第1図に見られるものと同イ、にな切
頭円錐形熱放散ペグの斜視図であり、小底面が基板10
にはんだ付けされるようになっている。7 and 8 are perspective views of a truncated conical heat dissipation peg similar to that seen in FIG.
It is designed to be soldered.
第7図のペグ30は第1図のハイブリッド回路に固定し
たものと同類である。該ペグはそれを通る分岐通路を有
し、基板10へはんだ付はゴる小底面62を員く外側末
端で開口する予備通路61で、さらにペグの側壁に開口
する複数の分岐部64.65.66゜67との交差点に
あるチャンバ63に直角に交わりその内側末端を開口す
る該通路61から成り、また前記分岐部ははんだ受容部
を形成する。第8図のペグ70は第6図のペグと同様に
角度をもつ4つの通路があけられており、各々は切頭円
錐体の1袖に平行’、E ツレ自oの毛1111[71
,72,73,74を有し、dつ4角形をなす4隅の各
々で小底面75に開口してa>す、また各々の通路は、
切頭円錐体の軸に直角で且つ側面を員いて開口するはん
だ受容部76、7?。The pegs 30 of FIG. 7 are similar to those secured to the hybrid circuit of FIG. The peg has a branch passage through it, with a preliminary passage 61 opening at the outer end of the base 62 for soldering to the board 10, and a plurality of branches 64, 65 opening into the side walls of the peg. .66°67, said passageway 61 intersects at right angles to a chamber 63 and opens at its inner end, and said branch forms a solder receptacle. The peg 70 of FIG. 8, like the peg of FIG. 6, is bored with four angular passages, each parallel to one sleeve of the truncated cone.
, 72, 73, 74, each of which opens into the small bottom surface 75 at each of the four corners of the d quadrilateral, and each passage is
Solder receptacles 76, 7 that open at right angles to the axis of the truncated cone and along the sides. .
78、 79を有する。78, 79.
本発明の主旨を逸脱することなく、仲々の配置が変更さ
れ■つ等画手段で秤々の手段が代替公れよう。特に熱放
散ペグは諸要望と外部表面の関数として半棉体ラジェー
タで通常であるフィンや溝を付すこともできる。基板か
ら晶も離れたペグの面にはねじ切り孔以外の固定手段も
用意でき、リベット用ボルトであり、またはねじ付きシ
ャンクであり得る。従ってペグから物7電を除く欠点、
すなわちペグの熱伝導性や不活性の附属影響をもっこと
を回避できる。Without departing from the spirit of the present invention, the arrangement of the scales could be changed and the scale means could be replaced by a drawing means. In particular, the heat dissipation pegs can also be provided with fins or grooves, as is usual in half-cotton radiators, as a function of requirements and external surface. The face of the peg remote from the substrate can also have fixing means other than threaded holes, which can be rivet bolts or threaded shanks. Therefore, the disadvantage of removing the object 7 electric from the peg,
That is, the thermal conductivity of the peg and the effects of inert attachments can be avoided to a large extent.
第1図は本発明の冷却装置を用いて配置した集積回路パ
ッケージを取付けたハイブリッド回路の一部切取り概略
斜視図、第2図は第1図の集積回路パッケージの下方か
らの斜視図、第3図は基板にはんだ付けする前の、集積
回路パッケージと本発明による冷却装置を示す部分1斬
而図、第4図は基板にはんだ付けした後の集積回路パッ
ケージとその冷却装置の部分断面図、第5図は第3図と
第4図で示した冷却装置の斜視図、第6図は第3、第4
、第5図に示す冷却装置の変形例の断面図、10・・・
・・・基板、11・・・・・・低抗体と4電路、14・
・・・・・集積回路パッケージ、16・・・・・・ピン
、30、40.50.70・・・・・・熱放散ペグ、[
34,67・・・・・・通路。
ヒ
匡
匡1 is a partially cutaway schematic perspective view of a hybrid circuit equipped with an integrated circuit package arranged using the cooling device of the present invention; FIG. 2 is a perspective view from below of the integrated circuit package of FIG. 1; FIG. 4 is a partial sectional view of the integrated circuit package and the cooling device according to the present invention before being soldered to the substrate; FIG. 4 is a partial sectional view of the integrated circuit package and its cooling device after being soldered to the substrate; Figure 5 is a perspective view of the cooling device shown in Figures 3 and 4, and Figure 6 is a perspective view of the cooling device shown in Figures 3 and 4.
, a sectional view of a modification of the cooling device shown in FIG. 5, 10...
...Substrate, 11...Low antibody and 4 electric circuits, 14.
...Integrated circuit package, 16...Pin, 30, 40.50.70...Heat dissipation peg, [
34,67...Aisle. Hi Confident
Claims (9)
却する方法であつて、該方法は、 集積回路パッケージの底の外側表面に、はんだ付けによ
る固定に適当なすずめっき被覆領域を設け、 集積回路パッケージが位置づけられるべきゾーンで、基
板には該基板の両面に2つのすずめっき被覆領域を相互
に重ねて・設け、その第1のすずめっき被覆領域は集積
回路パッケージの底のすずめっき被覆領域と対面して配
置され、またその第2のすずめっき被覆領域は基板を貫
通する少なくとも1つの被覆貫通孔を介して第1の領域
と連通するものであり、 更に、集積回路パッケージの底をすずめっき被覆領域が
面と面とが向き合うような仕方で基板の上部へはんだ付
けし、またペグを基板の下のレベルにおいて集積回路パ
ッケージとはんだ付けし、該ペグは基板の第2のすずめ
っき被覆にそれ自体がはんだ付けできるようなすずめっ
き被覆表面を有しており、さらに該ペグは、すずめっき
被覆表面内に開口する毛細管にその一端が終結し且つは
んだ受容部によってその他端が終結する少なくとも1つ
の金属壁の通路により孔があけられており、前記通路が
基板と集積回路パッケージの底との間の任意の過剰はん
だを被覆貫通孔を互いに経由して吸収する役目をなして
いる方法。(1) A method of cooling an integrated circuit package for placement on a substrate, which method comprises: providing a tin-plated coating area on the bottom outer surface of the integrated circuit package suitable for fixation by soldering; In the zone where the circuit package is to be located, the substrate is provided with two tin-plated areas superimposed on each other on both sides of the substrate, the first tin-plated area being the tin-plated area on the bottom of the integrated circuit package. the second tin-plated coating area is in communication with the first area through at least one coating through-hole through the substrate; The plating areas are soldered to the top of the board in a face-to-face manner, and the pegs are soldered to the integrated circuit package at the bottom level of the board, with the pegs bonding to the second tin plating area of the board. the peg has at least one end terminating in a capillary tube opening into the tin plating surface and the other end terminating in a solder receptacle; A method in which one metal wall is perforated by a passageway, said passageway serving to absorb any excess solder between the substrate and the bottom of the integrated circuit package through the coated through-holes to each other.
、ペグは基板に対して小さい領域を介して接触がなされ
ており、さらに基板にはんだ付けされた後は単なる破壊
によってペグが基板から分離される請求項1に記載の方
法。(2) The peg is in contact with the board through a small area so that the connection to the board by soldering is fragile, and furthermore, after soldering to the board, the peg separates from the board by mere breaking. The method according to claim 1.
却する装置であって、基板の両面の共通位置において該
両面の各々に配置されたすずめつき被覆領域を介して集
積回路パッケージの底と共にはんだ付けされた熱放散ペ
グを有しており、基板の前記すずめつき被覆領域は少く
とも1つの被覆貫通孔を介して相互に連通するようにな
っており、また前記熱放散ペグは、基板の近傍に開口す
る毛細管によって一端が終結し且つはんだ受容部によっ
てその他端が終結する少なくとも1つの金属壁の通路に
よって孔があけられている装置。(3) an apparatus for cooling an integrated circuit package for placement on a substrate, the device comprising: soldering the integrated circuit package together with the bottom of the integrated circuit package at a common location on both sides of the substrate through tinted coating areas disposed on each of the sides; heat dissipation pegs attached thereto, the tinned coating areas of the substrate are in communication with each other via at least one coating through hole, and the heat dissipation pegs are arranged adjacent to the substrate. 2. A device perforated by at least one metal wall passageway terminating at one end by a capillary tube opening into the opening and at the other end by a solder receptacle.
毛細管と、基板から離れて向き合うペグの面を占有する
のを避けるべく該ペグの側面内に開口するはんだ受容部
とから成る少くとも1つの角度を持つ通路によつて孔あ
けされている請求項3に記載の装置。(4) The heat dissipation peg comprises a capillary tube opening into the surface facing the substrate and a solder receptacle opening into the side surface of the peg to avoid occupying the surface of the peg facing away from the substrate. 4. The device of claim 3, wherein the device is perforated by a passage having at least one angle.
へ開口し、一方でははんだ受容部を形成してペグの側面
内に開口する複数の分岐部間の交差点にあるチャンバ内
にペグ内部を開口する毛細管を含む分岐通路により孔あ
けされている請求項3に記載の装置。(5) said heat dissipating peg is located in a chamber at the intersection between a plurality of branches that open to the outside of the peg on the side facing the substrate and on the other hand form solder receptacles and open into the sides of the peg; 4. The device of claim 3, wherein the device is perforated by a branch passageway containing a capillary tube opening into the interior of the peg.
形の隅にその毛細管の外側端部が開口し且つそのはんだ
受容部がペグの側面の周りで開口する複数の角度付き通
路によつて孔があけられている請求項4に記載の装置。(6) the heat dissipation peg has a plurality of angled passages with the outer ends of the capillaries opening at the corners of the square on the side of the peg facing the substrate and with the solder receptacles opening around the sides of the peg; 5. The device of claim 4, wherein the device is perforated.
定手段を有し、前記固定手段がペグを熱放散プレートに
固定させるものである請求項3に記載の装置。7. The apparatus of claim 3, wherein the heat-dissipating peg has securing means on a surface facing away from the substrate, the securing means securing the peg to the heat-dissipating plate.
の装置。8. The apparatus of claim 3, wherein the heat dissipation peg is cylindrical.
記載の装置。9. The apparatus of claim 3, wherein the heat dissipation peg is frustoconical.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR8717920A FR2625038B1 (en) | 1987-12-22 | 1987-12-22 | METHOD AND DEVICE FOR COOLING AN INTEGRATED CIRCUIT HOUSING |
FR8717920 | 1987-12-22 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH022655A true JPH022655A (en) | 1990-01-08 |
Family
ID=9358156
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63321855A Pending JPH022655A (en) | 1987-12-22 | 1988-12-20 | Method and apparatus of cooling integrated circuit package |
Country Status (6)
Country | Link |
---|---|
US (1) | US4924352A (en) |
EP (1) | EP0321899B1 (en) |
JP (1) | JPH022655A (en) |
CA (1) | CA1278878C (en) |
DE (1) | DE3853413T2 (en) |
FR (1) | FR2625038B1 (en) |
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-
1987
- 1987-12-22 FR FR8717920A patent/FR2625038B1/en not_active Expired - Fee Related
-
1988
- 1988-12-19 EP EP88121209A patent/EP0321899B1/en not_active Expired - Lifetime
- 1988-12-19 DE DE3853413T patent/DE3853413T2/en not_active Expired - Fee Related
- 1988-12-20 JP JP63321855A patent/JPH022655A/en active Pending
- 1988-12-20 CA CA000586393A patent/CA1278878C/en not_active Expired - Fee Related
- 1988-12-21 US US07/287,251 patent/US4924352A/en not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3305485A1 (en) | 1982-02-18 | 1983-11-03 | Centre National de la Recherche Scientifique (C.N.R.S.), 75700 Paris | HALOGENIDE-CONTAINING GLASSES, THEIR PRODUCTION AND THEIR USE FOR PRODUCING MOLDED BODIES, GRINDING PRODUCTS OR OPTICAL FIBERS |
JP2018101661A (en) * | 2016-12-19 | 2018-06-28 | 新電元工業株式会社 | Mounting substrate and heat generating component mounting module |
Also Published As
Publication number | Publication date |
---|---|
US4924352A (en) | 1990-05-08 |
DE3853413D1 (en) | 1995-04-27 |
DE3853413T2 (en) | 1995-09-21 |
FR2625038A1 (en) | 1989-06-23 |
EP0321899A1 (en) | 1989-06-28 |
EP0321899B1 (en) | 1995-03-22 |
FR2625038B1 (en) | 1990-08-17 |
CA1278878C (en) | 1991-01-08 |
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