JPH0226473A - Scanning adding device - Google Patents

Abstract

PURPOSE:To easily adding a scanning >=2 bits by storing a deciding signal from a scanning adding circuit and the data of then in plural one line delay components. CONSTITUTION:A scanning adding device provides a reference area output circuit 11, a scanning adding deciding circuit 12, a discriminating signal storing circuit 13, a scanning adding result storing circuit 14 and a scanning adding result output control circuit 15. Then, a deciding signal as a scanning adding deciding result from the scanning adding deciding circuit 12 and the data of then are stored in respective plural one line delay components 61-64, and the output of the scanning adding result is controlled by them. Thus, the processing of more than two dots can be executed easily.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a recording device that handles line drawings, and more particularly to a device for changing the width of the line drawings.

(Prior Art) Conventionally, the width of the line drawing described above has been changed by making it thicker or thinner by one dot in the sub-scanning direction. For example, when printing newspapers or magazines, the width of the line drawing may be narrower than the actual width depending on the performance of the printing press. that time,
With conventional devices, it was possible to compensate for the characteristics of the printing press by increasing the width of the line drawing. It could also be used to simply make line drawings thicker or thinner.

FIG. 7 is a block diagram showing an example of a drawing line addition device according to the prior art. In FIG. 7, 21 is a reference area output circuit, and 22 is a ROM-based drawing line addition utilization circuit.

In the conventional drawing line addition device shown in FIG. 7, only the judgment of drawing drawing addition is made using the ROM.

Therefore, it is only possible to widen or narrow the dot by one dot in the sub-scanning direction, and it is not possible to process two or more dots.

(Problems to be Solved by the Invention) As mentioned above, in the present invention, since only the addition of a drawing line is determined by the ROM, it is possible to accumulate only one dot in the sub-scanning direction or to narrow it down. However, it has the disadvantage that it cannot process two or more dots.

An object of the present invention is to store a determination signal as a result of the image addition determination and the data at that time in a plurality of one-line delay elements, and to control the output of the image addition result using these elements. It is an object of the present invention to provide a drawing line adding device which eliminates the above-mentioned drawbacks and is configured to be able to process two or more dots.

(Means for Solving the Problems) A drawing line addition device according to the present invention includes a reference area output circuit, a drawing addition determination circuit, a discrimination signal storage circuit, a drawing addition result storage circuit, and a drawing addition result output control. It is constructed by fully equipping the circuit.

The reference area output circuit is for outputting a reference area in the sub-scanning direction.

The drawing line addition determination circuit is for determining whether the reference area matches a predetermined pattern.

The determination signal storage circuit is for storing a determination signal for determining whether or not to add a two-dot dividing line in the sub-scanning direction, among the image line addition determination outputs.

The drawing line addition result storage circuit is for storing data in which one dot of drawing line is added in the sub-scanning direction, out of the drawing line addition determination output.

The drawing line addition result output control circuit is for controlling the output of drawing line addition determination output data and drawing line addition result storage data based on the discrimination signal storage data.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a drawing line adding device according to the present invention.

In FIG. 1, 11 is a reference area output circuit, 12 is an object addition determination circuit, 13 is a discrimination signal storage circuit, 14 is an object addition result storage circuit, and 15 is an object addition result output control circuit.

In FIG. 1, from the terminal 101 to the reference area output circuit 11
Binary serial data is input to. The reference area output circuit 11 stores the input data line by line, and when the data for 5 lines has been stored, the 5
It is assumed that one dot is sequentially read out from each line.

In explaining the present invention, a reference area of 1 dot in the main scanning direction and 5 lines/line in the sub-scanning direction will be explained as shown in FIG. Of course, other numbers of lines and dots can be realized in a similar manner. Also, for simplicity, it is assumed that the drawing line conversion method is to convert one dot to two dots or convert one dot to three dots. Of course, other changes can be implemented in a similar manner. Furthermore, for simplicity, the pixel conversion direction is set to the black side. Of course, the white side can also be realized in a similar manner. The blank marks in FIG. 2 represent the pixels of interest in the reference area at a given time, and the black marks represent pixels that are output by reflecting the result of drawing lines in the reference area.

In FIG. 1, data output from the reference area output circuit 11 is input to the drawing line addition determination circuit 12, and the following processing is executed. The determination itself is performed by a ROMK provided inside the image addition determination circuit 12.

First, as shown in FIG. 3, it is assumed that one dot is converted into two dots. At this time, if a pattern as shown in FIG. 3(a) is input to the main drawing line addition determination circuit 12, addition of one dot as shown in FIG. 4 (dark) will be performed. Pixels marked with ■ are converted.

Next, suppose that one dot is converted into three dots as shown in FIG. At this time, case I, which is the same as in Figure 3,
There is also a second case in which a determination signal indicating whether or not the pattern shown in FIG. 3 has been determined is output dot by dot in the main scanning direction.

Next, in the first case, among the two outputs from the drawing line addition determination circuit 12, one is input to the drawing line addition result output control circuit 15, and the other is input to the drawing line addition result storage circuit 1.
4 is input.

Further, for the second case, the signal is input to the determination signal storage circuit 13.

In the drawing line addition result storage circuit 14, the drawing line addition determination circuit 12
The drawing line addition determination data from is delayed in units of one line. Similarly, in the discrimination signal storage circuit 13, the discrimination signal data is delayed in units of one line. Due to these delays, when the data advances by one line, the third dot can be added as shown in FIG. 4(b)K. This process is
This is performed by the drawing line addition result output control circuit 15. The determination as to whether or not to add the third dot is made based on the data in the determination signal storage circuit 13. Through the above processing, the data at the positions marked with ■ in FIGS. 2 to 4 is output from the terminal 102 in FIG.

FIG. 5 is a block diagram showing details of the reference area output circuit 11 of FIG. 1.

In FIG. 5, 61 to 64 each represent one line delay element.

In FIG. 5, when binary serial data is input to the terminal 601, one is output to the terminal 602,
The other one is input to the one-line delay element 61. One of the data output from the 1-line delay element 61 is output to the direct terminal 603, and the other is input to the 1-line delay element 62. Similarly, serial data is transmitted to terminals 604-6.
06, and input to 1-line delay elements 61-64. In this way, data of 1 rai/minute can be delayed line by line to output data of 5 rai/minute.

FIG. 6 is a block diagram showing details of the drawing line addition result output control circuit 15 of FIG. 1.

In FIG. 6, 71 to 73 are AND gates, respectively;
74 is an OR gate, and 75 is an inverter.

In FIG. 6, the drawing line addition result output control circuit receives data from the drawing line addition determination circuit 12 and the drawing line addition result storage circuit 1.
This is to control which of the data from 4 and 4 is output.

In FIG. 6, is it the addition of one dot to the terminal 701?
A fixed signal is input to select whether to add two dots or to add two dots. Here, when one dot is added, the output is low level, and when two dots are added, the output is high level. When adding one dot is selected, the discrimination signal from the discrimination signal storage circuit 13 is ignored. Therefore, terminal 7
The drawing line addition determination data from 04 is output from the terminal 705.

Furthermore, when adding two dots is selected, the discrimination signal from the discrimination signal storage circuit 13 becomes valid. Therefore, if the discrimination signal is a signal whose pattern has been determined by the image addition determination circuit, the data from the image addition result storage circuit 14 is transferred to the terminal 703.
If the signal is not determined, the data from the image line addition determination circuit 12 is received from the terminal 704 and outputted to the terminal 705. This means that when viewed from the main scanning direction, the addition of a line in units of one dot may or may not be determined to be the same as that one dot.

(Effects of the Invention) As explained above, the present invention stores the determination signal from the image line addition determination circuit and the data at that time in a plurality of one-line delay elements, so that two or more dots can be detected. This has the effect that drawing lines can be added easily.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a drawing line adding device according to the present invention. f! 42 to 4 are explanatory diagrams each showing the process of adding drawing lines to data. FIG. 5 is a block diagram showing details of the reference area output circuit of FIG. 1. FIG. 6 is a block diagram showing details of the drawing line addition result output control circuit of FIG. 1. FIG. 7 is a block diagram showing an example of a drawing line adding device according to the prior art. 11.21... Reference area output circuit 12.22... Object addition determination circuit 13... Discrimination signal storage circuit 14... Object addition result storage circuit 15-- Object addition result output control circuit 61 ~64...1 line delay elements 71-73...AND gate 74...OR gate 75...Inverter 101.102.201 701-705...Terminal, 202,601-606°

Claims (1)

[Claims] a reference area output circuit for outputting a reference area in the sub-scanning direction; a drawing line addition determination circuit for determining whether the reference area applies to a predetermined pattern; and a drawing line addition determination output. A discrimination signal storage circuit for storing a discrimination signal for determining whether or not to add a dividing line of 2 dots in the sub-scanning direction; a drawing line addition result storage circuit for storing data to which drawing lines have been added; and a drawing line addition result storage circuit for controlling output of the drawing line addition determination output data and the drawing line addition result storage data based on the discrimination signal storage data. 1. A drawing line addition device comprising a drawing addition result output control circuit.