JPH02264578A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To compensate the unevenness of the characteristics of a horizontal reading circuit by detecting the output difference between the clamp output level and the signal output level of the horizontal reading circuit before and after the reset clamp of the input terminal of the horizontal reading circuit. CONSTITUTION:The horizontal read selection switching MOSFETs 17-1 and 17-2 are activated by the horizontal scan pulses phiS1 and phiS2, the signal voltages V01 and V02 are obtained at the output terminals of the load resistance 20-1 and 20-2 connected to the video lines 18-1 and 18-2 by the input voltage of a MOS source follower circuit with its source follower action. Simultaneously, the signal voltages of picture elements SIT 10-11 and 10-12 and a clamp output level appear at the voltages V01 and V02 of the lines 18-1 and 18-2 since the horizontal selection pulses phiS3-phiS5 are applied. Both voltages V01 and V02 are inputted to a correction circuit which fetches these voltages by an amount equal to the difference between the clamped output level and a signal output level. Thus, it is possible to obtain an output after correcting the variance of the input/output characteristics of the MOS source follower circuit.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an amplifying solid-state (imaging device) using an X-Y addressing method, and in particular, the present invention relates to an amplifying solid-state imaging device using an The present invention relates to an amplification type solid-state imaging device that receives a signal in a circuit and reads out the signal to the outside.

[Conventional technology]

As a conventional solid-state image device, a MOS type or CCD type image sensor is generally known. However, if you try to make an image sensor for a 1-inch high-definition camera using these conventional image sensors, the pixel size will be 7.
It is about 3 μm (horizontal) x 7.6 μm (vertical) and the saturation charge amount is about 8 x 10', making it increasingly difficult to ensure a sufficient dynamic range. It has now become clear that since scanning (75M) (z) is performed at a higher speed, heat generation of the element and the entire drive circuit system becomes a problem.

2/3-inch image pickup tubes are starting to appear as image pickup tubes for high-definition cameras, but 2/3-inch image pickup tubes are also starting to appear in solid-state imaging devices.
Considering that it is necessary to reduce the pixel size to 3/3 inch, the pixel size must be further reduced, which reduces the dynamic range.
The disadvantages of conventional solid-state imaging devices become more pronounced.

The inventors of the present invention have developed an amplified type S I=T (Static Indu
As a measure to improve the vertical smear characteristics of image sensors, we have developed an amplified SIT image sensor that receives the voltage signal information of the vertical signal line in a source follower circuit via a gate switch and reads the signal externally via a video line. - JP-A-63-1
It is disclosed in No. 31662.

This configuration is shown in the 10th diagram. In the figure, 10-11
゜10-12. ...10-14.10-21.1
0-22. ...10-24.・・・・・・・・・10
-44 denotes SITs forming a pixel, and in this configuration example, for convenience of explanation, these SITs are arranged vertically and horizontally in a matrix of 4 rows and 4 columns. Each source of the vertically arranged SIT is connected to a vertical signal line 11-1.11-2.・
...11-4, and the gates of the SITs arranged horizontally are connected to the row line 12-4 through a capacitor.
L L2-2. . . . are respectively connected to 12-4. And vertical signal line 11-1.11-2°,...
・11-4 is sample MOS FET16-1
．． 16-2°...16-4 drain-source path, readout MOSFET T21-1.2
1-2. ...21-4, and sample MO3FETs 16-1, 16-2.
. . . The sample and hold pulses φ and A are commonly applied to each gate of 16-4. In addition, a read MOS FET21-L21-2.
...The drain of 21-4 is the substrate power supply V. and their sources constitute the horizontal selection switch.
2°...connected to the video line 18 via 17-4. MOS FET1 for switch? -1
, 17-2, . φ, z,・
...φ, 4 is applied. In addition, the video line 18 includes a load resistor 20 and a reset MO3.
FET19 is connected in parallel, and MO3 for reset
Video line reset pulse φ is applied to the gate of FET19.
□ is applied.

On the other hand, row lines 12 to L 12-2. ...12-
4 is connected to the vertical scanning circuit 14, and the vertical scanning pulse φG
++φcz+...φG4 is applied. Furthermore, vertical signal lines 11-1, 11-2. ...
・・MOS FET1 for the sample of 11-4
6-1.16-2. ...The end opposite to the side connected to 16-4 is the M for vertical signal line reset.
OS F E T15-1.15-2. ...15
The vertical signal line reset pulse φ of the pixel SIT is commonly applied to each gate of these vertical signal line reset MO3FETs. Note that the drains of each SIT constituting a pixel are commonly connected to a drain power supply (2).

Next, to explain the operation of this configuration example, first, the vertical signal line reset MOS
F E T15-1.15-2. ...15-4
is turned on, and the vertical scanning pulse φc+(i=1.2.
) reaches the reset level V11, the diode composed of the gate and source of the pixel SIT connected to that row line 12-j becomes forward biased, and the gate potential becomes the forward dark value voltage of that diode. It becomes φ3,
The source potential becomes GND level. Also, φG+,
When φ is turned off, the gate of the pixel SIT becomes a reverse bias state and starts optical integration. After a predetermined integration time has elapsed, assuming ψG1-V, ll1l, the gate of the pixel SIT in the i-th row becomes a readout state. Be biased.

In this state, the sample MOS F B 716-1
．． 16-2. ...When the sample hold pulse φ8M applied to the gate of 16-4 is set to the old gh level,
The source potentials of the pixels SIT on the first row line are all connected to the sample MOS FET16-1.16-2.・
・・・・Reading MOS F E via 16-4
T21-1.21-2. ...is transmitted to the gate of MOS FET 21-4, and the reading MOS FET 21-1.2 is transmitted even after the sample and hold pulse φI is set to Low level.
1-2. ...It is held at a gate capacitance of 21-4.

Thereafter, the vertical scanning pulse φ and the beam are set to Low level.

Note that the timing for setting φGi'''VRD may be after the sample hold pulse φ8. The scanning pulse φG11l is turned off just before it becomes VIIO, and the scanning pulse φG11l is turned off immediately before it becomes VIIO.

(+-1, 2,...) is at the same timing as φ or is at the reset level during the period when φ is at the old GH level ■
□.

And read MO3FET21-j N=12,・
...4) The voltage signal held in the gate capacitance is the horizontal scanning pulse φs>(j=1.2°...4) during the period when the sample hold pulse φSH is at a low level.
And MOS FET1 for switch? -j is read out sequentially by turning on the output voltage ■. is now available.

[Problem to be solved by the invention]

Although vertical smear is improved in the SIT image sensor using the readout circuit method configured in this way, the horizontal readout circuit (readout MO3FET21-1, 21-2.
...21-4 and selection switch MOS F E
T17-1.17-2. . . . Due to the non-uniformity of the characteristics of the MO3 type source follower circuit (composed of 17-4 and load resistor 20), there is a problem in that a new fixed pattern noise factor is added.

That is, the input/output characteristics of the above MO3 type source follower circuit are as shown in Figure 10.
When the dark voltage (■T) of the FET or MO3FET for the selection switch changes, the curve a shifts as shown in the curve. Further, a similar shift or deformation of the input/output characteristics occurs due to variations in the conductance of the read MO3FET or the selection switch MO3FET. This variation in input/output characteristics appears as fixed pattern noise of vertical stripes on the screen when an imaging operation is performed.

The present invention has been made to solve the above-mentioned problems in conventional amplification type solid-state imaging devices, and provides a solid-state imaging device that can remove fixed pattern noise caused by variations in input/output characteristics of horizontal readout circuits. The purpose is to provide.

[Means and effects for solving the problems] In order to solve the above problems, the present invention provides a first main electrode that has a photoelectric conversion function and a current amplification function, and serves as an output terminal and a first main electrode connected to an external terminal. Amplifying elements having a second main electrode and a control a electrode are arranged as unit pixels in a one-dimensional row line or in a matrix across row lines and column lines, and each pixel arranged in the row line direction is A horizontal selection line commonly connected to the control electrodes of the pixels, and a horizontal selection line connected to the second main electrode of each pixel, respectively.
or a pixel array section including a vertical signal line commonly connected to the second main electrode of each pixel arranged in the column line direction, and a vertical selection circuit for selectively activating the horizontal selection line; It has a sample transistor connected to each of the vertical signal lines, and a horizontal readout circuit including a readout element and a selection switch connected via the sample transistor, and selectively operates the selection switch of the horizontal readout circuit. A solid-state imaging device comprising a horizontal selection circuit for controlling sending of signals to an output video line, comprising a clamping transistor having a first main electrode connected to an input terminal of the horizontal readout circuit, and a control electrode of the clamping transistor. are commonly connected to the control terminals of the selection switches of adjacent horizontal readout circuits, the second main electrodes of the transistors are commonly connected across all horizontal readout circuits to apply a clamp voltage, and the odd-numbered horizontal readout The output terminals of the circuits are connected to the first output video line, and the output terminals of the even-numbered horizontal reading circuits are connected to the second output video line.

With this configuration, the pixel signal readout operation during the horizontal scanning readout period is performed by the horizontal selection signal applied to the selection switch of the horizontal readout circuit connected to each vertical signal line, and immediately after that, the pixel signal readout operation in the horizontal scanning readout period is performed. A clamping transistor is driven by a horizontal selection signal applied to the selection switch of the horizontal readout circuit, and the input terminal of the horizontal readout circuit is reset and clamped to a predetermined voltage. After the input terminal is clamped, the horizontal readout circuit performs a clamp level readout operation in parallel with the signal readout operation of the horizontal readout circuit in the next column. Therefore, by detecting the output difference between the signal output level output from the horizontal readout circuit and the clamp output level before and after the reset/clamp of the input terminal of the horizontal readout circuit, the non-uniformity of the characteristics of the horizontal readout circuit is compensated for and fixed. A pixel signal from which pattern noise has been removed is obtained.

〔Example〕

Next, examples of the present invention will be described. FIG. 1 is a circuit configuration diagram of a first embodiment of the present invention, in which the same components as those of the conventional solid-state imaging device shown in FIG. The present invention, as shown in FIG.
Each read MO3FET21-1.21-2. ...
・・Clamping MOS F for resetting the gate of 21-4, that is, the input terminal whose source is connected to the input terminal of the source follower circuit, and clamping it to a predetermined potential.
E T22-1.22-2. ...22-4 is provided, and MOSFE T22-1.22- for the clamp is provided.
Each gate of 2 and 22-3 is a selection switch MOS FET1? that constitutes an adjacent source follower circuit.
-2゜17-3.Commonly connected to the gate of 17-4,
Horizontal scanning pulse φ3! ,φ,3. φ, 4 is now applied. In addition, in this example, the MO for clamping
A horizontal scanning pulse φ35 is applied to the 3FET22-4. Also, MO3F for the clamp
ET22-1.22-2. ...The drains of 22-4 are commonly connected to the clamp line 23, and the clamp voltage ■. is applied.

And MOS FET17-1 for selection switch.
17-3 is connected to the first video line 18-1 and is a selection switch MOS FET1? -2,17-4
is connected to the second video line 18-2, and each video line 1B-1, 18-2 has a video line reset MO3FET 191, 19-2 and a load resistor 20-2.
1.20-2 are connected in parallel, MO3F E T19-1.19-2 for video line reset
The configuration is such that a video line reset pulse φmV is applied to the gate of the video line reset pulse φmV.

Next, the operation of the solid-state imaging device constructed as described above will be explained with reference to the waveform diagram of FIG. First, vertical scanning circuit 1
When the row line 12-1 connected to 4 is selected and a read pulse appears in the vertical selection signal φGl, the pixel S I
Tl0-1. ...10-4 gate signal voltage VG
I (i-1 to 4) are the vertical signal lines 11-1°, respectively.
...11-4, and becomes Vst (i=1 to 4).

Here 1. (2), =v, +ΔVllll-Vp.

Note that ΔVIID is the increase in floating gate potential of pixel SIT due to the application of the selection pulse of φG, and vP is the increase in the floating gate potential of pixel SI
is the pinch-off voltage of T.

The signal voltage Vs of this vertical signal line is the sample MOS F
E T16-1.16-2. ...16-4 simultaneously converts MOS FET21-i (i = 1 to
4), 17-i (i = 1 to 4), 22-
i (i = 1 to 4) and load resistance 20-1.20-2
It is transmitted to the input terminal of a MOS source follower circuit consisting of and becomes v31. This v sl is approximately equal to v3.

Next, MO3FET17-1 for horizontal readout selection switch
is first activated by the horizontal scanning pulse φ,I, then
The input voltage v,1 of the MOS source follower circuit is transmitted as an output signal voltage VOI proportional to the input voltage to the output terminal of the load resistor 20-1 connected to the first video line 18-1 by the source follower operation. ■. 1 is expressed as follows.

V01-γ'Vsr'+ However, Tζ constant <1. to: constant The operation up to this point is the same as the conventional one.

Next, the horizontal selection pulse φ3t selects the next horizontal readout selection switch MOS FET1? -2 is activated, the load resistor 2 connected to the second video line 18-2
Signal ■ to 0-2. 2, but at the same time, the clamp MO of the previous stage MOS source follower circuit
SFET22-1 is also activated.

On the other hand, as shown in FIG. 2, the horizontal selection pulse φ31 is
By designing the horizontal scanning circuit 13 so that the second selection pulse appears in synchronization with the readout timing of the second pixel, the output signal voltage waveform V in FIG. 2 is obtained. ,
As shown in , the output level of the MOS source follower circuit (hereinafter referred to as the clamp output level of the source follower circuit) when the input terminal of the MOS source follower circuit is reset and clamped to the clamp voltage V, is the first It can be obtained on video line 18-1.

Similarly, the horizontal selection pulse φ31. φs4. φ
By applying 3S, the first video line 1
8-1 output voltage■. 1 has a pixel S I Tl0-1
1 signal output level, the same clamp output level, the signal output level of 1 pixel S I Tl0-13, the same clamp output level appear sequentially, and the second video line 1 day -
2 output voltage V. , the signal output level of pixels SI Tl0-12, the clamp output level, and the pixel SI
The signal output levels of T10-14 and the clamp output level also appear sequentially.

And the output voltage like this ■. l+v. 2 to the correction circuit shown in FIG. 3 which extracts only the difference between the signal output level and the clamp output level, an output is obtained in which variations in the input/output characteristics of each MOS source follower circuit are corrected. That is, in FIG. 3, 31 is a preamplifier or buffer amplifier, 32 is a sample and hold circuit, and 33 is a differential circuit, and each output voltage V o l I V oz is sent to the preamplifier 31.
The successive signal output levels and clamp output levels are inputted via sample pulses SHI and SH2, and are respectively taken into the sample and hold circuit 32 and held.
The differential circuit 33 outputs only the difference. This allows M.O.
Variations in the input/output characteristics of each circuit of the S source follower circuit (mainly due to the readout MO3FET21-L2
1-2. ...Signal output (■) corrected for (due to variations in (■) in 21-4). Il+V. 8z is obtained. At the same time, a signal output is obtained in which the non-uniformity of the horizontal selection pulse waveform outputted from the horizontal scanning circuit 13 is also canceled out.

In order to obtain such a corrected output voltage, horizontal scanning pulses φffl+φMtr as shown in FIG.
FIG. 4 (2) shows a specific example of a shift register type horizontal scanning circuit that generates a scanning pulse with such an output waveform. This circuit example is a shift register type scanning pulse generation circuit that utilizes the operating principle of a bootstrap type inverter, which was disclosed by the present inventor in Special No. 1983-233734. In the figure, 51 is the first basic circuit consisting of three MO3 type transistors Qn +
+ Q L I I Q t + and capacitor CF
The MO3 type transistors QD, II and QL+ connected in series constitute an inverter circuit with nine ports as load transistors and QDI as a driver transistor, and between the power supply Viio and the ground terminal. It is connected. Further, capacitor C1 is a capacitor composed of a MOS diode, and C8 is a parasitic capacitance. The source electrode of the MO3 type input transistor Qt+ is connected to the gate terminal of the load transistor Qi,+, and the start pulse ST is applied to the drain terminal of the transistor QTl, and the transfer synchronization pulse φ is applied to the gate terminal as well. A synchronizing pulse φ2 is applied to the gate terminal of the driver transistor QDI, and the connection point of the MO8 type transistor QprrQt+ forming the inverter circuit serves as an output terminal.

52 is a second basic circuit configured similarly to the first basic circuit 51, and includes an MO3 type transistor Qo + + Q L I I Q t + in the first basic circuit 51.
MOS type transistor Qo t corresponding to each
+ Q t t + Q t t, a feedback capacitor CF, and a parasitic capacitance C5. The drain terminal of the MO3 type transistor Qtz is connected to the output terminal of the first basic circuit 51 so that the output of the first basic circuit 51 is inputted, and the gate terminal of the driver transistor Q o z is connected to the drain terminal of the MO3 type transistor Qtz. A synchronizing pulse φ1 is applied to the gate terminal of the MO3 type transistor Qtt, and a synchronizing pulse φ4 is applied to the gate terminal of the MO3 type transistor Qtt. Below, these first and second basic circuits 51.
52 are connected alternately to form a scanning pulse generation circuit.

Next, the operation of the scanning pulse generation circuit configured as described above will be briefly explained based on the pulse waveform diagram applied to each part shown in FIG. 4 (Bl) and the voltage waveform diagram at each connection point and output terminal. It is assumed that all MO3 type transistors constituting the scanning pulse generation circuit are of N-channel type.

If the start pulse ST is set to be at the "1" level over two cycles of the transfer synchronizing pulse φ3 of the input transistor QTI, the "1 level" will be input to the shift register for 2 bits, and the output terminal LCI+
A continuous 2-bit "1" level pulse as shown in FIG. 4(B) is output to vsct. This effective output pulse portion is shown with diagonal lines.

Figure 4 above ^,! B) contains 2 consecutive bits “°1”
Although a shift register type scanning circuit that outputs a level is shown, a circuit that outputs two consecutive "L" levels is not limited to the above shift register type circuit, and for example, a Duder type randomly accessible scanning circuit can be used. The above output pulse can be easily obtained using a circuit.

Next, a second embodiment will be described. FIG. 5 shows a circuit configuration diagram thereof, and FIG. 6 (B) shows a shift register type scanning circuit that can be used in this embodiment and its signal waveform diagram. First, the shift register type scanning circuit shown in FIG. 6, a3) will be explained. This scanning circuit is exactly the same as the scanning circuit shown in FIG.
output terminal VB.

The output is used as the output of the second output terminal 8, 3 of the scanning circuit. At that time, the first output terminal V
At the same time as the second output pulse of the ICI, the third output terminal v
The first output pulse of scs appears, and as shown in Figure 2 (A
), the horizontal scanning pulse φ3I shown in [11].

They are not separated in timing as in the output pulses for φ,3. Therefore, when a scanning circuit with this configuration is used, source follower circuit outputs for both pulses cannot be taken out from a common video line.

In order to solve this problem, the second embodiment shown in FIG.
The signal output level and clamp output level of one source follower can be extracted as a source follower signal from one video line at a 4-bit period. In addition, in Figure 5, 19-1.19
-2.19-3.19-4 are video line reset transistors, and 20 to 1.20-2.20-3.20-4 are load resistors.

By being able to utilize the scanning circuit shown in FIG. 6 in this way, in the second embodiment shown in FIG.
Therefore, it can be suitably applied to a solid-state imaging device in which the horizontal pixel pitch is arranged at a higher density.

The first and second embodiments described above are applied to a solid-state imaging device in which a signal voltage appearing on a vertical signal line is received by a MOS source follower circuit for each column. The present invention is applicable not only to solid-state imaging devices using this method but also to solid-state imaging devices using other signal readout methods. Such a third embodiment is shown in FIG. That is, in this embodiment, vertical signal lines 11-1, 11-2 . ...11-4 signal voltage for sampling MOS FET T16-1.1
6-2. ...16-4's on/off operation, this signal voltage is used as a signal charge to be transferred to the hold capacitor C.
□-1, C knee 2. . . . It is configured to be held at C, -4. Then, the horizontal selection pulse φ5i (i-1, 2, . . . ) controlled by the horizontal scanning circuit 13
), the signal output level based on the signal charge held by each hold capacitor is read out, and the next horizontal selection pulse φ! ! By taking the difference between the clamp output level outputted by □ (i=1°2,...) in the same manner as in the first embodiment, the horizontal selection switch MOS FET17 -1.17-2.・・・
...C caused by variations in switch characteristics of 17-4
Vertical striped fixed pattern noise on RT (F P N)
can be corrected and removed.

Next, an embodiment in which the present invention is applied to a one-dimensional sensor is shown in FIGS. 8 and 9. The embodiment shown in FIG. 8 includes vertical signal lines 11-1, 11-2. . . . The signal voltage of 11-4 is once received by each source follower circuit, the source follower circuit is selected by the horizontal scanning circuit 13, and the signal is read out. Reference numeral 14a denotes a one-dimensional sensor drive circuit, and the signal readout operation is the same as in the first embodiment, so a description thereof will be omitted.

The embodiment shown in FIG. 9 is an application of the third embodiment shown in FIG. 7 to a one-dimensional sensor, and the vertical signal line 11-L
11-2. ...Hold the signal voltage of 11-4 Capacitor C E L C) I-2, ... C, -
4 and the accumulated signal charge is transferred to the selection switch MOS FET selected by the horizontal scanning circuit 13.
1? -117-2, . . . 17-4, the other operations are the same as those of the above embodiments.

〔Effect of the invention〕

As described above based on the embodiments, according to the present invention, the threshold voltage of the read transistor and the selection switch 7
Clamping due to the clamping operation of the clamping transistor provided in the horizontal readout circuit is caused by nonuniformity in the characteristics of the horizontal readout circuit due to variations in conductance, and nonuniformity in the waveform of the selection pulse of the horizontal selection circuit that drives the selection switch. By detecting the output difference between the front and rear signal output levels and the clamp output level, it is possible to obtain a pixel signal from which fixed pattern noise has been compensated and fixed pattern noise has been removed.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of the solid-state imaging device according to the present invention, FIG. 2 is a signal waveform diagram for explaining the operation of the embodiment shown in FIG. 1, and FIG. 4 is a circuit configuration diagram showing an example of the configuration of a horizontal scanning circuit. FIG. 4) is a signal waveform diagram for explaining its operation. A circuit configuration diagram showing a second embodiment of the invention, and FIG. 6 is a circuit configuration diagram showing an example of the configuration of a horizontal scanning circuit used in the second embodiment. A signal waveform diagram, FIG. 7 is a circuit diagram showing a third embodiment of the present invention, FIGS. 8 and 9 are circuit diagrams showing still other embodiments of the present invention, and FIG. 10 is a circuit diagram showing a third embodiment of the present invention. , a circuit configuration diagram showing a conventional solid-state imaging device, and FIG. 10(B) is a diagram showing the characteristics of its signal readout circuit. In the figure, 10-11.10-12. ... is pixel SIT. 11-1.11-2. ... is a vertical signal line, 12-
1.12-2. . . . Brush line, 13 is a horizontal scanning circuit, 14 is a vertical scanning circuit, 15-1.15-2.
... is MO3FET for vertical signal line reset, 16
-L 16-2.・・・・・ is MOS F for sample
ET, 17-1.17-2. ... is MOS FET for water selection switch, 1B-L 18-2. -1
1.・Video Line, 19-1.19-2.・・・・・・
- MOS FET for video line reset, 2
0-1.20-2. ... is load resistance, 21-1.
21-2. ... is MO3FET for reading, 22
1, 22-2.・・・・・・ is MOS F E for clamp
Indicates T. Patent applicant: Olympus Optical Industry Co., Ltd. Figure 10 (A) Figure 9 (B) Input voltage

Claims (1)

[Claims] 1. An amplification type element having a photoelectric conversion function and a current amplification function, and having a first main electrode connected to an external terminal, a second main electrode serving as an output terminal, and a control electrode. As a unit pixel,
Horizontal selection lines are arranged in one-dimensional row lines or in a matrix across row lines and column lines, and commonly connect the control electrodes of each pixel arranged in the row line direction, and the second main electrode of each pixel. a pixel array section including vertical signal lines connected to each other or commonly connected to the second main electrodes of each pixel arranged in the column line direction; and a vertical signal line for selectively activating the horizontal selection line. It has a selection circuit, a horizontal readout circuit including a sample transistor connected to each of the vertical signal lines, a readout element connected via the sample transistor, and a selection switch, and selectively operates the selection switch of the horizontal readout circuit. A solid-state imaging device comprising a horizontal selection circuit that controls sending of a signal from a horizontal readout circuit to an output video line, the clamping transistor having a first main electrode connected to an input terminal of the horizontal readout circuit; The control electrodes of the transistors are commonly connected to the control terminals of the selection switches of adjacent horizontal readout circuits, the second main electrodes of the transistors are commonly connected across all the horizontal readout circuits to apply a clamp voltage, and A solid-state imaging device characterized in that an output terminal of a th horizontal readout circuit is connected to a first output video line, and an output terminal of an even numbered horizontal readout circuit is connected to a second output video line. 2. An amplification type element having a photoelectric conversion function and a current amplification function and having a first main electrode connected to an external terminal, a second main electrode serving as an output terminal, and a control electrode is used as a unit pixel,
Horizontal selection lines are arranged in one-dimensional row lines or in a matrix across row lines and column lines, and commonly connect the control electrodes of each pixel arranged in the row line direction, and the second main electrode of each pixel. a pixel array section including vertical signal lines connected to each other or commonly connected to the second main electrodes of each pixel arranged in the column line direction; and a vertical signal line for selectively activating the horizontal selection line. It has a selection circuit, a horizontal readout circuit including a sample transistor connected to each of the vertical signal lines, a readout element connected via the sample transistor, and a selection switch, and selectively operates the selection switch of the horizontal readout circuit. A solid-state imaging device comprising a horizontal selection circuit that controls sending of a signal from a horizontal readout circuit to an output video line, the clamping transistor having a first main electrode connected to an input terminal of the horizontal readout circuit; The control electrodes of the transistors are commonly connected to the control terminals of the selection switches of adjacent horizontal readout circuits, the second main electrodes of the transistors are commonly connected across all horizontal readout circuits to apply a clamp voltage, and 4n+1 (n=0, 1, 2,...)
The output terminal of the 4n+2nd horizontal readout circuit is connected to the 1st output video line, the output terminal of the 4n+2nd horizontal readout circuit is connected to the 2nd output video line, and the output terminal of the 4n+3rd horizontal readout circuit is connected to the 3rd output video line. 4n on the line
A solid-state imaging device, wherein output terminals of the fourth horizontal readout circuit are respectively connected to a fourth output video line. 3. The solid-state imaging device according to claim 1 or 2, wherein the readout element of the horizontal readout circuit is comprised of a readout transistor or a hold capacitor. 4. A circuit for time-sequentially sampling the horizontal readout circuit output signal level and the horizontal readout circuit clamp output level that are successively output in the two or four output video lines, and each of the sample circuits described above. 4. The solid-state imaging device according to claim 1, further comprising a circuit for correcting non-uniformity in characteristics of a horizontal readout circuit comprising a differential circuit that outputs an output difference.