JP2833854B2 - Driving method of solid-state imaging device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a solid-state imaging device that can secure desired light receiving sensitivity with simple operation control.

[Prior Art] Recently, a solid-state imaging device using an imaging element in which a junction-type photoelectric conversion element such as an electrostatic induction transistor (SIT) is used as a pixel and an imaging surface is formed by arranging a plurality of pixels in a matrix is known. Various types have been developed.

Incidentally, for example, in Japanese Patent Application No. 2-169758, a solid-state imaging device proposed by the present applicant, that is, an electrostatic induction transistor (SIT) and a reset control transistor connected to the gate electrode of the SIT are referred to as a unit pixel. In such a solid-state imaging device, two imaging modes can be realized by resetting the SIT (resetting pixels) by the reset control transistor. By selectively using such two imaging modes, for example, it is possible to perform imaging according to the state of the object to be imaged (subject).

FIG. 1 shows a schematic configuration of a solid-state imaging device proposed in the above-mentioned Japanese Patent Application No. 2-169758, in which 3 × 3 pixels arranged in a 3 × 3 matrix form a light receiving section 11. 1 illustrates a solid-state imaging device described above. An outline of this type of solid-state imaging device will be described with reference to FIG.

Each of the pixels 11-11, 11-12,... 11-33, which are arranged in a matrix to form the light receiving section 11, has a SIT as a light receiving element and a reset control transistor connected to a gate electrode of the SIT. Each is provided with a P-MOSFET.

The source electrodes of the SITs of the respective pixel columns arranged in the vertical direction are commonly connected to the vertical signal lines 12-1, 12-2, 12-3, respectively, and the SITs of the SITs of the respective pixel rows arranged in the horizontal direction are respectively connected. Each gate electrode is connected to a SIT gate line 13-1, 13 via a capacitor.
−2, 13-3 are connected in common. Each SI
The drain electrode of T is commonly connected to a power supply (not shown).

The gate electrodes of the P-MOSFETs provided in the pixels arranged in the horizontal direction are commonly connected to the P-MOSFET gate lines 14-1, 14-2, and 14-3, respectively. The drain electrode of the P-MOSFET has a common P-
MOSFET drain voltage _VPD is applied.

The vertical signal lines 12-1, 12-2, 12-3 are connected to a transfer pulse φ.
Transfer transistor Q _T1 which is driven by the _T, Q _T2, Q _T3
Are connected to the storage capacitors C ₁ , C ₂ , C ₃ and the gate electrodes of the drive transistors Q _D1 , Q _D2 , Q _D3 , respectively. The source electrodes of the drive transistors Q _D1 , Q _D2 , Q _D3 whose drain electrodes are commonly connected to the power supply V _DD are supplied with horizontal scanning pulses φ _H1 , φ _H2 , φ from the horizontal scanning circuit 16.
And _H3 is connected to the output line 17 via a horizontal selection switch transistors Q _S1, Q _S2, Q _S3 is selectively driven is applied.

Also, the driving transistor Q _D1, Q _D2, Q to a connection point _D3 and horizontal selection switch transistors _{Q S1, Q S2, Q S3} , the reset pulse phi _R1 reset transistor Q _R1 which is driven by being applied, _QR2 and _QR3 are connected respectively.

It should be noted that the output line 17, a load resistor R _L and the output line resetting transistor Q _RV is connected in parallel, the output line by an output line reset pulse phi _RV applied to the gate electrode of the reset transistor Q _RV 17 resets are performed. And the signal voltage from each pixel appearing in the storage capacitors C ₁ , C ₂ , C ₃ is:
The data is read out via a source follower circuit composed of drive transistors Q _D1 , Q _D2 , Q _D3 , switch transistors Q _S1 , Q _S2 , Q _S3 , and a load resistor _RL .

On the other hand, the SIT gate lines 13-1, 13-2, 13-3 are supplied from the vertical scanning circuit (I) 18 with SIT gate control pulses φ _VG1 ,
φ _VG2 and φ _VG3 are applied. In addition, P-MOSFET gate lines 14-1, 14-2, and 14-3 are connected to vertical scanning circuit (II) 19
-MOSFETs are adapted to receive gate control pulses _φVP1 , _φVP2 , _φVP3 .

Further, the vertical signal lines 12-1, 12-2, and 12-3 is grounded via the SIT source line reset transistor Q _SRS1, Q _SRS2, Q _SRS3 the vertical signal line reset pulse phi _R is applied, and Vertical signal line precharge transistor driven by application of vertical signal line precharge pulse φ _PR
It is connected to a precharge voltage source V _PR via Q _PR1 , Q _PR2 , and Q _PR3 .

In the solid-state imaging device configured as described above, by changing the pulse timing related to resetting of each SIT, two imaging modes, that is, an imaging mode in which no afterimage occurs as described below and a high-sensitivity imaging mode, are described. Mode is realized.

The imaging mode in which the afterimage does not occur is that, when performing the light integration operation by the SIT, the initial potential of the SIT gate electrode of each pixel is fixed by conducting the P-MOSFET provided in the pixel. This is a mode in which imaging is performed without setting an afterimage by setting.

FIG. 2A shows pulse timings for realizing an imaging mode in which such an afterimage does not occur. In FIG. 2A, φ _VG1 , φ _VG2 , and φ _VG3 are _output from the vertical scanning circuit (I) 18 to the respective SIT gate lines 13-1, 13-2, _13-3.
, Which controls the gate potential of each pixel SIT when reading a signal through the capacitor. Φ _VP1 , φ _VP2 , φ _VP3
Is, for example, a V _P1, V _P2, 3-value signal of the three voltage V _P3, via the respective P-MOSEFT gate lines 14-1, 14-2, 14-3 from the vertical scanning circuit (II) 19 P-MOSFET gate control pulse applied to the gate of the P-MOSFET of each pixel,
Reset operation of each SIT and P-MOSFE of the excess charge
It controls the overflow operation due to drain discharge to T.

Here focusing on SIT gating pulse phi _VG1, and gating pulse V _P1 of P-MOSFET is applied to the first row of pixels of the light receiving unit 11 reads the pixel signals of the pixels in the first row of the light receiving portion 11 Will be described.

In a period t ₁ ~t _2, a transfer pulse phi _T, a reset pulse phi _R1, the vertical signal line reset pulse phi _R respectively "H"
, So that the transfer transistors Q _T1 , Q _T2 ,
Q _T3, the reset transistor _{Q R1, Q R2, Q R3} , the storage capacitor C ₁ vertical signal line resetting transistor Q _SRS1, Q _SRS2, Q _SRS3 is respectively turned on, C _2, C ₃ is reset You. Note that “H” of each pulse is a voltage level for turning on a MOSFET used as each transistor.
“L” is a voltage level for turning off the MOSFET.

In the subsequent period t ₁ ~t ₂ ', the P-MOSFET gating pulse phi _VP1 becomes voltage V _P1, P-MOSFET in the pixel is turned on. At this time, the gate potential of each SIT in the first row of the pixel column is clamped by the drain voltage V _PD of P-MOSFET, thereby the gate potential is reset. Thereafter, the P-MOSFET gating pulse phi _VP1 at time t ₂ 'is becomes the voltage V _P2, each pixel in the first row starts light accumulation.

The voltage _VR2 is a level at the time of an overflow operation necessary for discharging an excess charge exceeding the surface potential φS _(VP2) under the gate electrode of the P-MOSFET to the drain of the P-MOSFET.

Then comes a period t ₃ ~t _4, the vertical signal line reset pulse phi _R becomes "L", after precharging the vertical signal lines 12-1, 12-2, and 12-3 by the precharge pulse phi _PR, 1
A read level SIT gate control pulse φ _VG1 is applied to each gate of the SIT in the pixel column of the row. In this period, the P-MOSFET gating pulse phi _VP1 becomes the voltage V _P3. This voltage _VP3 is a level for turning off the P-MOSFET.

The reason why the P-MOSFET is turned off during this period is that the photoelectric charge accumulated in the SIT gate at the time of reading is changed to the P-M
This is to prevent the drain from the OSFET from flowing out. Moreover during this period, transfer pulse phi _T becomes "H", since the transfer transistor Q _T1 vertical signal line reset pulse phi _R becomes the _{"L", Q T2, Q} T3 is turned on, the pixel 11 11,11−
Each of the pixel signals of 12,11-13 is the transfer transistor
The data is transferred to and stored in the storage capacitors C ₁ , C ₂ and C ₃ via Q _T1 , Q _T2 and Q _T3 , respectively. Then at time t _4, the transfer transistors Q _T1, Q _T2, Q _T3 even after turned off, the pixel signals are respectively held in the capacitors _{C 1, C 2, C 3} .

Thereafter, the horizontal scanning pulse φ _H1 from the horizontal scanning circuit 16,
phi _H2, by phi _H3, switching transistors Q _S1, Q _S2, Q
_S3 is sequentially turned on, and each of the storage capacitors C ₁ , C ₂ , C _3
Are sequentially read out to the output line 17 via the driving transistors Q _D1 , Q _D2 , Q _D3, and taken _out as the output V _out .

The above-described operations of reset, light accumulation, and signal reading are repeatedly performed. In such an imaging mode, the SIT forming a pixel using the P-MOSFET is always reset to a constant level, so that an afterimage does not occur.

On the other hand, the high-sensitivity mode described above refers to the P-
This is an imaging mode in which the SIT is reset by biasing the gate and the source of the SIT in the forward direction without causing the MOSFET to conduct, thereby causing the charge accumulated in the gate to flow out to the source.

FIG. 2B shows the pulse timing in the high-sensitivity imaging mode. The pulse timing in the high sensitivity imaging mode shown in FIG.
The differences from the pulse timing of the imaging mode shown in FIG. 7A are the SIT gate control pulses φ _VG1 , φ _VG2 , φ _VG3 , and the P-MOSFET gate control pulses φ _VP1 , φ _VP2 , φ _VP3. −MOSFET gate control pulse φ _VP1 , φ _VP2 , φ
Always the point to be set to the voltage V _P3 to turn off the P-MOSFET and _VP3. However, the pulse timings of the other pulses are the same.

Also in high-sensitivity imaging mode, focusing on the pixel of the first row, when described with respect to reading of the first row of pixel signals, the first period t ₁ ~t _2, the reset level to the gates of the first row of the SIT SIT gate control pulse _φVG1 is applied. At this time, as in the case of the imaging mode shown in FIG. 2A, the source line of each SIT is set to the vertical signal line 12-1,1.
Since the storage capacitors C ₁ , C ₂ , and C ₃ are reset at the same time as the storage capacitors C ₁ , C ₂ , and C ₃ are grounded via 2-2 and 12-3, the gate-source of the SIT of each pixel is biased in the forward direction. Each is reset. The time t ₂ SIT gating pulse phi _VG1 in, transfer pulse phi _T, a reset pulse phi _R1
Become “L”, respectively, the pixels 11-1, 11-12, 1 in the first row
1-13 starts light accumulation.

Thereafter, similarly to the imaging mode causing no residual image described above, in the period t ₃ ~t ₄ is performed transferring the readout of the pixel signal, subsequently, a horizontal scanning pulse phi _H1, phi _H2, output by phi _H3 V _out Is taken out.

At this time, when the vertical signal lines 12-1, 12-2, and 12-3 are not precharged, the forward bias between the gate and the source of the SIT can be increased. it is desirable that the _PR of the potential V _PR [0].

In the example of the pulse timing of the imaging mode shown in FIG. 2B, the gate control pulses φ _VP1 , φ _VP2 , φ _VP3 for the P-MOSFET are set to the voltage V _P3 for always turning off the P-MOSFET. However, this is because it is assumed that the high sensitivity imaging mode is used in the low illuminance region. Therefore, when there is no such assumption, the voltages of the gate control pulses φ _VP1 , φ _VP2 , φ _VP3 are set to V so that the overflow operation is performed.
Can be set to _R2 .

As described above, the operation in each imaging mode based on the pulse timings shown in FIGS. 2A and 2B for the imaging mode in which no afterimage occurs and the high-sensitivity imaging mode,
Switching between these imaging modes can be performed by changing only the SIT gate control pulse and the P-MOSFET gate control pulse. Also, in the case of the imaging mode in which afterimages do not occur, the SIT gate control pulse is set in the same manner as in the high sensitivity imaging mode, and after the forward bias between the gate and the source of the pixel SIT, resetting is performed by the P-MOSFET. The switching of the imaging mode can be performed by changing only the P-MOSFET gate control pulse. Further, the gate control pulses φ _VP1 , φ
_The saturation level, overflow operation level, and reset level can be controlled by the surface potential under the gate electrode of the P-MOSFET by the voltages of _VP2 and _φVP3 .

FIG. 3 shows the photoelectric conversion characteristics when the solid-state imaging device shown in FIG. 1 is driven at the pulse timings shown in FIGS. 2 (a) and 2 (b). However,
In FIG. 3, the horizontal axis represents the amount of light (log scale) and the vertical axis represents the output voltage (log scale).
The image pickup mode without the afterimage according to FIG.
The photoelectric conversion characteristic in the high sensitivity imaging mode according to FIG.

As shown in FIG. 3, in the high-sensitivity imaging mode, higher sensitivity can be obtained than in the imaging mode without afterimage in which the SIT is reset using the P-MOSFET.

By the way, in the case of the above-described high-sensitivity imaging mode, the reset potential of the gate electrode depends on the gate potential before the reset, that is, the exposure amount. The gate potential depending on the amount of exposure is determined by the operation of a diode formed between the gate and the source due to the forward bias between the gate and the source and the gate potential at the time of discharging charges (holes) accumulated in the gate electrode. This is caused by changing points. For this reason, there is a problem that when the change in the subject brightness is fast, if the gate / reset level cannot follow the change in the subject brightness, an afterimage appears.

However, on the other hand, a change in the light amount of the gate / reset level appears as an output change as it is, so that the sensitivity can be apparently improved. This will be described in more detail with reference to FIG.

The Fig. 4 and the number of holes N _AC accumulated in the gate electrode of the SIT before resetting operation, shows the relationship between the gate potential [Delta] V _GRS in reset immediately before the end. In the figure, characteristic curves a, b, and c respectively represent the vertical signal line precharge voltage _VPR .
The graph shows the characteristics when 1.0 V, 0.5 V, and 0.25 V are set.
As shown in these characteristics, when the number of holes N _AC accumulated in the gate electrode of the SIT is small, i.e., when the exposure amount is small, the reset level of the gate electrode is reduced. Incidentally, since the output change with respect to the light intensity of the solid-state imaging device is based on the dark level, the decrease in the potential of the gate / reset level directly changes the output of the solid-state imaging device, which means that the effective sensitivity is improved. means.

[Problems to be Solved by the Invention] The high-sensitivity imaging mode described above has an afterimage, but its apparent sensitivity is improved as compared with the imaging mode in which no afterimage occurs. Therefore, it is extremely effective when capturing an image of a low-illuminance subject that does not move.

However, the following problem arises when long-time photocharge integration is performed using only the high-sensitivity imaging mode at the time of imaging with extremely low illuminance to improve the sensitivity.

That is, as shown in FIG. 5, the pulse timing when performing long-time integration in the high-sensitivity mode is as follows.
This is performed by extending the time “time” from reset of T to reading.

In this case, the photoelectrically-converted signal charges separately, thermally generated charges accumulated number of charges before the gate reset due to (dark charge) (number of holes) N _AC increases. Then, as shown in FIG. 4, an action in the direction in which the gate reset potential becomes constant occurs, and the characteristics approach those in the case of using the imaging mode in which no afterimage occurs, so that desired high sensitivity cannot be obtained.
That is, as shown in FIG. 6, in contrast to the photoelectric conversion characteristics of the imaging mode in which no afterimage occurs, in the imaging mode in which no afterimage occurs, for example, if the integration time is extended by 10 times, the dark charge Although accompanied by an increase in noise level due to accumulation, an output value basically 10 times is obtained.

On the other hand, in the high sensitivity mode, if the SIT gate reset level is [T _int = T ₀ ] and [T _int = 10
* T ₀ ], the same as [T _int = 10 *
In the case of T ₀ ], as shown by the characteristic b ′, the photocharge amount becomes ten times, and a ten times output is obtained.

However, in practice, the SIT gate reset level is [T
The case of [ _int = T ₀ ] and the case of [T _int = 10 * T ₀ ] are different due to accumulation of dark charges and photo charges. Therefore, for the above-mentioned reason, the characteristic becomes as shown by b ″, and the sensitivity corresponding to the extension of the integration time cannot be obtained.

The present invention has been made in view of such circumstances,
The purpose is to solve the above-mentioned problem in the case where a low-illuminance still subject is integrated for a long time and image it, and to obtain solid-state imaging that can obtain sensitivity according to extension of integration time in a high-sensitivity imaging mode. An object of the present invention is to provide a method for driving the device.

[Means for Solving the Problem and Action Thereof] The driving method of the solid-state imaging device according to the present invention includes adding a new operation for discharging the charge accumulated by long-time integration from the accumulation region of the pixel. Before the reset operation of the SIT described above, the number of stored charges (the number of holes) N _AC stored in the SIT gate is reduced, and a change in the gate potential ΔV _GRS immediately before the end of reset with respect to the number of stored charges N _AC ( After setting the state of the SIT gate in the (high-sensitivity region), integration is started for a long time.

Embodiment Hereinafter, an embodiment of a method for driving a solid-state imaging device according to the present invention will be described with reference to the drawings.

FIG. 7 is a diagram showing the drive pulse timing of the solid-state imaging device showing the method of the first embodiment. This method is a method in which a reset operation in a high sensitivity mode is repeated a plurality of times before starting long-time integration.

That is, prior to the start of one long-time integration, as shown in FIG. 7, a plurality of reset cycles, that is, a reset operation in a high-sensitivity imaging mode, that is, a P-MOSF
ET gate control pulses φ _VP1 , φ _VP2 , φ _VP3 are always P-MOSFE
In the set conditions of the voltage V _P3 turning off the T, by applying a SIT gate control pulse phi _VG1 of the reset level to the gates of the SIT, and the bias between the SIT gate-source forward,
The operation of resetting each SIT is repeated a plurality of times, sufficiently small SIT gate stored charge (number positive hole) N _AC before its final reset operation, provided that the number of accumulated charge to sufficiently reduce in this way (number of holes) N _AC is not needed to be a constant for all SIT, it may be made of a value corresponding to the illuminance.

Such multiple reset operation by executing prior to the start of the long integration, the accumulated charge number of SIT gate (number positive hole) N _AC sufficiently small, the sensitivity corresponding to the extension of the optical integration time Can be obtained. In addition, the conventional problem can be effectively solved only by changing the driving method such that the reset operation is repeated a plurality of times before the start of the long-time integration.

In the present invention, a long reset period may be provided prior to the start of long-time integration, as shown in FIG.

That is, the SIT gate control pulse φ _VGi and the reset pulse φ
_R is turned on for a long time. If the ON time of these pulses is, for example, the total time of the reset time repeated in the previous embodiment, as in the previous embodiment, the number of accumulated charges in the SIT gate before the start of long-time integration the (number of holes) N _AC can be sufficiently small, the same effect as the previous embodiment are obtained if.

Further, the present invention can be implemented as follows.
That is, as shown in the example of the drive pulse timing in FIG. 9, a signal reading operation from the SIT may be added during a plurality of reset operations.

If such a read operation is added, it is possible to monitor the state of the SIT at the time of a plurality of resets, so that it is possible to accurately determine whether or not the reset is sufficient.

Further, as shown in FIG. 10 showing an example of the drive pulse timing, a reset operation is performed in an imaging mode in which no afterimage occurs. That is, the transfer pulse φ _T , the reset pulse φ _R1 , and the vertical signal line reset pulse φ _R are set to “H”, whereby the transfer transistors Q _T1 , Q _T2 , Q _T3 , and the reset transistors _{QR 1} , QR ₂ , _{QR 3} , the vertical signal line reset transistor Q _SRS1, Q _SRS2, Q _SRS3 the made conductive respectively resets the storage capacitor _{C 1, C 2, C 3} , followed by P-MOSF
The ET gate control pulse φ _{VP1 is set} to the voltage V _P1 and the P
-Turn on the MOSFET. And the gate potential of each SIT
Clamped by the drain voltage V _PD of P-MOSFET, thereby resetting the gate potential. After such a reset operation is performed once, the reset operation described above may be appropriately performed.

With this configuration, since the reset operation for the imaging mode that does not cause an afterimage is performed once, the gate reset level does not depend on the exposure state before the start of integration. As a result, even when the object to be imaged changes, it is possible to perform high-sensitivity imaging for a long time without being affected by the afterimage.

As described above, according to the present invention, only control of the timing of the reset pulse for the solid-state imaging device enables a drive capable of sufficiently coping with a high-sensitivity imaging mode by long-time integration. Is played.

Note that the present invention is not limited to the above-described embodiment. For example, in the above description, a solid-state imaging device including a light receiving unit in which pixels are arranged in a matrix is described. However, the present invention can also be applied to a line sensor in which a plurality of pixels are arranged in a line, and a similar effect is obtained. can get.

Further, in the above configuration example, the pixel is a SIT having a P-MOSFET.
However, the present invention can also be applied to a solid-state imaging device including pixels formed by using a bipolar transistor or a junction field-effect transistor instead of the SIT. In addition, the present invention can be variously modified and implemented without departing from the gist thereof.

[Effects of the Invention] As described above, according to the present invention, in the case where a low-illuminance still subject is integrated for a long time and an image is taken, a new operation of discharging the charge accumulated by the long-time integration from the accumulation region of the pixel. That is, since the reset operation is added before the start of integration to drive the solid-state imaging device, a great effect in practical use is obtained, such as the sensitivity according to the extension of the integration time in the high sensitivity mode can be easily obtained.

[Brief description of the drawings]

1 is a diagram showing a configuration example of a solid-state imaging device, FIG. 2 is a diagram showing a drive clock timing for the solid-state imaging device, FIG. 3 is a diagram showing photoelectric conversion characteristics in the solid-state imaging device, and FIG. diagram showing the relationship between the number of holes N _AC and reset immediately before the end definitive gate potential [Delta] V _GRS before, fifth
FIG. 6 is a diagram showing pulse timing when performing long-time integration in the high-sensitivity mode. FIG. 6 is a diagram showing the relationship between illuminance and output during long-time integration. FIGS. FIG. 4 is a pulse timing chart showing a driving method of the solid-state imaging device. 11-11,11-12, ~ 11-33 ... Pixel (SIT, P-MOSFET), 1
6 …… horizontal scanning circuit, 18.19 …… vertical scanning circuit, φ _VG1 , φ
_VG2, φ _VG3 ...... SIT gating pulse, φ _{T ......} transfer pulse, φ _R1 ...... reset pulse, φ _{R ......} vertical signal line reset _{pulse, φ H1, φ H2, φ} H3 ...... horizontal scanning pulse.

Claims (5)

(57) [Claims] In a solid-state imaging device in which a junction-type photoelectric conversion transistor having a photoelectric conversion function is used as a pixel and an imaging unit is formed by arranging a plurality of pixels, a light integration operation by the junction-type photoelectric conversion transistor is started. A method for driving a solid-state imaging device, characterized in that a bias between a gate electrode and a source electrode of the junction type photoelectric conversion transistor is biased in a forward direction to reset charges accumulated in the gate electrode. 2. The solid-state imaging device according to claim 1, wherein the reset operation of the charge by the forward bias between the gate electrode and the source electrode of the junction type photoelectric conversion transistor is repeatedly performed a plurality of times. A method for driving an imaging device. 3. The method according to claim 1, wherein the reset operation of the charge by the forward bias between the gate electrode and the source electrode of the junction type photoelectric conversion transistor is performed over a predetermined reset period. The driving method of the solid-state imaging device according to the above. 4. When the reset operation by forward bias between the gate electrode and the source electrode of the junction type photoelectric conversion transistor is performed a plurality of times, the charge from the junction type photoelectric conversion transistor is reset during the reset operation. The driving method of a solid-state imaging device according to claim 2, wherein a read operation is performed. 5. A control transistor connected to a gate electrode of the junction type photoelectric conversion transistor is turned on prior to a forward bias between the gate electrode and the source electrode of the junction type photoelectric conversion transistor to perform a reset operation. The overflow control operation for the junction type photoelectric conversion transistor is performed to fix a potential of a gate electrode of the junction type photoelectric conversion transistor.
4. The method for driving a solid-state imaging device according to claim 1.