JPH0226433A - Data communication equipment - Google Patents

Abstract

PURPOSE:To prevent double receiving by comparing the sequence number of a received signal block addressed to a self-equipment with a stored sequence number and anulling the signal block where the coincidence of the two sequence numbers is detected. CONSTITUTION:A transmission signal is divided into suitable signal blocks by a control part 6, a series of sequence numbers are given to the signal blocks and the latest sequence number of the signal block is stored on a reception side. When the signal block is received, it is checked whether or not the sequence number of the signal block is the same as the sequence number of the signal block received previously, when they are the same, the signal block received twice and stored in a buffer memory is cleared and is not transferred to a memory 10. Thus, double receiving can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a data communication device, and particularly to a device capable of preventing double reception.

"Conventional technology" A conventional data communication device (hereinafter referred to as a processor) is
This will be explained with reference to FIGS. 8 to 8. Common bus la, lb
A plurality of processors P+, Pz, . . . are connected to. Each processor is always in reception mode, with the signal receiving section 2 being connected to the common bus 1a through contacts a and c of the switch 3, and the signal transmitting section 4 being connected to the common bus 1b through contacts a and c of the switch 5. . These signal receiving section 2 and signal transmitting section 4 are controlled by a control section 6 that controls each functional block. Now, when one processor tries to transmit data to another processor, the control section 6 of the transmission source processor checks whether the signal receiving section 2 is receiving data or not. After confirming that there is no data on the bus la, that is, that the common bus la is free (step 1 in Figure 7), switch 3.5.
is controlled to disconnect each movable contact C to the b side, and as shown by the dotted line in the processor P1, the signal transmitter 4
is connected to the common bus 1a, and the signal receiving section 2 is connected to the common bus 1b, and the reception mode is switched to the transmission mode (step 2).
), the control unit 6 divides the transmission data into signal blocks (also called data blocks) of an appropriate length, and in the signal block format shown in FIG. Set the signal block S to be transmitted next in the order of the number of bytes and data (step 3), send it from the signal transmitter 4 (step 4),
This signal block S is received by the signal receiving units 2 of all other processors and once written into the buffer memory 8 (step 5).The control unit 6 checks its destination (step 6), and if it is not addressed to its own device. The buffer memory 8 is cleared (step 7), and if the data is for the own device, the data in the buffer memory 8 is transferred to the memory 10 via the gate circuit 9 as necessary (step 8).

When the writing of data to the memory 10 is completed, the control unit 6 causes the signal transmitting unit 4 to send a response signal R to the signal transmitting source to indicate that the next signal program 7R S can be received (step 9 ).

The control unit 6 at the transmission source checks whether the response signal R is received within a predetermined time after transmitting the signal (step 10).
), if the response signal R is lost on the way and does not arrive within a predetermined time, the process returns to step 4 and the previous signal block S is retransmitted. Further, if a response signal is received within a predetermined time, the process returns to step 3 to set the next signal block, and the same operations as described above are repeated to perform transmission and reception of all the divided signal blocks. Note that a computer is normally used as the control unit 6.

[Problem to be Solved by the Invention] A signal block retransmitted due to loss of a response signal is received at the destination and stored in the buffer memory 8. At the destination, the destination is checked, but the contents of the data are not checked. Therefore, even though the data has already been stored in the memory 10, the data in the buffer memory 8 is transferred to the memory 10, and the same data is stored in the memory 10 again. Stored.

Therefore, a time loss such as the time required for transfer occurs, and the storage area of the memory 10 is occupied in excess, which is wasteful. The purpose of this invention is to eliminate such inconveniences.

"Means for solving the problem" Connected to a common bus, there is a signal transmitter, a signal receiver, a buffer memory that temporarily stores the signals received by the signal receiver, and data transferred from the buffer memory. It is equipped with a memory that stores the information, and a control unit that controls each of the above parts, and divides the transmission signal into blocks of appropriate length and transmits them.When it receives a signal block addressed to itself, it transmits a response signal, and sends the signal to the destination. According to the present invention, in a data communication device that receives a response signal from a destination and transmits the next signal block, and retransmits the previous signal block when a response signal is not received from the destination, the present invention provides a method for dividing the transmitted signal. The controller is provided with means for assigning a sequence number to the received signal block, a sequence number storage means for storing the latest sequence number of the received signal block addressed to the own device, and a sequence number storage means for storing the latest sequence number of the received signal block addressed to the own device. The data communication device is provided with a comparison means for comparing the sequence number of the block with the sequence number stored in the sequence number storage means and detecting a match between the two sequence numbers, and the comparison means detects a match between the sequence numbers. The control section is provided with means for discarding the signal block in which the signal block is detected.

Embodiment In order to prevent the same data block from being stored twice in the memory 10 by the processor on the receiving side, the present invention manages the number of signal blocks. That is, in the present invention, as shown in FIG. 2, a series of sequence numbers are assigned in advance of data as a signal format.

An embodiment of the present invention is shown in FIG. 1, and parts corresponding to those in FIG. 6 are denoted by the same reference numerals, and some redundant explanations will be omitted. The operation of FIG. 1 will be explained with reference to the operation flowchart of FIG. 3. At the source, the control unit 6 checks whether the common bus is free (step 1), and if it is free, the mode is switched from the reception mode to the transmission mode (step 2).

The control unit 6 sets the signal block to be transmitted next, and at this time a new sequence number l is assigned to the data block (step 3).The sequence number l is, for example, 0, which increases by 1 starting from i-1. Next, the signal block St is transmitted (step 4), received by the destination signal receiving section 2, and stored in the buffer memory 8 (step 5). It is checked whether it is the number of the device (step 6). As a result, if the number is not the number of the device itself, the signal block Si stored in the buffer memory 8 is cleared (step 7). For example, the comparator 12 compares whether the sequence number of the signal block Si matches the sequence number of the previously received signal block stored in the sequence number storage means 11 (step 8). For example, the control unit 6
The signal block St of the buffer memory 8 is cleared by the control of the buffer memory 8 (step 7), and if different, the signal block St is cleared from the buffer memory 8 through the gate circuit 9 as necessary.
The data etc. of the signal block SI are transferred to the signal block SI (step 9), and the sequence number stored in the sequence number storage means 11 under the control of the control unit 6 is transferred to the signal block SI.
is updated to the sequence number i (step 10).

When the above step 10 is completed, or when the signal St has the same sequence number as before in the above step 8, the transmitter 4 sends a response signal R indicating that the next signal block can be received. (Step 11
).

The control unit 6 at the transmission source checks whether the response signal R has been received within a predetermined time after sending the signal block 31 (step 12), and if it has been received, it is checked in step 3.
Returning to step 4, the next signal block to be transmitted is given a new sequence number, while if no response is received, returning to step 4, the signal block Si is transmitted again, and the same operations as before are repeated. .

In Fig. 1, the carriers of the transmitted and received signals at each terminal are selected at different frequencies f, , f, and in the normal reception mode, frequency f1 is used for reception and f2 is used for transmission, and only the transmitter's frequency Invert the
When setting to the transmission mode, that is, when inverting fl to transmit and f to receive, switch 3 is turned on as shown in Fig. 4.
．． 5 can be omitted and the number of common buses can be reduced to one. In FIG. 4, only processor P+ is in transmit mode, and the others are in receive mode.

Further, if the processors P in FIG. 1 perform only half-duplex communication with each other and there is no need to perform full-duplex communication, only the switch 3 and the common bus 1a are used, and the switch 5 and The common bus lb can be omitted. Also in FIG. 5, only the processor P is in the transmitting mode and the others are in the receiving mode.

Each processor switches the movable contact C to the b side only when transmitting a signal block or response, and communicates with the transmitter 4 through the common bus 1a.
In other cases, the movable contact C is connected to the a side, and only the signal receiving section 2 is connected to the common bus 1a.

"Effects of the Invention" According to the present invention, a transmission signal is divided into appropriate signal blocks, a series of sequence numbers are assigned to each signal block, the latest sequence number of the signal block is stored on the receiving side, and the signal block is Upon reception, it is checked whether the sequence number of the signal block is the same as the sequence number of the previously received signal block;
If they are the same, the duplicate received signal block stored in the panzer memory will be cleared and will not be transferred to memo January 0. Therefore, according to the present invention, double reception, which has been a problem in the past, can be completely prevented.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data communication device showing an embodiment of this invention, FIG. 2 is a diagram showing the format of a signal block of a transmission signal used in this invention, and FIG. 3 is a block diagram of a data communication device according to an embodiment of the invention. The operation flowchart, FIG. 4 and FIG. 5 are block diagrams showing main parts of a modified embodiment of the present invention, and FIG.
The figure is a block diagram of a conventional data communication device, and Figure 7 is a block diagram of a conventional data communication device.
FIG. 8 is an operation flowchart of the data communication device shown in FIG. 8, and FIG. 8 is a diagram showing the format of a signal block of a conventional transmission signal.

Claims (1)

[Claims] (1) A signal transmitter, a signal receiver, a buffer memory that temporarily stores signals received by the signal receiver, and a memory that stores data transferred from the buffer memory, which are connected to a common bus; It is equipped with a control section that controls each of the above sections, divides the transmission signal into signal blocks of appropriate length and transmits them, transmits a response signal when it receives a signal block addressed to itself, and receives a response signal from the destination. In a data communication device that receives a signal block, transmits the next signal block, and retransmits the previous signal block when a response signal from the destination is not received, the signal block is provided in the control unit and is a signal block obtained by dividing the transmission signal. means for assigning a sequence number to the received signal block addressed to the own device; sequence number storage means for storing the latest sequence number of the received signal block addressed to the own device; and sequence number storage means for storing the sequence number and the sequence number of the received signal block addressed to the own device. Comparing means for comparing a sequence number stored in the means and detecting a match between both sequence numbers; and means provided in the control section for discarding a signal block whose sequence numbers have been detected to match by the comparing means. A data communication device comprising: