JPH02262792A - Television system converter - Google Patents

Abstract

PURPOSE:To monitor almost whole screen of high vision video with a correct aspect ratio without modifying the vertical deflecting circuit of an NTSC monitor by converting the aspect ratio conversion to the scanning line conversion with a vertical filter and compressing a signal on the time base in the vertical direction. CONSTITUTION:In a scanning line conversion filter circuit 19, the signal of 525 scanning lines/60Hz inputted to an input terminal 11 is inputted to first and second vertical filter circuits 23 and 24. Respective filters have transfer characteristics shown by formulas I and convert the number of scanning lines from 3 to 2. A selector circuit 25 selects the output (a1 to a4) of the first vertical filter circuit 23 and the output (b1 to b4) of the second vertical filter circuit in the period of a first field and the period of a second field respectively and outputs the selected output to an output terminal 18. This signal has 350 scanning lines/60Hz and is compressed on the time base in the vertical direction by a speed conversion memory circuit 20, and the blanking period of 175 scanning lines is added by a blanking inserting circuit 21 to output the signal of 525 scanning lines/60Hz (350 effective scanning lines).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal processing circuit, and particularly to a digital filter that converts the aspect ratio of a television signal.

[Conventional technology]

FIG. 2 is a diagram showing a television receiver according to the applicant's prior art, in which (1) is a first input terminal, (2) is an A/D converter, and (3) is a de-emphasis circuit. , (4) is the first PLL circuit, and (5) is the second PLL circuit.
LL circuit, (6) is a scanning line conversion circuit, (7) is a luminance signal processing circuit, (8) is a color difference signal processing circuit, (9) is a D/A
converter, Qo is a switch circuit, (b) is an inverse matrix circuit, @ is a CRT, ni) is a second input terminal, (b) is a third input terminal, αQ is an NTSC decoder, QCS is a timing generation circuit, αη is a vertical deflection circuit, and (to) is a horizontal deflection circuit.

Next, the operation will be explained. Input terminal (1) has MUS
A high-definition signal whose band has been compressed by the E method is applied. The above high-definition signal has 1125 scanning lines,
Field frequency 60H2, 2: 1 interlaced signal. In the MUJE system, the high-definition signal is compressed to a band of 8 MH2 and transmitted in one channel using a broadcasting satellite. This compression is performed by an offset sub-suspension, using inter-field and inter-frame offsets for still parts and line-picture offsets for moving parts. Also, two color difference signals (R-Y, B-Y)
is time compression multiplexed during the blanking period of the luminance signal.

The high-definition signal by the MUSE method (hereinafter referred to as MUSE signal) applied to the input terminal ([) is A /
It is converted into a digital signal by the D converter (2), and then sent to the de-emphasis circuit (3) and the first PLL circuit (display).
are applied to each. The first PLL circuit (4) reproduces a correct sampling clock based on the phase information in the MUSE signal. This correct sampling clock is supplied to the L A/D converter (2), and the MUSID signal sampled at the correct phase is applied to the de-emphasis circuit (3). The de-emphasis circuit (3) corrects the frequency characteristics of the MUSE signal, and this corrected signal is sent to the scanning line conversion circuit (6).
is applied to The scanning line conversion circuit (6) converts 75 out of 1125 scanning lines per frame of the MUSE signal.
By discarding the scanning lines of a book and converting to 1050 scanning lines per frame, for example, using memory, the speed of the write clock is set to the speed obtained from the time axis of the MUSE signal, and the speed of the read clock is set to the speed obtained from the time axis of the NTSC signal. It is configured to achieve the speed that can be obtained. This read clock is output from the second PLL circuit (5).

Therefore, a signal having 1050 scanning lines per frame, 2:1 interlacing, and a field frequency of 60 Hz is obtained from this scanning line conversion circuit (6).

The output signal of the scanning line conversion circuit (6) is applied to each of the luminance signal processing circuit (7) and the color difference signal processing circuit (8). Interpolation is performed to restore the band, and interlace conversion is then performed to obtain a signal with 525 lines per frame, 2:1 interlace, and a field frequency of 60H2. On the other hand, the color difference signal processing circuit (8) processes two time compression multiplexed color difference signals (
RY, B-Y)' 4 hours and performs intra-field interpolation processing to restore the band to its original value. Thereafter, interlace conversion is performed to convert into 525 interlace signals per frame. The above luminance signal processing circuit (7)
The luminance signal and the two color difference signals (R-Y, B-Y) which are the output signals of the color difference signal processing circuit (8) are D/
The signal is applied to the A converter (9) and converted into an analog signal.

On the other hand, the NTSC signal applied to the third input terminal α is guided to the NTSC decoder (g). The NTSC decoder (to) is composed of, for example, means for separating a luminance signal and a color signal, and means for demodulating the color signal.
A luminance signal and two color difference signals are output from the signal. The output signal of the D/A converter (9) and the output of the NTSC decoder (g) are applied to a switch circuit α0. The switch circuit αQ is configured to output one of two signals applied to the switch circuit αQ depending on a signal applied to a second input terminal (to) described later. The output signal of the switch circuit αQ is input to an inverse matrix circuit (b), and primary color signals of R, G, and B are generated. The above inverse matrix circuit (b) is similar to that implemented in current television receivers. The output signals R, G, and B of the above inverse matrix circuit (b) are C
The deflection timing of CRTO, ) applied to RT(2) and displayed is generated by the timing generation circuit aQ, and the vertical deflection circuit α and the horizontal deflection circuit (to) are generated by the signal from the timing generation circuit a. Driven. The vertical deflection circuit αη is configured so that its deflection width can be controlled by a signal applied to a second input terminal (to be described).

A control signal for selecting whether to display the NUSK signal or the NTSC signal on the television screen is applied to the second cutting terminal (to). As mentioned above, this signal is applied to the switch circuit Ql and the vertical deflection circuit α. The switch circuit QO passes the output signal of the D/A converter (9) or the output signal of the NTSC decoder 06 according to the control signal of the second input terminal (to). In addition, when the switch circuit αO selects the output signal of the NTSC decoder (16), the vertical deflection circuit α is driven with the normal NTSC vertical deflection width. The output signal of 9) is
Figure 3 (b) with an aspect ratio of 4:3 is obtained by time-compressing an image with an aspect ratio of 16:9 as shown in Figure 3 (,) in the horizontal direction.
It is a vertically long image like this. Therefore, when the switch circuit α0 selects the output of the D/A converter (9), the power of the vertical deflection circuit α is such that the vertically elongated image as shown in FIG. c) Aspect ratio like 16:
The vertical deflection width is reduced so that the image becomes 9.

[Problem to be solved by the invention]

Conventional television format converters are configured as described above, so in order to display almost full-screen high-definition video on an NTSC monitor, the vertical deflection circuit of the NTSC monitor must be modified so that it can be controlled externally. For this reason, the NTSC monitors already on the market have the drawback of not being able to display almost full-screen high-definition images.

This invention was made to solve the above problems, and provides a television format converter that can display almost full-screen high-definition images on an NTSC monitor without modifying the vertical deflection circuit of the NTSC monitor. The purpose is to

[Means to solve the problem]

The television format converter according to the present invention includes means for converting scanning lines from 525 to 350, means for vertically time-compressing the converted signal, and blanking for the time-compressed signal. Add a period and increase the number of scanning lines to 525
It is equipped with the means to turn it into a book.

[Effect]

The television format converter of this invention converts the scanning lines from 525 to 350, compresses the time in the vertical direction, and adds a blanking period, thereby converting the aspect ratio correctly and displaying high-definition images on an NTSC monitor. Display almost the entire screen.

C Embodiment of the Invention] Hereinafter, an embodiment of the invention will be described with reference to the drawings. 1st
In the figure, the same symbols as in FIG. 2 indicate the same things. Q
9 is a luminance signal (Y signal) and a color difference signal (R-Y, B-Y) output from a luminance processing circuit (7) and a color difference processing circuit (8).
A scanning line conversion filter circuit that converts the scanning line of (signal), (
A) is a speed conversion memory circuit, and B) is a blanking insertion circuit. Moreover, FIG. 4 shows the scanning line conversion filter circuit of FIG. 1 (6), (A) is an input terminal, (2) is a first vertical filter circuit, (C) is a second vertical filter circuit,
) is a selector circuit that selects the output of the first vertical filter circuit (to) and the second vertical filter circuit (to); (e)
is an input terminal, ) is a field determination circuit, and (to) is an output terminal.

The MUSE signal input to the input terminal ([) is quantized by the A/D converter (2), and then sent to the first PLL circuit (4).
The clock is regenerated by On the other hand, the frequency characteristics of the quantized signal are corrected by a de-emphasis circuit (3). The corrected signal is input to the scanning line conversion circuit (6), and 1050 of the 112 scanning lines are written into memory and read out at a slower speed than writing, resulting in 1050 lines per frame, 2:1 interlace, It is converted into a signal with a field frequency of 60H2. The above conversion output is processed in two systems: luminance and two color differences. The luminance signal (Y) is subjected to intra-field interpolation processing and scanning line conversion from 1050 lines to 525 lines in a luminance signal processing circuit (7). On the other hand, the color difference signal (R-
Y, B-Y) are time-axis compressed and multiplexed during the horizontal blanking period of the luminance signal, so they are time-axis expanded (TCI decoder) in the color difference signal processing circuit (8), and further subjected to intra-field interpolation processing and 1050 lines. The scanning lines are converted from 1 to 525. Two color difference signals R-Y, B from the color difference processing circuit (8)
-Y signal is output.

The above luminance signal processing circuit (7) and color difference signal processing circuit (8)
) output signal (Y, R-Y, B-Y) is 52
It is a 2:1 interlaced signal with 5 lines/frame field station wave number 60H2. The above signal (Y, R-Y, B-Y
) is a vertically elongated image as shown in FIG. 3(b). The above signal is input to the scanning line conversion filter circuit H. The operation of the scanning line conversion filter circuit Ql will be explained using FIGS. 4 and 5.

The 525 lines/60H2 signal input to the input terminal - is
It is input to the I-th vertical filter circuit (to) and the second vertical filter circuit). The first vertical filter circuit (to) is composed of a fourth-order digital filter, and its tap coefficient is 1/
16.1/4.3/8.1/4.1/16, and the transfer characteristic is
h+z-4h)/16Z-h: Represented by one horizontal scan line delay. The second vertical filter circuit (goods) is composed of a fifth-order digital filter, and its tap coefficient is 1/32.
．． 5/32. s/ 16.5/16. s/32.1
/32.

The transfer characteristic is: )T(Z)=(1+5Z+10Z-"+10Z-3h
+5Z-4h+Z-") /32Z→:1 horizontal scanning line delay. The signals m and b output from the first vertical filter circuit slope and the second vertical filter circuit (c) are output from the selector circuit (i). ).The selector circuit (C) selects the false signal during the first field period and the b signal during the second field period according to the signal output from the field judgment circuit G, and sends it to the output terminal (To). The above operation will be explained with reference to Fig. 5. In Fig. 5, the ○ marks are the scanning lines of the first field of the signal input to the input terminal (sha), the marks are the scanning lines of the second field, and the 0 marks are the scanning lines of the second field. The mark indicates the scanning line of the first field of the signal output to the output terminal), and the symbol ■ indicates the scanning line of the second field. Symbols A1 to A7 indicate the scanning line of the first field of the input signal, and Bl to B7 indicate the scanning line of the first field of the input signal. The scanning line number of the second field, a1 to a4 are the scanning lines of the first field of the output signal, b
1 to b4 indicate scanning lines of the second field.

The first field (Al to A7) and the second field (B1 to B7) of the input signal are in an interlaced relationship. The first vertical filter circuit (to) is connected to the input signal scanning line (A
1 to A7) to the scanning line of the output signal (ml [0). At this time, the scanning lines are converted from 3 to 2, and the phase is as follows: al is the middle between A1 and A2. becomes,B
2 is in phase with A3, B3 is between A4 and A5, and B
4 is in the same phase as A6. 2nd vertical filter circuit (goods)
performs scanning line conversion from input signal scanning lines (Bl to B7) to output signal scanning lines (bl to b4), and at this time, the number of scanning lines is converted from three to two. Its phase is bl is B
1 and B2 have a 3=1 phase, B2 has a 1:3 phase of B3 and B4, B3 has a 3:1 phase of B4 and B5, and B4 has a 1:3 phase of B6 and B7.

selector circuit) is the output of the first vertical filter circuit (to) during the first field (a4 to ml), and the output of the second vertical filter circuit (bl to b4) during the second field.
is selected and output to the output terminal (7). The output signal is such that bl is placed at the center of al and 82, B2 is placed at the center of B2 and B3, and the first field (a I
~a4) and the second field (bl~b4) are in an interlaced relationship. The signal output to the output terminal) is a signal of 350 lines/60 Hz.

The above scanning line conversion filter circuit α is added to the speed conversion memory circuit.
9 to 60Hz signal (
Y, RY, B-Y) are input. The speed conversion memory circuit (1) is composed of a memory, and by reading at a faster speed than writing, a signal compressed in time in the vertical direction as shown in FIG. 6(b) is sent to the blanking insertion circuit).
Output to. In the blanking insertion circuit (2), Figure 6 (
By adding blanking to the shaded area shown in b) for a period of 175 scanning lines, 525, 60H2 (350 effective scanning lines) signals (Y, R-Y, B-Y) are output. . The signal obtained by filtering is an image whose vertical length has been corrected, as shown in FIG. 3(C). The signal obtained as above (
Y, RY, B-Y) are converted into analog signals by a D/A converter (9) and input to switch α0. On the other hand, the NTSC signal input to input terminal α→ is NTSC
Decoder (to) Y, RY.

It is decoded into a B-Y signal and input to the switch (io).Switch α1 is the MUS input from the input terminal (to)
One of the output of the D/A converter (9) and the output of the NTSC decoder Oθ is selected by the K/NTSC selection signal and output to the inverse matrix circuit (b). Inverse matrix circuit αυ
The Y, R-Y, and B-Y signals input to the CRT (6) are converted into RqB signals and displayed on the CRT (6).

Although the above embodiment describes the case where the encoder is built into a television receiver, an NTSC encoder can be installed after the D/A converter (9) to modulate the color signal to generate an NTSC composite signal and Y/C separate signal. It may also be an adapter-type system converter that outputs a signal.

〔Effect of the invention〕

As described above, according to the present invention, aspect ratio conversion is configured to perform scanning line conversion using a vertical filter and compress time in the vertical direction. This has the effect of allowing you to monitor almost the entire screen at the correct aspect ratio.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a television system converter according to an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional television system converter, and FIG. 3 is a diagram explaining the operation of FIG. 2. 4 is a block diagram of the scanning line conversion filter circuit in FIG. 1, FIG. 5 is a diagram explaining the operation of FIG. 4, and FIG.
FIG. 2 is a diagram illustrating the operation of FIG. 1; In the figure, (1) #03. (E) is the input terminal, (2) is the A/D converter, (3) is the de-emphasis circuit, (
4), (5) are PLL circuits, (6) are scanning line conversion circuits,
(7) is a luminance signal processing circuit, (8) is a color difference signal processing circuit, (9) is a D/AK converter, 00 is a switch, (b) is an inverse matrix circuit, and @ is a CRT. (g) is an NTSC decoder, α・ is a timing generation circuit, αη is a vertical deflection circuit, (to) is a horizontal deflection circuit, (a)
is the scanning line conversion filter circuit, gradient is the speed conversion memory circuit,
(2) is a blanking insertion circuit, (2) is a vertical filter circuit, (2) is a selector circuit, (2) is a field determination circuit, and (2) is an output terminal. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (2)

[Claims] (1) means for converting 1125 scanning lines of the MUSE signal into 1050 scanning lines; means for performing intra-field interpolation processing on the converted luminance signal;
A means for converting into a 25-line interlaced signal, and a means for performing time axis expansion on the above-mentioned scanning line-converted color difference signal to generate RY and B signals.
- means for outputting a Y color difference signal; means for performing intra-field interpolation processing on the two color difference signals;
MU equipped with means for converting into 25 interlaced signals
A television format converter that converts SE signals to NTSC signals uses 525 scanning lines per frame, with 3 to 2 scanning lines per frame.
1. A television system converter comprising two digital filters having different coefficients for converting into a television format, and means for switching the two digital filters for each field. (2) The television format converter according to claim 1, wherein coefficients of two mutually different digital filters are given by the following equations. Filter 1: ▲ Contains mathematical formulas, chemical formulas, tables, etc. ▼ Filter 2: ▲ Contains mathematical formulas, chemical formulas, tables, etc. ▼ Z^-^h: 1 horizontal scanning line delay