JPH02262295A - Thin film el element - Google Patents
Thin film el elementInfo
- Publication number
- JPH02262295A JPH02262295A JP1083799A JP8379989A JPH02262295A JP H02262295 A JPH02262295 A JP H02262295A JP 1083799 A JP1083799 A JP 1083799A JP 8379989 A JP8379989 A JP 8379989A JP H02262295 A JPH02262295 A JP H02262295A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating layer
- resistance material
- composite insulating
- material layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 12
- 239000000463 material Substances 0.000 claims abstract description 39
- 239000002131 composite material Substances 0.000 claims abstract description 18
- 230000005684 electric field Effects 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 13
- 238000004544 sputter deposition Methods 0.000 abstract description 8
- 239000011810 insulating material Substances 0.000 abstract 3
- 229910002113 barium titanate Inorganic materials 0.000 abstract 2
- 239000010408 film Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 2
- 238000004020 luminiscence type Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000000474 nursing effect Effects 0.000 description 1
Landscapes
- Electroluminescent Light Sources (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、外側を高抵抗材料層内側を低抵抗材料層とす
る複合絶縁層を使用する高輝度化した薄膜EL (エ
レクトロルミネセンス)素子に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a thin film EL (electroluminescence) device with high brightness using a composite insulating layer having a high resistance material layer on the outside and a low resistance material layer on the inside. It is related to.
一般に薄膜EL素子は、基板上に表面電極、第1絶縁層
、発光層、必要に応じて第2絶縁層更に背面電極を積層
した構造を有するものであるが、従来、発光層への電流
密度と発光輝度特性を考慮して薄膜EL素子の高輝度化
を図るため発光層に接する絶縁層は低抵抗であることが
望ましく、また、一方で絶縁破壊特性を考慮して、高抵
抗の絶縁層を有することら必要であるという研究結果に
より絶縁層を発光層と接する内側を低抵抗材料層とし、
外側を高抵抗材料層とする複合絶縁層にした高輝変化し
た薄膜EL素子が開発されている。Generally, a thin film EL device has a structure in which a surface electrode, a first insulating layer, a light emitting layer, and a second insulating layer and a back electrode are laminated on a substrate. In order to increase the brightness of a thin-film EL element, taking into account the luminance characteristics and the luminance characteristics, it is desirable that the insulating layer in contact with the light emitting layer has a low resistance. According to research results that it is necessary because the insulating layer has a low-resistance material layer,
High brightness thin film EL devices have been developed that have a composite insulating layer with a high resistance material layer on the outside.
しかしながら、従来、この複合絶縁層の低抵抗材料層と
高抵抗材料層には例えば低抵抗材料層にはTatO3、
高抵抗材料層には5iftというように夫々別々の材料
により形成していた。However, conventionally, the low-resistance material layer and the high-resistance material layer of this composite insulating layer, for example,
The high resistance material layers were formed of different materials such as 5ift.
従って、第1絶縁周、第2絶縁層を形成する場合は合わ
せると計4層もいろいろ違う材料層を蒸着などにより形
成しなくてはならず、非常に製作が厄介となりそれだけ
看産性になじまないという欠点があった。Therefore, when forming the first insulating layer and the second insulating layer, a total of four layers of different materials must be formed by vapor deposition, etc., which makes the manufacturing process very complicated and makes it difficult for nursing care. There was a drawback that there was no
本発明は、この欠点を解決した薄膜EL素子を提供する
ものである。The present invention provides a thin film EL device that solves this drawback.
添付図面を参照して詳述すると次の通りである。 The details are as follows with reference to the accompanying drawings.
電界に応じて発光を呈する発光層1を表面電極4と背面
電極5間に設け、前記発光層1に対して外側を高抵抗材
料層内側を低抵抗材料層とする複合絶線層を前記発光層
1と接するように少な(とも−層設けた薄[EL素子に
おいて、前記複合絶縁層を1つの材料で形成せしめたこ
とを特徴とする薄膜EL素子に係るものである。A light-emitting layer 1 that emits light in response to an electric field is provided between a front electrode 4 and a back electrode 5, and a composite continuous wire layer having a high-resistance material layer on the outside and a low-resistance material layer on the inside of the light-emitting layer 1 is provided in the light-emitting layer 1. The present invention relates to a thin film EL device in which a small number of layers are provided in contact with layer 1, and the composite insulating layer is formed of one material.
発光層重を複合絶縁層から成る第1.第2絶律層2・3
間に配在せしめ双方の絶縁層2・3とも同一材料で高抵
抗材料層2a・3a低抵抗材料層21)・3トを形成し
た一実施例について詳述する。The first light-emitting layer consists of a composite insulating layer. Second insulating layer 2 and 3
An embodiment in which the high resistance material layers 2a, 3a and the low resistance material layers 21) and 3 are formed of the same material as the insulating layers 2 and 3 disposed between them will be described in detail.
ガラス基板6上に表面電極4としてITOを蒸着法で形
成し、希望するパターンにパターニング加工する。ITO is formed as a surface electrode 4 on a glass substrate 6 by a vapor deposition method, and patterned into a desired pattern.
その上に第1絶縁層2の高抵抗材料層2aを設けるべく
基板6の温度を室温とし、B aT io sを100
0〜2000Aの膜厚となるようにスパッタ法で形成し
、続いてその上に低抵抗材料層2bを設けるべく基板6
の温度を300℃とし、BaT i 03を3000〜
4000Aの膜厚となるようスパッタ法で形成すること
により、複合絶縁層から成る第1絶縁層2を同一材料B
aTiOsにより形成する。In order to provide the high-resistance material layer 2a of the first insulating layer 2 thereon, the temperature of the substrate 6 is set to room temperature, and the B aT ios is 100.
A substrate 6 is formed to have a film thickness of 0 to 2000A by sputtering, and then a low resistance material layer 2b is provided thereon.
The temperature of is 300℃, BaT i 03 is 3000~
The first insulating layer 2 consisting of a composite insulating layer is formed using the same material B by forming it to a thickness of 4000A by sputtering.
It is formed from aTiOs.
その上にZnS:Mnなどの発光層1をエキタキシビー
ム法(EB法)で設け、第1絶縁層2と同様に第2絶縁
層3の低抵抗材料層3bを設けるべく基板6の温度30
0℃でB aT i O3を3000〜4oooAの膜
厚となるようスパッタ法で形成し、続いてその上に高抵
抗材料層3aとして基板6の温度を150℃まで冷却し
てB aT i O3を1000〜2oooAの膜厚と
なるようスパッタ法で形成することにより、複合絶縁層
から成る第2絶縁層3を同一材料B aT f Osに
より形成する。A light emitting layer 1 made of ZnS:Mn or the like is provided thereon by an epitaxy beam method (EB method), and the temperature of the substrate 6 is set at 30°C in order to provide a low resistance material layer 3b of the second insulating layer 3 in the same manner as the first insulating layer 2.
B aT i O3 is formed at 0° C. by sputtering to a thickness of 3000 to 400 A, and then a high-resistance material layer 3a is formed on the substrate 6 by cooling the temperature of the substrate 6 to 150° C. to form B aT i O3. The second insulating layer 3, which is a composite insulating layer, is formed from the same material B aT f Os by forming the second insulating layer 3 to have a thickness of 1000 to 200 A by sputtering.
そして、この上に背面電極5としてのAQを形成する。Then, AQ as the back electrode 5 is formed on this.
尚、第2絶縁層3については無くてもよいし、材料が異
なった従来の複合絶縁層としても良い。Note that the second insulating layer 3 may be omitted, or may be a conventional composite insulating layer made of different materials.
第2図、第3図の実線アは、B aT I Osを基板
6温度25℃でスパッタリング法により1700人の膜
厚にて成膜した場合(第1絶縁層2の高抵抗材料層2a
に相当)の電圧電流特性及びこの膜を絶縁層として用い
たEL素子の電圧発光特性を示すもので、電圧印加に対
して殆ど電流が流れない高抵抗材料となっていることを
示しており、発光開始電圧も高くなっている。The solid line A in FIGS. 2 and 3 shows the case where B aT I Os is formed into a film with a thickness of 1700 nm by sputtering at a substrate temperature of 25°C (high resistance material layer 2a of first insulating layer 2).
This shows the voltage-current characteristics of the film (equivalent to 1) and the voltage-current characteristics of an EL device using this film as an insulating layer, indicating that it is a high-resistance material in which almost no current flows when voltage is applied. The light emission starting voltage is also high.
また、実線イは、B aT to 3を基板6温度15
0℃でスパッタリング法により1500人の膜厚にて成
膜した場合(第2絶祿層3の高抵抗材料層3aに相当)
の前記同様の特性を示すもので、電圧印加に対してわず
かに電流が流れる高抵抗材料となっていることを示して
おり、発光開始WEは実線アの約75%となっている。In addition, solid line A shows B aT to 3 at substrate 6 temperature 15
When a film is formed to a thickness of 1500 by sputtering at 0°C (corresponding to the high resistance material layer 3a of the second insulation layer 3)
The material exhibits the same characteristics as described above, indicating that it is a high-resistance material in which a slight current flows when a voltage is applied, and the emission start WE is approximately 75% of that of the solid line A.
そして、実線つは、B aT i Osを基板6温度3
00℃でスパッタリング法により4100Aの膜厚にて
成膜した場合(第1.第2絶縁層2・3の低抵抗材料B
21)・31)の相当)の前記同様の特性を示しており
、発光開始電圧は実線アの約50%となっている。And the solid line shows B aT i Os at substrate 6 temperature 3
When a film is formed with a thickness of 4100A by sputtering at 00°C (1. Low resistance material B of the second insulating layers 2 and 3)
21) and 31)), and the emission start voltage is about 50% of that of the solid line A.
これらは何れも単独として成膜した場合の測定値である
が、このような差は、基板61度を変えることにより、
層の結晶性が変化し、高い温度はど結晶性が良く、抵抗
率が小さくなるためによるものであり、実施例のように
連続積層にて設けても近い特性が維持されているものと
考えられる。These are all measured values when the film was formed as a single film, but such a difference can be seen by changing the substrate angle of 61 degrees.
This is because the crystallinity of the layer changes, and the higher the temperature, the better the crystallinity and the lower the resistivity.It is thought that similar characteristics are maintained even if the layer is formed by continuous lamination as in the example. It will be done.
尚、前記抵抗率の変化は、B aT io sの池に、
P bT io 、のようなへロブカイト構造材料にて
ら見受けられ、前記同様の特性が得られるものである。In addition, the change in resistivity is caused by
It is found in herobukite structure materials such as P bT io , and the same characteristics as described above can be obtained.
第4図実線Aは、前記実施例の電圧発光特性を示すもの
で、異なる材料(T at o 3と5iOy)にて複
合絶縁層を形成した従来のEL素子の電圧発光特性を示
す実線Bと比べて、はぼ同程度の特性であることが分か
った。The solid line A in FIG. 4 shows the voltage emission characteristics of the above example, and the solid line B shows the voltage emission characteristics of a conventional EL element in which a composite insulating layer was formed using different materials (T at o 3 and 5iOy). In comparison, it was found that the characteristics were almost the same.
また、この実施例である実線Aは、第3図で示した単独
にて絶縁層を形成したEL素子のうち最も良い特性であ
る実線ウ (基板6温度300℃。Further, the solid line A representing this example is the solid line C representing the best characteristics among the EL elements shown in FIG. 3 in which an insulating layer is formed alone (substrate 6 temperature: 300°C).
膜厚4100人)と比べて、発光開始電圧はほぼ同じで
ありながら発光輝度が約1.5倍であることが分かった
。It was found that the luminescence brightness was approximately 1.5 times higher than that of the film with a film thickness of 4,100 mm, although the luminescence starting voltage was almost the same.
本発明は上述のように構成したから同一材料で高抵抗材
料層と低抵抗材料層からなる複合絶縁層を形成すること
ができるから非常に作製が簡単となりそれだけ短時間に
作製でき量産性に秀れた高輝度化された薄膜EL素子を
提供できることとなる。Since the present invention is configured as described above, it is possible to form a composite insulating layer consisting of a high-resistance material layer and a low-resistance material layer using the same material, which makes it extremely easy to manufacture, and can be manufactured in a short time, making it excellent in mass production. Therefore, it is possible to provide a thin film EL element with high brightness.
図面は本発明の一実施例を示すもので、第1図はその構
造図、第2図はI3 aT io 3の単独絶線層を成
膜した場合の電圧電流特性図、第3図は第2図の絶縁層
を用いたEL素子の電圧発光特性図、第4図は絶縁層を
複合絶縁層として従来例と同上実施例の電圧発光特性図
である。
1・・・発光層、4・・・表面電極、5・・・背面電極
。
77個
プZ肩
79別
フ<−1The drawings show one embodiment of the present invention, and FIG. 1 is a structural diagram thereof, FIG. 2 is a voltage-current characteristic diagram when a single insulation layer of I3 aT io 3 is formed, and FIG. FIG. 2 is a voltage-emission characteristic diagram of an EL element using an insulating layer, and FIG. 4 is a voltage-emission characteristic diagram of a conventional example and an embodiment of the same, in which the insulating layer is a composite insulating layer. DESCRIPTION OF SYMBOLS 1... Light emitting layer, 4... Surface electrode, 5... Back electrode. 77 pieces Z shoulder 79 different Fu <-1
Claims (1)
極間に設け、前記発光層に対して外側を高抵抗材料層内
側を低抵抗材料層とする複合絶縁層を前記発光層と接す
るように少なくとも一層設けた薄膜EL素子において、
前記複合絶縁層を1つの材料で形成せしめたことを特徴
とする薄膜EL素子。A light-emitting layer that emits light in response to an electric field is provided between the front electrode and the back electrode, and a composite insulating layer having a high-resistance material layer on the outside and a low-resistance material layer on the inside is in contact with the light-emitting layer. In a thin film EL element provided with at least one layer,
A thin film EL device characterized in that the composite insulating layer is formed of one material.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1083799A JPH02262295A (en) | 1989-03-31 | 1989-03-31 | Thin film el element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1083799A JPH02262295A (en) | 1989-03-31 | 1989-03-31 | Thin film el element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02262295A true JPH02262295A (en) | 1990-10-25 |
Family
ID=13812703
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1083799A Pending JPH02262295A (en) | 1989-03-31 | 1989-03-31 | Thin film el element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02262295A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1995027303A1 (en) * | 1994-03-31 | 1995-10-12 | Orion Electric Company Ltd. | Flat display and method of its manufacture |
-
1989
- 1989-03-31 JP JP1083799A patent/JPH02262295A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1995027303A1 (en) * | 1994-03-31 | 1995-10-12 | Orion Electric Company Ltd. | Flat display and method of its manufacture |
US5698353A (en) * | 1994-03-31 | 1997-12-16 | Orion Electric Company, Ltd. | Flat display and method of its manufacture |
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