JPH0226106A - Delay line - Google Patents

Delay line

Info

Publication number
JPH0226106A
JPH0226106A JP63176637A JP17663788A JPH0226106A JP H0226106 A JPH0226106 A JP H0226106A JP 63176637 A JP63176637 A JP 63176637A JP 17663788 A JP17663788 A JP 17663788A JP H0226106 A JPH0226106 A JP H0226106A
Authority
JP
Japan
Prior art keywords
signal
slit
line
hole
signal connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63176637A
Other languages
Japanese (ja)
Other versions
JP2666391B2 (en
Inventor
Hideki Kusamitsu
秀樹 草光
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63176637A priority Critical patent/JP2666391B2/en
Publication of JPH0226106A publication Critical patent/JPH0226106A/en
Application granted granted Critical
Publication of JP2666391B2 publication Critical patent/JP2666391B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To cause an upper limit signal frequency, which can be delayed, to be high and to easily control the length of a delay line by inserting a connector to a slit at an arbitrary position and constituting the induction line of a prescribed length. CONSTITUTION:The interval of terminals for signal connection between respective modules 9 is connected in a shape to go through a ground surface 6 by a through-hole 8 for signal connection, whose internal wall is formed with a metallic film. Slits 20 are provided to a dielectric plate 7A or 7B so that the part of the through-hole 8 can be parted. Then, the electric connection is separated. Connecting pieces 16, which are provided to a connector 15 and mutually insulated, are inserted to the slit 20 and the through-hole 8, which is electrically disconnected, is caused to be in a conductive condition. By inserting the connecting piece 16 to the slit 20, cascade connection is executed for the induction line of the module 9 and the induction line of the desired length is formed. A signal is supplied from the upper module 9 and fetched from the termination of the formed induction line by a signal fetching piece 17.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は分布定数型の遅延線路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a distributed constant type delay line.

〔従来の技術〕[Conventional technology]

従来の分布定数型遅延線路は、第8図の断面図に示すよ
うな構造をしている。すなわち、中心導体11と外部導
体14とで構成された同軸状の線路の中心導体11をフ
ェライト13などの磁性材料の表面にコイル状に巻いて
インダクタンスを増加させ、さらに、中心導体11と外
部導体14の間に誘電体12を配している。このコイル
状に巻かれた中心導体11のインダクタンスLと中心導
体11と外部導体14間の分布容量Cとにより遅延線路
を形成していた。
A conventional distributed constant delay line has a structure as shown in the cross-sectional view of FIG. That is, the center conductor 11 of a coaxial line composed of a center conductor 11 and an outer conductor 14 is wound in a coil shape on the surface of a magnetic material such as ferrite 13 to increase inductance, and further, the center conductor 11 and the outer conductor A dielectric material 12 is arranged between the parts 14 and 14. The inductance L of the coiled center conductor 11 and the distributed capacitance C between the center conductor 11 and the outer conductor 14 form a delay line.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の分布定数型遅延回路は、一般にインダク
タンスLが静電容量Cよりも大きくなるので、この回路
の持つ特性インピーダンスZ。;存在する浮遊容量の影
響を受けやすく、遅延時間の長い遅延回路はど、遅延可
能な上限の信号周波数は低くなる欠点がある。また、フ
ェライト上に中心導体11をコイル状に巻き、さらに、
その上に誘電体をかぶせる構造のため、インダクタンス
Lの調整が極めて困難であった。
In the conventional distributed constant type delay circuit described above, the inductance L is generally larger than the capacitance C, so the characteristic impedance Z of this circuit. Delay circuits that are easily affected by existing stray capacitance and have a long delay time have the disadvantage that the upper limit signal frequency that can be delayed becomes low. In addition, the center conductor 11 is wound in a coil shape on the ferrite, and further,
Because of the structure in which a dielectric material is placed on top of the dielectric material, it is extremely difficult to adjust the inductance L.

本発明の目的は遅延可能な上限の信号周波数を高くし、
かつ、遅延線路長の調整を容易に行うことができる遅延
線路を提供することにある。
The purpose of the present invention is to increase the upper limit signal frequency that can be delayed,
Another object of the present invention is to provide a delay line whose length can be easily adjusted.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の遅延線路は両端に信号接続用端子を有するマイ
クロストリップラインによる誘導線路パタンと、接地面
を構成する接地パタンと、前記誘導線路パタンと前記接
地パタンとを絶縁して交互に積層するための誘電体板と
、積層された前記複数の誘導線路パタンの信号接続用端
子間を複数の信号接続用スルーホールにより複数の接地
パタンおよび誘電体板を貫通して縦続接続した遅延線路
において、前記各誘電体板の信1号接続用スルーホール
を分断するスリットと、前記スリットにより分断された
信号接続用スルーホールの金属膜間を導通させる互いに
独立した金属片と信号入出力用の金属片とを有する接続
子とを備え、前記接続子を任意の位置の前記スリットに
挿入して所定の長さの誘導線路を構成している。
In the delay line of the present invention, a guiding line pattern made of a microstrip line having signal connection terminals at both ends, a grounding pattern constituting a ground plane, and the guiding line pattern and the grounding pattern are insulated and laminated alternately. In the delay line in which the dielectric plate and the signal connection terminals of the plurality of laminated guiding line patterns are cascade-connected by a plurality of signal connection through holes passing through the plurality of ground patterns and the dielectric plate, A slit that divides the signal No. 1 connection through hole of each dielectric plate, a mutually independent metal piece that connects the metal film of the signal connection through hole divided by the slit, and a signal input/output metal piece. A guide line having a predetermined length is constructed by inserting the connector into the slit at an arbitrary position.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図、第2図は本発明の一実施例の要部を示す平面図
であり、第3図は本実施例の要部の構成図である。まず
、第3図は、遅延線路の構成単位であるモジュール9の
構成を示している。すなわち、誘電体板7Aの一面には
金属蒸着等による誘導線路パタン5が形成され、対向す
る他の面は同じく金属蒸着等によるアース面6で形成さ
れている。また誘電体板7Bはモジュール9の多層化に
必要な誘電体板である。誘導線路パタン5は、第1図に
示すように、インダクタンス成分となる誘導線路2がマ
イクロストリップラインで形成されている。またキャパ
シタンス成分は誘導線路2と周辺の図のハツチで示した
アース部4との間で形成される。端子IA、IBは誘導
線路2へのそれぞれ信号入力、出力用の端子であり、後
述する信号接続用スルーホール8につながる。スルーホ
ール3はアース接続用の貫通孔である。アース面6は、
第2図に示すように、貫通孔1’A、1’Bが誘導線路
パタン5の端子IA、IBの信号を後述する信号接続用
スルーホール8による多層化されたほかのモジュールに
供給するための接続線用に開けられている。またハツチ
で示したアース面6のスルーホール3は誘導線路パタン
5のスルーホール3と誘電体板7A、7Bを通してアー
ス接続するための貫通孔である。
1 and 2 are plan views showing the main parts of an embodiment of the present invention, and FIG. 3 is a configuration diagram of the main parts of this embodiment. First, FIG. 3 shows the configuration of a module 9 which is a structural unit of the delay line. That is, a guide line pattern 5 is formed on one surface of the dielectric plate 7A by metal vapor deposition or the like, and the other opposing surface is formed with a ground plane 6 also formed by metal vapor deposition or the like. Further, the dielectric plate 7B is a dielectric plate necessary for making the module 9 multi-layered. In the guide line pattern 5, as shown in FIG. 1, the guide line 2 serving as an inductance component is formed of a microstrip line. Further, a capacitance component is formed between the guide line 2 and the surrounding ground portion 4 indicated by hatching in the figure. Terminals IA and IB are terminals for signal input and output to the guide line 2, respectively, and are connected to a signal connection through hole 8, which will be described later. The through hole 3 is a through hole for ground connection. The ground plane 6 is
As shown in FIG. 2, the through holes 1'A and 1'B are used to supply signals from the terminals IA and IB of the guide line pattern 5 to other multilayered modules using the signal connection through holes 8, which will be described later. Opened for connecting wires. Also, the through hole 3 in the ground plane 6 indicated by a hatch is a through hole for connecting to the ground through the through hole 3 of the guide line pattern 5 and the dielectric plates 7A and 7B.

第4図、第5図は同じく本実施例の複数モジュールの組
立図である。すなわち、複数のモジュール9が多層に積
みあげられた積層構造となっている。アース線10は、
第5図に示すように、各モジュール9の誘導線路パタン
のアース部4とアース面6とを同電位にするためにスル
ーホール3を介して縦方向にすべて接続される。
FIGS. 4 and 5 are also assembly diagrams of a plurality of modules of this embodiment. That is, it has a laminated structure in which a plurality of modules 9 are stacked in multiple layers. The ground wire 10 is
As shown in FIG. 5, the ground portions 4 and the ground planes 6 of the guide line pattern of each module 9 are all connected in the vertical direction via through holes 3 in order to have the same potential.

次に各モジュール間の接続と誘導線路長を設定するため
の構成を第6図の構成説明図により説明する。各モジュ
ール間の信号接続用端子IA、IB間は内壁が金属膜で
形成された信号接続用スルーホール8により、アース面
6を貫通する形で接続されているが、この接続されてい
る信号接続用スルーホール8の部分を分断するように誘
電体板7A、または7Bにスリット20を設は電気的接
続を切りはなす。つぎに図のように、接続子15に設け
られた互いに絶縁された接続片16をスリット20に挿
入して電気的に切りはなされた信号接続用スルーホール
を再び導通状態にする。すなわち第6図A部を拡大した
第7図の断面図に示すように金属膜19が接続片16に
より接続される。
Next, the configuration for setting the connection between each module and the guide line length will be explained with reference to the configuration explanatory diagram of FIG. 6. The signal connection terminals IA and IB between each module are connected by a signal connection through hole 8 whose inner wall is formed of a metal film, passing through the ground plane 6. A slit 20 is provided in the dielectric plate 7A or 7B so as to separate the through hole 8 for electrical connection. Next, as shown in the figure, mutually insulated connection pieces 16 provided on the connector 15 are inserted into the slits 20 to make the electrically disconnected signal connection through holes conductive again. That is, as shown in the cross-sectional view of FIG. 7, which is an enlarged view of section A in FIG. 6, the metal film 19 is connected by the connecting piece 16.

示6図に戻りこのように複数の接続片6をスリット20
に挿入子ることにより、複数のモジュール9の誘導線路
が縦続接続されて所望の長さの誘導線路を形成する。第
6図では、信号が図示していない上部のモジュール9か
ら供給され、この形成された誘導線路の終端から信号取
出し片17により信号が取出される。
Returning to Figure 6, in this way the plurality of connection pieces 6 are connected to the slit 20
By inserting the guide lines into the module 9, the guide lines of a plurality of modules 9 are connected in cascade to form a guide line of a desired length. In FIG. 6, a signal is supplied from an upper module 9 (not shown), and the signal is extracted from the terminal end of the formed guide line by a signal extraction piece 17.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、マイクロストリッ
プラインで形成された遅延線路を多層構成とすることに
より、その特性インピーダンスは、どんなに多層化して
もほぼ一定である。特に信号入出力端子への導入線が短
くなり浮遊容量が少なくなる。したがって使用可能な上
限の周波数特性を劣化させることなく、遅延時間を増加
させることができる。さらに、電気的に分断された多層
化モジュールを接続子により再接続することにより、任
意の長さの遅延線路を構成できるので、遅延時間の調整
が簡単に行なえる効果がある。
As explained above, according to the present invention, the delay line formed of a microstrip line has a multilayer structure, so that its characteristic impedance remains almost constant no matter how many layers there are. In particular, the lead-in lines to the signal input/output terminals are shortened, and stray capacitance is reduced. Therefore, the delay time can be increased without deteriorating the upper limit usable frequency characteristics. Furthermore, by reconnecting electrically disconnected multilayer modules using connectors, a delay line of arbitrary length can be constructed, which has the effect of easily adjusting the delay time.

を拡大した断面図、第8図は従来の遅延線路の構成図で
ある。
FIG. 8 is an enlarged cross-sectional view of the conventional delay line.

LA、IB・・・端子、1’A、1’B・・・貫通孔、
2・・・誘導線路、3・・・スルーホール、4・・・ア
ース部、5・・・誘導線路パタン、6・・・アース面(
接地パタン)、7.7A、7B・・・誘電体板、8・・
・信号接続用スルーホール、9・・・モジュール、10
・・・アース線、11・・・中心導体、12・・・誘電
体、13・・・フェライト、14・・・外部導体、15
・・・接続子、16・・・接続片、17・・・信号取出
し片、18・・・絶縁体、19金属膜、20・・・スリ
ット。
LA, IB... terminal, 1'A, 1'B... through hole,
2...Guidance line, 3...Through hole, 4...Ground part, 5...Guidance line pattern, 6...Ground surface (
Grounding pattern), 7.7A, 7B...dielectric plate, 8...
・Through hole for signal connection, 9...Module, 10
... Earth wire, 11 ... Center conductor, 12 ... Dielectric material, 13 ... Ferrite, 14 ... Outer conductor, 15
... Connector, 16... Connection piece, 17... Signal extraction piece, 18... Insulator, 19 Metal film, 20... Slit.

Claims (1)

【特許請求の範囲】[Claims]  両端に信号接続用端子を有するマイクロストリップラ
インによる誘導線路パタンと、接地面を構成する接地パ
タンと、前記誘導線路パタンと前記接地パタンとを絶縁
して交互に積層するための誘電体板と、積層された前記
複数の誘導線路パタンの信号接続用端子間を複数の信号
接続用スルーホールにより複数の接地パタンおよび誘電
体板を貫通して縦続接続した遅延線路において、前記各
誘電体板の信号接続用スルーホールを分断するスリット
と、前記スリットにより分断された信号接続用スルーホ
ールの金属膜間を導通させる互いに独立した金属片と信
号入出力用の金属片とを有する接続子とを備え、前記接
続子を任意の位置の前記スリットに挿入して所定の長さ
の誘導線路を構成することを特徴とする遅延線路。
A guiding line pattern formed by a microstrip line having signal connection terminals at both ends, a grounding pattern constituting a ground plane, and a dielectric plate for insulating and alternately stacking the guiding line pattern and the grounding pattern. In the delay line in which the signal connection terminals of the plurality of laminated guiding line patterns are cascade-connected by a plurality of signal connection through holes passing through the plurality of grounding patterns and dielectric plates, the signal of each of the dielectric plates is A connector having a slit that divides the connection through hole, a mutually independent metal piece that connects the metal film of the signal connection through hole divided by the slit, and a signal input/output metal piece, A delay line characterized in that a guide line of a predetermined length is constructed by inserting the connector into the slit at an arbitrary position.
JP63176637A 1988-07-14 1988-07-14 Delay line Expired - Fee Related JP2666391B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63176637A JP2666391B2 (en) 1988-07-14 1988-07-14 Delay line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63176637A JP2666391B2 (en) 1988-07-14 1988-07-14 Delay line

Publications (2)

Publication Number Publication Date
JPH0226106A true JPH0226106A (en) 1990-01-29
JP2666391B2 JP2666391B2 (en) 1997-10-22

Family

ID=16017062

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63176637A Expired - Fee Related JP2666391B2 (en) 1988-07-14 1988-07-14 Delay line

Country Status (1)

Country Link
JP (1) JP2666391B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09191205A (en) * 1995-12-04 1997-07-22 Lucent Technol Inc Signal separation microwave splitter/combiner
WO2008108003A1 (en) * 2007-03-02 2008-09-12 Nec Corporation Compact filtering structure

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5446232U (en) * 1977-09-06 1979-03-30
JPS5723926U (en) * 1980-07-10 1982-02-06
JPS58117701A (en) * 1982-01-06 1983-07-13 Nec Corp High frequency strip line
JPS59202702A (en) * 1983-05-02 1984-11-16 Juichiro Ozawa Delay line element

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5446232U (en) * 1977-09-06 1979-03-30
JPS5723926U (en) * 1980-07-10 1982-02-06
JPS58117701A (en) * 1982-01-06 1983-07-13 Nec Corp High frequency strip line
JPS59202702A (en) * 1983-05-02 1984-11-16 Juichiro Ozawa Delay line element

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09191205A (en) * 1995-12-04 1997-07-22 Lucent Technol Inc Signal separation microwave splitter/combiner
WO2008108003A1 (en) * 2007-03-02 2008-09-12 Nec Corporation Compact filtering structure
JP2010520652A (en) * 2007-03-02 2010-06-10 日本電気株式会社 Compact filtering structure
US8378762B2 (en) 2007-03-02 2013-02-19 Nec Corporation Compact filtering structure

Also Published As

Publication number Publication date
JP2666391B2 (en) 1997-10-22

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