JPH02260714A - Pll circuit - Google Patents

Abstract

PURPOSE:To perform the phase-locking of an output signal with the scale of 1/2 of a reference signal F2 by selecting the relation of f2 with f3 as f3=f2/4, and providing a polarity inversion switching circuit for an error signal in a phase-locked loop circuit(PLL). CONSTITUTION:The circuit is comprised so that the PLL can be established by selecting either a point 2 or a point 5 by adding the polarity inversion switching circuit 10 and inverting the polarity of an error voltage. Therefore, the PLL can be established at all the points 1-6 corresponding to the selection of a tuning voltage Vt and the setting of the polarity inversion switching circuit. Here, assuming that it is f2-2f3=2f3, namely, f2=4f3 or f3=f2/4, the points 1-6 are arranged with an equal interval of 2f3=f2/2. In such a way, it is possible to phase-lock f1 with a f2/2 step without switching f3.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention applies a phase lock to a phase-locked loop circuit (hereinafter referred to as a PLL circuit), particularly an oscillator in an ultra-high frequency band such as a microwave, at every fixed step frequency. P
This invention relates to improvements in LL circuits.

(Conventional technology) FIG. 6 shows a conventionally used PLL circuit.

The output of a voltage controlled oscillator (hereinafter referred to as VCO) 1 in an ultra-high frequency band such as a microwave is mixed with a high-order harmonic of the output f2 of the first reference signal generator 3 in a sampler 2, and a large number of IF multiplied signals are generated. Occur. Of these, only those below f2 are extracted by a low-pass filter (hereinafter referred to as LPF) 4, and this is compared with the output f3 of the second reference signal generator 5 by a phase/frequency detector (hereinafter referred to as PFD) 6. A PLL circuit is formed in which the error signal obtained is extracted by the LPF 7 and the DC amplifier 8 and added to the tuning voltage of the VCO 1 created by the tuning voltage setting means 9.

With this configuration, the output frequency f1 becomes L
-nfz + f3 or fI - nfz fs by setting the tuning voltage Vt so that the value of n corresponding to the desired - is selected. It is possible to obtain a phase-locked ultra-high frequency signal with a precise frequency by steps of . However, in the conventional technique, as shown in FIG. 6, when trying to reduce the step interval that can be set for the output frequency f, it is necessary to lower the frequency of f in accordance with the step interval. In this case, the order n of the harmonics actually used becomes large, which reduces the efficiency of the sampler and makes it difficult to implement a phase-locked loop (PLL).

Furthermore, as n becomes large, the phase noise component leakage in nf□ increases in proportion to the phase-locked signal f,
The disadvantage is that the noise (C/N ratio) also deteriorates.

(Problem to be Solved by the Invention) If the initial setting frequency of - deviates by f, 72 or more, there is a risk of being phase-locked to harmonics of an undesired order.
When f2 is low, it is better to control the initial value of f more accurately, and to keep f2 high while still increasing f.
, can be set in small steps, and the frequency range in which the PFD must operate is wide.

(Means for solving the problem and its effect) In the present invention, a means for switching the polarity of the error signal is provided in the phase-locked loop, and the relationship between f2 and f is changed to fs=f*
/4, it is possible to phase-lock f in steps of fz/2.

As a result, the value of f to obtain the same step can be twice that of the conventional method, and the above-mentioned problem can be greatly alleviated.

(Embodiment) FIG. 1 shows an embodiment of the present invention, in which parts having the same functions as in the conventional example shown in FIG. 6 are given the same numbers. FIG. 2 is a diagram showing the relationship between frequencies for explaining the operation of the embodiment. In the configuration shown in Figure 1, phase lock is possible when fs=lf+n-l, ->
If nfx, -=-nfz +rs (point corresponding to 2 in FIG. 2), and fI>r+4z fs (point corresponding to 5 in FIG. 2).

In the conventional example (FIG. 6), PLL is established only in cases 2 or 5, which are determined by the polarity of the loop. Therefore, even if the order n was changed, PLL was established only at the f2 step point corresponding to the point 1.2.3 or version 4.5.6 in FIG.

On the other hand, in the embodiment shown in FIG.
By adding , and inverting the polarity of the error voltage, it is possible to select either point 2 or 5 in FIG. 2 to establish a PLL. Therefore, depending on the selection of the tuning voltage Vt and the setting of the polarity inversion switching circuit, it is possible to establish a PLL at all points 1.degree. 2.3.4.5.6 in FIG. Here ft 2fs
=2fs or ft""4fx or rs-ft/
4, each point of 1.2.3°4.5.6 is 2f x
They are arranged at equal intervals of −f z/2. That is, by switching f, 11<1+ can be phase-locked in f2/2 steps. For example, in a specific example, f, -rs80MHz, fs-2
0M1 (set to z, use n -20 to 100 to 198
Signals from 0 MHz to 8020 MHz are obtained in 40 MHz steps.

The control signal to the polarity inversion switching circuit 10 is obtained by inputting the desired oscillation frequency F to the control device 11, calculating F/ft within the control device 11, and calculating the remainder f! Switching is performed by determining whether the value is larger than or smaller than /2.

The polarity inversion switching circuit can be realized with a simple circuit as shown in FIG. 3, for example, using an analog switch and an operational amplifier.

FIG. 4 is a diagram showing another embodiment of the present invention, in which two
The polarity of the error voltage of the PLL loop is changed by switching the input signal to the PFD 6 using the high frequency switches 12 and 13, and the other operations are the same as those shown in FIG. 12.13 requires a switch capable of switching high-frequency signals, but since the signal frequency is limited to values near f, an inexpensive switch with a relatively narrow band can suffice.

In addition, in this invention, f2 and f have a simple proportional relationship, so f2 can be created by multiplying f by 4 as shown in Figure 5 (a), or conversely, as shown in Figure 5 (b). It is possible to create f by dividing f2 by 4, and it is also possible to use only one expensive reference oscillator.

(Effect of the invention) As explained in detail above, in this invention, f.

By selecting the relationship between and f as fx=fz/4 and providing a polarity inversion switching circuit for the error signal in the PLL, it is possible to phase-lock the output signal with a precision of 1/2 of the reference signal f2. did. Furthermore, the two reference signals are
Since it can be easily created from several stable signal sources, it has the effect of economically realizing a high-performance signal source with low noise and phase locking in small steps. We will provide useful technology to achieve this goal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the invention; FIG. 2 is a diagram showing frequency relationships for explaining the invention in detail;
3 is a diagram showing a configuration example of a polarity inversion switching circuit used in the embodiment of FIG. 1, FIG. 4 is a block diagram showing another embodiment of the present invention, and FIG. 5 is a standard used in this invention. Figure 6 is a diagram showing a method for simply creating a signal. In the diagram, 1 is a voltage controlled oscillator, 2 is a sampler, 3 is an oscillator, 4 is a low-pass filter, 5 is an oscillator, and 6 is a phase controller. A frequency detector, 7 a low-pass filter, 8 a DC amplifier, 9 a tuning voltage setting means, 10 a polarity inversion switching circuit,
11 is a control device, 12 is a switch, and 13 is a switch.

Claims (1)

[Claims] Difference frequency between the output f_1 of the voltage controlled oscillator (1) and the higher harmonic nf_2 of the first reference signal f_2 |f_1-n
t_2|
The PLL is controlled to match the reference signal f_3 of
In the circuit, a second reference signal generator (5) receives the output of the first reference signal generator (3) and generates a second reference signal having a frequency of 1/4 of the frequency of the second reference signal generator (3); means (6) for generating an error signal from the frequency |f_1-nf_2| and the second reference signal; the voltage controlled oscillator receiving the error signal; and the polarity of the error signal input to the voltage controlled oscillator. a switch (10) inserted into the PLL circuit to switch the frequency of the first reference signal; A PLL circuit comprising: a device (11) for controlling the connection of the circuit to be switched between a first state and a second state.