JPH02260671A - Optical semiconductor device - Google Patents
Optical semiconductor deviceInfo
- Publication number
- JPH02260671A JPH02260671A JP1082805A JP8280589A JPH02260671A JP H02260671 A JPH02260671 A JP H02260671A JP 1082805 A JP1082805 A JP 1082805A JP 8280589 A JP8280589 A JP 8280589A JP H02260671 A JPH02260671 A JP H02260671A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- lead frame
- type gaas
- auge
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 230000003287 optical effect Effects 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 150000001875 compounds Chemical class 0.000 claims abstract description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract description 6
- 229910045601 alloy Inorganic materials 0.000 abstract description 5
- 239000000956 alloy Substances 0.000 abstract description 5
- 238000007747 plating Methods 0.000 abstract description 4
- 239000012535 impurity Substances 0.000 abstract description 3
- 229910005703 Ge—Ag Inorganic materials 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 229910002058 ternary alloy Inorganic materials 0.000 abstract description 2
- 229910052737 gold Inorganic materials 0.000 abstract 1
- 229910052709 silver Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 32
- 239000002184 metal Substances 0.000 description 5
- 238000001035 drying Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 239000011261 inert gas Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000001771 vacuum deposition Methods 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 150000007513 acids Chemical class 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Led Device Packages (AREA)
- Led Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は光半導体装置に関し、特に化合物半導体を用い
た光半導体装置のオーミック電極の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an optical semiconductor device, and more particularly to the structure of an ohmic electrode of an optical semiconductor device using a compound semiconductor.
従来、Ｎ型ＧａＡｓ基板を有する赤外ＬＥＤは、ボンデ
ィング方法として導電性ペーストを用いてＡｇメツキさ
れたリード・フレーム上にダイ・ボンディングする方式
が主流である。Conventionally, the mainstream bonding method for infrared LEDs having an N-type GaAs substrate has been die bonding onto an Ag-plated lead frame using a conductive paste.
第３図に示すように、赤外り、ＥＤチップ１０底面のオ
ーミック電極は、Ｎ型ＧａＡｓ基板１１とのオーミック
性を高める第１ＡｕＧｅ層１５と、電極形成時の熱アロ
イに於けるＡｕＧｅとＧａＡＳとの液相反応を抑制する
ためのＮｉ層１６、そして最表面金属は酸・アルカリに
対する腐食に強いＡｕ層１７を順次有する構造となって
いる。As shown in FIG. 3, the ohmic electrode on the bottom surface of the infrared ED chip 10 is made of a first AuGe layer 15 that enhances ohmic properties with the N-type GaAs substrate 11, and a layer of AuGe and GaAS in the thermal alloy during electrode formation. The structure has a Ni layer 16 for suppressing a liquid phase reaction with the metal, and an Au layer 17 whose outermost surface metal is resistant to corrosion by acids and alkalis.
そして赤外ＬＥＤチップ１０のリード・フレームへのダ
イ・ボンディング工程については、第４図に示すように
、Ａ、ｇメツキＪ’１Ｊ２２を有するリード・フレーム
２３の表面に導電性ペースト２４を塗布した後、赤外Ｌ
Ｅ Ｄチップ１０を加圧接触させることにより得られ
る。その後、導電性ペースト２４の溶剤を揮発させるた
めに、リード・フレーム２３を約２００℃の不活性ガス
中で約１時間乾燥する。As for the die bonding process of the infrared LED chip 10 to the lead frame, as shown in FIG. Back, infrared L
It is obtained by bringing the ED chip 10 into pressure contact. Thereafter, in order to volatilize the solvent of the conductive paste 24, the lead frame 23 is dried in an inert gas at about 200° C. for about 1 hour.
ダイ・ボンディング強度については、赤外ＬＥＤチップ
１０の側面にはい上った導電性ペースト２４により、必
要な強度が保たれていると考えられている。Regarding the die bonding strength, it is believed that the conductive paste 24 that has climbed up the side surface of the infrared LED chip 10 maintains the necessary strength.
上述した従来の光半導体装置１例えば赤外ＬＥＤのダイ
・ボンディング方法には、以下に述べる欠点がある。The die bonding method for the conventional optical semiconductor device 1, such as an infrared LED, described above has the following drawbacks.
（１）赤外ＬＥＤの電極の最表面金属となるＡｕと導電
性ペーストは、そのダイ・ボンディング工程に於いて、
前述の乾燥工程を通過するが、Ａｕと導電性ペーストは
共晶を形成するものではなく、前述したように赤外ＬＥ
Ｄチップのリード・フレームへの固定は主に導電性ペー
ストの赤外ＬＥＤチップ側面へのはい上りにより得られ
る。ところが赤外ＬＥＤチップ側面にはＰＮ接合が露出
している構造が一般的であるため、ダイ・ボンディング
強度の向上を目的として導電性ペーストの塗布量を増加
させることは、ＬＥＤショートによる著しい製品選別歩
留の低下と信顆度レベルの低下をもたらす。(1) During the die bonding process, Au, which is the outermost metal of the infrared LED electrode, and conductive paste are
Although it passes through the drying process described above, the Au and conductive paste do not form a eutectic, and as described above, the infrared LE
Fixing of the D chip to the lead frame is achieved mainly by creeping conductive paste onto the side surface of the infrared LED chip. However, since infrared LED chips generally have a structure in which the PN junction is exposed on the side surface, increasing the amount of conductive paste applied for the purpose of improving die bonding strength results in severe product selection due to LED shorting. This results in lower yield and lower reliability levels.
（２）例えば赤外ＬＥＤチップを用いた製品であるホト
・カプラは、市場より大量供給・低価格が要求される。(2) For example, photocouplers, which are products using infrared LED chips, are required to be supplied in large quantities and at low prices compared to the market.
その実行案としてリード・フレームのフープ化による大
量生産を目ざした組立ライン設計が考えられるが、組立
ラインのインデックスが極めて短いこと、速乾性の導電
性ペーストの選定が困難であること等を考慮すると、赤
外ＬＥＤチップを導電性ペーストを用いてダイ・ボンデ
ィングする方法では、前案による組立ライン設計のメリ
ットをいかすことができない。One possible implementation plan is to design an assembly line with the aim of mass production by hooping the lead frame, but considering the extremely short index of the assembly line and the difficulty of selecting a quick-drying conductive paste, etc. , the method of die-bonding infrared LED chips using conductive paste cannot take advantage of the assembly line design of the previous proposal.
本発明の光半導体装置は、化合物半導体基板と該化合物
半導体基板の底面に形成されたオーミック電極とを有す
る光半導体装置において、前記オーミック電極の最表面
層をＡ ｕ Ｇ ｅ層またはＡｕＳｎ層で構成したもの
である。The optical semiconductor device of the present invention includes a compound semiconductor substrate and an ohmic electrode formed on the bottom surface of the compound semiconductor substrate, in which the outermost surface layer of the ohmic electrode is composed of an AuG e layer or an AuSn layer. This is what I did.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の断面図であり、光半導体装
置として赤外ＬＥＤを用いた場合を示している。FIG. 1 is a sectional view of one embodiment of the present invention, showing a case where an infrared LED is used as an optical semiconductor device.
Ｓｉを不純物とするＮ型ＧａＡｓ基板１１上に、Ｓｉを
両性不純物元素として得られるＮ型ＧａＡｓエピタキシ
ャル層１２．Ｐ型ＧａＡｓエピタキシャル層１３を順次
エピタキシャル成長する。その後Ａ ｕ Ｚ ｎ系の合
金の蒸着及びパターン加工によりＰ側電極１４を形成し
、次にＮ型ＧａＡｓ基板１１の底面に、第１ＡｕＧｅ層
１５、Ｎｉ層１６．Ａｕ層１７及び第２ Ａ ｕ Ｇ
ｅ層１８からなるオーミック電極１９を形成する。An N-type GaAs epitaxial layer 12 obtained using Si as an amphoteric impurity element is formed on an N-type GaAs substrate 11 containing Si as an impurity. A P-type GaAs epitaxial layer 13 is epitaxially grown in sequence. Thereafter, a P-side electrode 14 is formed by vapor deposition and patterning of an A u Z n-based alloy, and then a first AuGe layer 15 , a Ni layer 16 . Au layer 17 and second Au G
An ohmic electrode 19 made of the e-layer 18 is formed.
第１ Ａ ｕ Ｇ ｅ Ｒ１５はＧｅの含有率を約１％
（重量比）のＡｕを蒸着ソースとして真空蒸着方法によ
り形成する。さらに連続してＮｉ層１６及びＡｕ層１７
を形成した後約４００℃の不活性ガス中にて熱アロイを
行なう。その後再び真空蒸着方法により融点温度が３５
６℃であるＧｅの含有率１２％（重量比）のＡｕを蒸着
ソースとして第２ＡｕＧｅ層１８を形成する。The first A u G e R15 has a Ge content of about 1%.
It is formed by a vacuum evaporation method using (weight ratio) of Au as a evaporation source. Furthermore, a Ni layer 16 and an Au layer 17 are continuously formed.
After forming, thermal alloying is performed in an inert gas at about 400°C. After that, the melting point temperature was reduced to 35% by vacuum evaporation method again.
The second AuGe layer 18 is formed using Au having a Ge content of 12% (weight ratio) at 6° C. as a deposition source.
次にこのように構成された赤外ＬＥＤチップのリードフ
レームへのダイ・ボンディングについて第２図を用いて
説明する。Next, die bonding of the infrared LED chip configured as described above to the lead frame will be explained using FIG. 2.
Ａｇメツキ層２２の形成されたＦｅを主成分とするリー
ド・フレーム２３のマウント・アイランド部分をヒータ
ーにより約４００°Ｃの温度に加熱し、赤外ＬＥＤチッ
プ１０をのせ、約５０ｇ程度の加重を加えてダイ・ボン
ディングする。このとき第２ Ａ ｕ Ｇ ｅ層１８は
、融点温度３５６℃を上回るエネルギーを受は溶融する
が、Ａｕ層１７よりＡｕを、そしてＡｇメツキ層２２よ
りＡｇの拡散を受けＡｕ−Ｇｅ−Ａｇの三元系の合金部
２１を形成する。ダイ・ボンディングされた赤外ＬＥＤ
チップ１０はマウント・アイランド部分がヒーターから
離されることにより常温まで冷却され、合金部２１は固
化する。内部歪を自己解消し易い金属であるＡｕ系金属
であるＡｕ層１７及び第２ Ａ ｕ Ｇ ｅ Ｎ １８
を、各々１μｍ程度の厚さとすることにより、Ｎ型Ｇ
ａ Ａ ｓ基板１１とリード・フレーム２３との間の熱
膨張係数差は解消され、歪による通電劣化レベルの影響
は生じない。The mounting island portion of the lead frame 23, which is mainly made of Fe and has the Ag plating layer 22 formed thereon, is heated to a temperature of about 400°C using a heater, the infrared LED chip 10 is placed on it, and a load of about 50 g is applied. In addition, die bonding is performed. At this time, the second AuGe layer 18 receives energy exceeding the melting point temperature of 356°C and melts, but the Au-Ge-Ag layer 18 is diffused by Au from the Au layer 17 and Ag from the Ag plating layer 22. A ternary alloy portion 21 is formed. Die bonded infrared LED
The chip 10 is cooled to room temperature by separating the mounting island portion from the heater, and the alloy portion 21 is solidified. The Au layer 17 is made of an Au-based metal, which is a metal that easily eliminates internal strain, and the second Au G e N 18
By making the thickness of each about 1 μm, N-type G
The difference in thermal expansion coefficient between the aAs substrate 11 and the lead frame 23 is eliminated, and the current deterioration level due to strain is not affected.
第２ＡｕＧｅ層１８の代りにＡｕＧｅ層を用いることか
できる。このとき用いるＳｎの含有率を約２０％（重量
比）とすることにより溶融点温度は２８０ ’Ｃに下が
る。従ってＡｕＳｎ層を用いる場合は、ダイ・ボンディ
ング時のリード・フレームの加熱温度を約３００℃に下
げることが可能になるため、Ｎ型ＧａＡｓ基板１１とリ
ード・フレーム２３との間の熱膨張係数差をより低減で
きる利点がある。An AuGe layer can be used instead of the second AuGe layer 18. By setting the content of Sn used at this time to about 20% (weight ratio), the melting point temperature is lowered to 280'C. Therefore, when using an AuSn layer, it is possible to lower the heating temperature of the lead frame during die bonding to approximately 300°C, which reduces the difference in thermal expansion coefficient between the N-type GaAs substrate 11 and the lead frame 23. This has the advantage of further reducing
なお上記実施例においては光半導体装置として赤外ＬＥ
Ｄを用いた場合について説明したが、化合物半導体基板
とオーミック電極を有するホトトランジスタ等地の光半
導体装置であってもよい。Note that in the above embodiment, an infrared LE is used as the optical semiconductor device.
Although the case where D is used has been described, an optical semiconductor device such as a phototransistor having a compound semiconductor substrate and an ohmic electrode may be used.
以上説明したように本発明は、化合物半導体基板の底面
に形成されたオーミック電極の最表面層をＡｕＧｅＪｌ
またはＡｕＳｎ層とすることにより、素子間のショート
の危険をともなわずに、リードフレームとのダイ・ボン
ディング強度を向上させることができる。又導電性ペー
ストを用いたダイ・ボンディングのような乾燥工程を必
要としないため、リード・フレームのフープ化といった
大量生産・低価格化への対応が可能になるという効果を
有する。As explained above, in the present invention, the outermost layer of the ohmic electrode formed on the bottom surface of the compound semiconductor substrate is formed using AuGeJl.
Alternatively, by using an AuSn layer, die bonding strength with the lead frame can be improved without the risk of short circuit between elements. Furthermore, since a drying process such as die bonding using conductive paste is not required, it is possible to respond to mass production and cost reduction, such as by forming a lead frame into a hoop.
第１図は本発明の一実施例の断面図、第２図は本発明の
一実施例をリードフレームにダイ・ホンディングした場
合の断面図、第３図は従来例の断面図、第４図は従来例
をリードフレームにダイ・ホンディングした場合の断面
図である。
１０−＝赤外ＬＥＤチップ、１１ ・Ｎ型ＧａＡｓ基板
、１２・・・Ｎ型ＧａＡｓエピタキシャルｊ―、１３・
・・Ｐ型ＧａＡｓエピタキシャル層、１４・・・Ｐ側電
極、１５・・・第１ Ａ ｕ Ｑ ｅ層、１６−Ｎｉ層
、１７−・−Ａｕ層、１８−・・第２ＡｕＧｅ層、２１
＝−合金部、２２・・・Ａｇメツキ層、２３・・・リ
ード・フレーム、２４・・・導電性ペースト。Fig. 1 is a sectional view of an embodiment of the present invention, Fig. 2 is a sectional view of an embodiment of the present invention die-bonded to a lead frame, Fig. 3 is a sectional view of a conventional example, and Fig. 4 is a sectional view of an embodiment of the present invention. The figure is a sectional view of a conventional example when die-bonded to a lead frame. 10-=infrared LED chip, 11・N-type GaAs substrate, 12...N-type GaAs epitaxial j-, 13・
...P-type GaAs epitaxial layer, 14--P side electrode, 15--first Au Qe layer, 16-Ni layer, 17--Au layer, 18--second AuGe layer, 21
=-alloy part, 22...Ag plating layer, 23...lead frame, 24...conductive paste.
Claims (1)
れたオーミック電極とを有する光半導体装置において、
前記オーミック電極の最表面層をＡｕＧｅ層またはＡｕ
Ｓｎ層で構成したことを特徴とする光半導体装置。In an optical semiconductor device having a compound semiconductor substrate and an ohmic electrode formed on the bottom surface of the compound semiconductor substrate,
The outermost layer of the ohmic electrode is an AuGe layer or an Au layer.
An optical semiconductor device comprising an Sn layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1082805A JPH02260671A (en) | 1989-03-31 | 1989-03-31 | Optical semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1082805A JPH02260671A (en) | 1989-03-31 | 1989-03-31 | Optical semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02260671A true JPH02260671A (en) | 1990-10-23 |
Family
ID=13784626
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1082805A Pending JPH02260671A (en) | 1989-03-31 | 1989-03-31 | Optical semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02260671A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002124524A (en) * | 2000-10-16 | 2002-04-26 | Kyocera Corp | Wiring board |
| US7829910B2 (en) | 2005-01-31 | 2010-11-09 | Shin-Etsu Handotai Co., Ltd. | Light emitting device and method of fabricating light emitting device |
| JP2013157423A (en) * | 2012-01-30 | 2013-08-15 | Toyoda Gosei Co Ltd | Semiconductor device manufacturing method and semiconductor device |
-
1989
- 1989-03-31 JP JP1082805A patent/JPH02260671A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002124524A (en) * | 2000-10-16 | 2002-04-26 | Kyocera Corp | Wiring board |
| JP4605883B2 (en) * | 2000-10-16 | 2011-01-05 | 京セラ株式会社 | Wiring board |
| US7829910B2 (en) | 2005-01-31 | 2010-11-09 | Shin-Etsu Handotai Co., Ltd. | Light emitting device and method of fabricating light emitting device |
| JP2013157423A (en) * | 2012-01-30 | 2013-08-15 | Toyoda Gosei Co Ltd | Semiconductor device manufacturing method and semiconductor device |
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