JPH0226038A - Fixing method of electronic element - Google Patents
Fixing method of electronic elementInfo
- Publication number
- JPH0226038A JPH0226038A JP63176386A JP17638688A JPH0226038A JP H0226038 A JPH0226038 A JP H0226038A JP 63176386 A JP63176386 A JP 63176386A JP 17638688 A JP17638688 A JP 17638688A JP H0226038 A JPH0226038 A JP H0226038A
- Authority
- JP
- Japan
- Prior art keywords
- period
- solder
- temperature
- semiconductor element
- brazing material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 22
- 238000005219 brazing Methods 0.000 claims abstract description 31
- 239000000463 material Substances 0.000 claims abstract description 27
- 230000004913 activation Effects 0.000 claims abstract description 17
- 230000004907 flux Effects 0.000 claims abstract description 12
- 238000010438 heat treatment Methods 0.000 claims abstract description 12
- 238000002844 melting Methods 0.000 claims description 23
- 230000008018 melting Effects 0.000 claims description 22
- 239000000945 filler Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 229910000679 solder Inorganic materials 0.000 abstract description 84
- 239000004065 semiconductor Substances 0.000 description 56
- 238000003825 pressing Methods 0.000 description 20
- 230000007423 decrease Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- 238000007711 solidification Methods 0.000 description 5
- 230000008023 solidification Effects 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 238000001816 cooling Methods 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000013459 approach Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000001629 suppression Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000006071 cream Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 230000001737 promoting effect Effects 0.000 description 2
- 239000002689 soil Substances 0.000 description 2
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 1
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 description 1
- 238000005299 abrasion Methods 0.000 description 1
- 230000002730 additional effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000000844 transformation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はトランジスタ、ダイオード、ＩＣ等の電子素子
を支持体に対し、てろう材を介し、て固着する方法に関
し６．更に詳り、 ＜は、１１子素子と支持板の間に介
在するろう材１の熱抵抗を減少させることができる電子
素子を固着する方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for fixing electronic elements such as transistors, diodes, ICs, etc. to a support via a brazing material.6. In more detail, < relates to a method for fixing an electronic device that can reduce the thermal resistance of the brazing material 1 interposed between the 11-element device and the support plate.
〔従来の技術及び発明が解決し、よりとする課題〕多く
の電力用半導体装置においては、半導体素子が放熱性の
良い支持板に対し、て手出付けされた構造となっている
。上記の半導体素子の支持板への固着はダイマウント法
あるいはりフロー法と称される方法で行われることがあ
る。以下にこの方法を簡単に説明する。まず、半導体素
子を固着すべき支持板の薔固漕面にペースト手出Ｃクリ
ーム中日〕を所定の厚みで供給する。通常、ペースト手
出の供給はスクリーン印刷法によって行われる。[Problems solved and improved by the prior art and the invention] Many power semiconductor devices have a structure in which semiconductor elements are attached to a support plate with good heat dissipation. The above-mentioned semiconductor element is sometimes fixed to the support plate by a method called a die mounting method or a reflow method. This method will be briefly explained below. First, a predetermined thickness of the paste (Cream Chunichi) is applied to the hardening surface of the support plate on which the semiconductor element is to be fixed. Usually, the application of paste paste is done by screen printing method.
次に、このペースト手出の上面に半導体素子を載置する
。載置された半導体素子はペースト手出の粘着力によっ
て支持板に仮固着される。次に、半導体素子が仮固着さ
れた支持板を加熱炉に投入し。Next, a semiconductor element is placed on the top surface of this paste handle. The placed semiconductor element is temporarily fixed to the support plate by the adhesive force of the paste. Next, the support plate to which the semiconductor element is temporarily fixed is placed in a heating furnace.
て、ペーヌト手出を加熱し、て再溶融（リフｏ−）させ
る。リフロー後に半田が固化することにより半導体素子
は支持板に固着される。Then, heat the paint and remelt it. The semiconductor element is fixed to the support plate by solidifying the solder after reflow.
上記のダイマウントを、複数の支持板が連結されたリー
ドフレームの状態で行うことにより、−度に多数個の半
導体素子の半田付けが行える。ところで、半導体装置に
おいては放熱性を向上することがＮ要な課題であり、こ
のために半導体素子と支持板との間に介在する半田層の
熱抵抗が少Ｌ２でも小さいことが望まれる。半田層の熱
抵抗を小さくするためには半導体素子と支持板との間に
気泡の少ない良好な半田層を極力薄く形成する必要があ
る。上記のダイ７ウント法では半田層を薄く形成すると
気泡が多く発生したり、半導体素子の下面全体に半田層
が良好に広がらす、半田層を薄く形成し、たにもかかわ
らす熱抵抗を十分に小さくｊることが困難であった。By performing the above die mounting on a lead frame to which a plurality of support plates are connected, a large number of semiconductor elements can be soldered at one time. By the way, improving heat dissipation is an important issue in semiconductor devices, and for this purpose, it is desirable that the thermal resistance of the solder layer interposed between the semiconductor element and the support plate be as small as possible, even if it is only a small amount L2. In order to reduce the thermal resistance of the solder layer, it is necessary to form a good solder layer with few bubbles between the semiconductor element and the support plate as thin as possible. In the above-mentioned die-cutting method, if the solder layer is formed thinly, many bubbles will be generated, and the solder layer will spread well over the entire bottom surface of the semiconductor element. It was difficult to make small adjustments.
そこで１本発明の目的は、上記の問題を解決し、。Therefore, one object of the present invention is to solve the above problems.
電子素子と支持体との間に介在するろり材層の熱抵抗を
小さくするごとができる電子素子の固着方法を提供する
ことにある。An object of the present invention is to provide a method for fixing an electronic device, which can reduce the thermal resistance of a sintering material layer interposed between the electronic device and a support.
上記目的を連成するための本発明は、支持体（ｎ所定の
箇所に７ラツクスを含有するろう材を供給し、前記ろり
材の上に電子素子を載置し、前記ろう材を加熱１て溶融
することで前記電子素子を前言ピ支持体に対し、て前記
ろう材を介し、て固着する方法において、前記ろう材の
溶融期間における溶融開始時点から前記フラックスの活
性化期間中又は後の任意の時点までを第１の期間とし、
かつ前記溶融期間の前記第１の期間よりも後の一部又は
全部の期間を第２の期間とり、た場合に、前記第２ ｏ
）期間での前記ろう材の＃冨を前記第１の期間での前記
ろう材の荷重よりも大きくすることによって前記第２の
期間での前記ろう材の層厚を前記第１の期間での前記ろ
う材の層Ｎよりも小さくすることを特徴とする電子素子
の固着方法に係わるものである。In order to achieve the above object, the present invention supplies a brazing material containing 7 lux to a predetermined location of a support (n), places an electronic element on the brazing material, and heats the brazing material for 1 hour. In the method of fixing the electronic element to the support via the brazing material by melting the electronic element, the electronic device is fixed to the support through the brazing material, from the start of melting during the melting period of the brazing material to during or after the activation period of the flux. The first period is up to an arbitrary point,
and a part or all of the period after the first period of the melting period is taken as a second period;
) The layer thickness of the brazing filler metal in the second period is increased from the layer thickness of the brazing filler metal in the first period by making the # thickness of the brazing filler metal in the period larger than the load of the brazing filler metal in the first period. The present invention relates to a method for fixing an electronic device, characterized in that the brazing material layer N is made smaller than the layer N of the brazing material.
本発明においては、電子素子を支持体に対してろう付け
する際に、第２の期間に抑圧等によってろり材の荷重を
大きくする。この結果、電子素子と支持体との間に介在
するろう材の層厚を小さくすることができる。更に、ろ
う材が溶融状態にあり、かつフラックスの活性化【てい
る期間を含む第１の期間の後の第２の期間にろう材を肉
薄化するために、１ｉ子素子と支持体との間に介在する
ろり材層の気孔の発生率を有効に減少できる。In the present invention, when brazing the electronic element to the support, the load on the filtration material is increased by suppressing or the like during the second period. As a result, the layer thickness of the brazing material interposed between the electronic element and the support can be reduced. Further, in order to thin the brazing material during a second period after the first period, which includes a period in which the brazing material is in a molten state and the flux is being activated, the connection between the 1i element and the support is performed. The incidence of pores in the intervening filler material layer can be effectively reduced.
第１図〜第６図を参照し、て不発明の一実施例とし、て
の半導体素子の固着方法を以下に説明する。With reference to FIGS. 1 to 6, a method for fixing a semiconductor element will be described below as an embodiment of the present invention.
ます、第６図のようなリードフレーム１を用意する。リ
ードフレーム１は図示のように複数個の支持体としての
半田付は可能な金楕板から成る支持板２とそれに対応す
る外部リード３を有する。First, a lead frame 1 as shown in FIG. 6 is prepared. As shown in the figure, the lead frame 1 has a plurality of support plates 2 made of gold oval plates that can be soldered as supports, and external leads 3 corresponding to the support plates 2.
なお、半導体素子は支持板２の一方の主面の機内−Ｎ部
４に半田を介し６て固着されることとなる。Note that the semiconductor element is fixed to the inside-N section 4 of one main surface of the support plate 2 via solder 6.
次に、第１図（ａ＋に示すようにリードフレーム１０す
べての支持板２の被固着ｓ４に半田５を供給する。半田
５は鉛と錫の共晶合金力・ら＃：Ｄ、粘着性を有するペ
ースト状の半田（クリーム半田）である。この半田５は
半田ぬれ性を向上するためにロジン糸の７ラツクスを含
有し、ている。なお、半田５の供給は従来例と同様にス
クリーン印刷法によって行い、被固着部４に所望な厚み
で供給される。Next, as shown in FIG. This solder 5 is a paste-like solder (cream solder) having 7 lux of rosin threads to improve solder wettability.The solder 5 is supplied using a screen as in the conventional example. This is done by a printing method, and the adhesive is supplied to the adhered portion 4 in a desired thickness.
次に、第１図（ｂｌに示すように、被固着部４に供給さ
れた半田５の土に半導体素子６を半田５に対し、て若干
押えつけるようにし、て載置する。半導体素子６は半田
５の粘着力によって被固着部４に仮固着される。なお、
半導体素子６と支持板２の間に介在する中日５０層厚は
約２０μｍである。なお１図示は省略し、ているが、半
導体素子６０）下面。Next, as shown in FIG. 1 (bl), the semiconductor element 6 is placed on the soil of the solder 5 supplied to the adhered portion 4 while being slightly pressed against the solder 5.Semiconductor element 6 is temporarily fixed to the fixed part 4 by the adhesive force of the solder 5.
The thickness of the Chunichi 50 layer interposed between the semiconductor element 6 and the support plate 2 is approximately 20 μm. Although not shown in the figure, the bottom surface of the semiconductor element 60).
即ち支持板２に固着される側の主面全体にニッケル電極
が形成されている。また、上面には部分的にアルε電極
が形成されている。That is, the nickel electrode is formed on the entire main surface of the side fixed to the support plate 2. Further, an aluminum ε electrode is partially formed on the upper surface.
リードフレーム１のすべての支持板２の被固着部４に半
導体素子６が固着された後にリードフレーム１をｍ熱炉
に投入する。なお、リーと７レ−ム１はホルダー（挟持
用治具）によって挾持され。After the semiconductor elements 6 are fixed to the fixed parts 4 of all the support plates 2 of the lead frame 1, the lead frame 1 is put into a heating furnace. Incidentally, the Lee and the 7th frame 1 are held together by a holder (a holding jig).
ホルダーを移動することによってＷ熱炉内を移動させる
。加熱炉内には複数個のヒーターブロックが配置さｔて
おり、リードフレーム１はこの正方を移動する。リード
フレーム１を加熱炉に投入することによって、支持板２
土に供給された半田５は加熱されて溶融する。ここで、
加熱炉内のり−トフレーム１の通路の温度分布はリード
フレーム１の投入口と取出口で温度が比較的低く、炉内
の中央側で相対的に高く設定されている。し、たかって
、半田５の温度はリードフレーム１が加熱炉内を移動す
ることによって第２図のよりに変化する。By moving the holder, it is moved inside the W heat furnace. A plurality of heater blocks are arranged in the heating furnace, and the lead frame 1 moves in this square. By putting the lead frame 1 into the heating furnace, the support plate 2
The solder 5 supplied to the soil is heated and melted. here,
The temperature distribution in the passageway of the lead frame 1 in the heating furnace is such that the temperature is relatively low at the input and output ports of the lead frame 1 and relatively high at the center of the furnace. However, the temperature of the solder 5 changes as shown in FIG. 2 as the lead frame 1 moves within the heating furnace.
因示のように、 ｔｏ時点を出発点とし、てリードフレ
ーム１が加熱炉の中央に移動Ｔるにつれて半田５は温度
上昇し、て、１１時点で半田浴４！ｌｌ温度（約１８３
℃）に逼り２．やがてｔｓ時点で最高温度Ｃ約２７０℃
）に到趣１”る。ｔ３〜ｔ４の＃高温度の期間（−定温
度期間）は約２０秒間に設定されている。−定温度期間
後、半田５の温度は１降し、、１７時点で溶融温度以）
となって固化する。なお、半田５の最高温度は半田５内
に含有された７ラツクスの活性化温度（約２３０℃）エ
フも高い温度（２７０℃）に設定されている。７う゛ツ
クスの活性化温度よりも高い期間は１３時点よりも少し
、前の１２時点から１４時点よりも少し、後のｔｓ時点
までである。As indicated, the temperature of the solder 5 rises as the lead frame 1 moves to the center of the heating furnace starting from the time t, and at the time 11, the solder bath 4! ll temperature (approximately 183
℃) 2. Eventually, the maximum temperature C reached approximately 270℃ at TS.
). The high temperature period (-constant temperature period) from t3 to t4 is set to about 20 seconds. - After the constant temperature period, the temperature of the solder 5 drops by 1". below the melting temperature)
It solidifies. Note that the maximum temperature of the solder 5 is set at the activation temperature of the 7 luxes contained in the solder 5 (approximately 230°C), which is also a high temperature (270°C). The period of time when the activation temperature of the 7th vox is higher is a little more than the 13th time point, from the previous 12th time point to a little more than the 14th time point, and up to the later ts time point.
半導体素子６と支持板２との間に介在する半田５の層厚
は半田５が溶融温度を越えて溶融状態となると、半導体
素子６に基づく荷重によって半田５のＭｋ庫は減少する
と考えられる。し、かし、実際には層厚が減少すること
はほとんどない。このため、半田５の温度が溶融温度を
越えて＃高温度に運り、ても、半導体素子６と支持板２
との間に介在する牛田５０層厚は第１図ｔｂ＋に示す仮
固着時と大差のない厚さＣ約２０μｍ）を維持する。第
２図では、溶融開始時点、から７ラツクス活性化温度期
間の終了時点ｔ６の直後の時点ｔ６までを第１の期間と
し、ている。It is thought that when the layer thickness of the solder 5 interposed between the semiconductor element 6 and the support plate 2 exceeds the melting temperature and becomes molten, the Mk of the solder 5 decreases due to the load caused by the semiconductor element 6. However, in reality, the layer thickness rarely decreases. Therefore, even if the temperature of the solder 5 exceeds the melting temperature and reaches a high temperature, the semiconductor element 6 and the support plate 2
The thickness of the Ushida 50 layer interposed between the two is maintained at a thickness C (approximately 20 μm), which is not much different from that at the time of temporary fixation as shown in FIG. 1 tb+. In FIG. 2, the first period is from the start of melting to a time t6 immediately after the end time t6 of the 7 lux activation temperature period.
最高温度から溶融温度に向って半田５の温度が下り始め
た１６時点以後の第２の期間において、半導体素子６を
支持′＆２に対し７て押圧治具７によって押圧する。な
お、この実施例では、ＩＩＡ勤装置（移動装置）７ａに
よって押圧治具７を半導体素子６上に移動する。上記の
溶融温度に近づいた期間では半田５か完全に溶融し、た
状態から流動性が低下し、て牛固融の状態に移行する期
間である。半導体素子６と支持板２との間に介在し、た
半田５は半導体素子６を介し、て押圧されることによっ
て半導体素子６の下面全体に広がり、その一部は半導体
素子６の下部から押し、出される。結果とし、て、半導
体素子６と支持板２０間に介在する半田５の層厚を約８
μｍに均一に肉薄化できる。半田５は押圧治具７に工っ
て押圧されている間に固化が始まっているよりに見られ
る。し、かり、完全溶融−半溶融−固化とい５相変化は
微妙であ＃）４ｃ密には判別できない。し、たがって、
押圧治具７を離間させる時期′１に溶融温度に一致させ
ているが、Ａ密に−致し、ているとはいえない。半導体
素子６を押圧し。In a second period after time 16 when the temperature of the solder 5 begins to decrease from the maximum temperature to the melting temperature, the semiconductor element 6 is pressed against the support '&2 by the pressing jig 7. In this embodiment, the pressing jig 7 is moved onto the semiconductor element 6 by the IIA movement device (moving device) 7a. In the period when the solder 5 approaches the above-mentioned melting temperature, the solder 5 completely melts, and the fluidity decreases from the previous state to a solid state. The solder 5 interposed between the semiconductor element 6 and the support plate 2 spreads over the entire lower surface of the semiconductor element 6 by being pressed through the semiconductor element 6, and a part of it is pushed from the bottom of the semiconductor element 6. , served. As a result, the layer thickness of the solder 5 interposed between the semiconductor element 6 and the support plate 20 is approximately 8.
Can be uniformly thinned to μm. It can be seen that the solder 5 has begun to solidify while being pressed by the pressing jig 7. However, the five-phase change from complete melting to semi-melting to solidification is subtle and cannot be clearly distinguished. therefore,
Although the pressing jig 7 is separated at the timing '1' to match the melting temperature, it cannot be said that it closely matches the melting temperature. Press the semiconductor element 6.
ている期間では半田５が溶融し、ている期間ではあるか
、一定温度期間のように半田５が十分に溶融状態にある
のではなく、若干溶融状態が損なわれた状態である。し
、たがって、抑圧を解いても、＃−導体素子６の側方に
押し、出された半田５が再び半導体素子６の下方にもど
って肉摩化することはない。リードフレーム１が加熱炉
の出口に近づくと。During this period, the solder 5 is melted, and the solder 5 is not in a sufficiently molten state as in the constant temperature period, but is in a state where the molten state is slightly impaired. Therefore, even if the suppression is released, the solder 5 pushed to the side of the #- conductor element 6 and ejected will not return to the bottom of the semiconductor element 6 and become abrasion. When the lead frame 1 approaches the outlet of the heating furnace.
半田５は温度か低下し、やがて固化する。固化し、た後
に、半導体素子６と支持板２の間に介在する半田５の層
厚は約８μｍとなっている。なお、上記のよりに溶融温
度を境とし、て完全溶融状態−生溶融状態一固化という
相変化をするが、実際には目視で確認できるほど明硲な
ものではない。また。The temperature of the solder 5 decreases and eventually solidifies. After solidification, the layer thickness of the solder 5 interposed between the semiconductor element 6 and the support plate 2 is approximately 8 μm. As described above, the phase change occurs from a completely molten state to a raw molten state to solidification at the melting temperature, but this is not so clear that it can be visually confirmed. Also.
半田５σ、）温度分布等によって−様な相変化を七、て
いるとは限らない。Solder does not always undergo a -like phase change due to temperature distribution, etc.
本実施例は以下の効果を有する。This embodiment has the following effects.
１１１ 半導体素子６と支持板２との間に介在する半
田５の層厚を８μｍ程度に肉薄に形成し、ても。111 Even if the layer thickness of the solder 5 interposed between the semiconductor element 6 and the support plate 2 is formed as thin as about 8 μm.
本実施例では半田５の層内に発生する気泡が少ない。し
、たがって＃Ｉ抵抗の小さい半田層を得ることができる
。即ち、単に肉薄の半田５の鳩を形成するのであれば、
おもりを載置する方法等により半導体素子６を初めから
押圧し、た状態とし、て加熱炉に適せばよい。しかし、
この場合、肉薄化し、た半田５の層に気泡が比較的多く
発生する。本実施例では、フラックスの活性化温度を越
える温度を所定期間Ｃ約２５秒）経たのちに半導体素子
６を押圧し、ている。このため、上記の気泡の発生を著
、 ＜減少し、ている。気泡を減少できる理由は以下の
よ）に考えらｆ″Ｌる。半田５が加熱されて、半田５内
に含有し、たフラックスの活性化温度を越えると。In this embodiment, there are few bubbles generated within the layer of solder 5. Therefore, a solder layer with low #I resistance can be obtained. That is, if simply forming a thin solder dove 5,
The semiconductor element 6 may be pressed from the beginning by a method such as placing a weight on the semiconductor element 6 to be in a flat state, which is suitable for a heating furnace. but,
In this case, a relatively large number of bubbles are generated in the thin solder layer 5. In this embodiment, the semiconductor element 6 is pressed after the temperature exceeds the activation temperature of the flux for a predetermined period C (approximately 25 seconds). For this reason, the generation of the above-mentioned bubbles is significantly reduced. The reason why air bubbles can be reduced is as follows. When the solder 5 is heated to exceed the activation temperature of the flux contained in the solder 5.
このフラックスが活性化し、艮好な半田付けを可能とす
る。このとき、フラックスは分解に伴うガスを発生し、
、このガスが半田５ＦＥＪＩＣ多く残存する七午田５の
１内に気泡（ホイド）ができる。本実施例ではフラック
スの活性化温度を越える温度上昇期間の後期及び温度一
定期間及び温度下降期間の初期の約２５秒間（第１の期
間）では半田５の層厚を約２０μｍ程度と比較的浄く保
っている。し、たがって、上記のガスあるいは７ラツク
スの残渣は半導体素子６０刊１・ら側方に良好に移動り
、てガスの大手は雰囲気中に放出される。結果とり、て
半田５中に気泡の発生が少なく、半導体素子６の下部の
半田５の中の気泡の体積比を５％以下とすることができ
た。なお、上記の半導体素子６におもりを載せる方法等
による半導体素子６の抑圧では、７ラツクスの活性化温
度以前記半田５を肉薄化するため、後に７ラツクスの活
性化温度に運し。This flux is activated and enables beautiful soldering. At this time, the flux generates gas as it decomposes,
, this gas forms bubbles (hoids) in the Nachigota 5 where a large amount of the solder 5FEJIC remains. In this embodiment, the layer thickness of the solder 5 is kept relatively clean at about 20 μm in the latter half of the temperature rising period exceeding the flux activation temperature, the constant temperature period, and the initial period of about 25 seconds (first period) of the temperature falling period. It is kept well. Therefore, the above-mentioned gas or the residue of 7 lux easily moves to the side from the semiconductor device, and a large amount of the gas is released into the atmosphere. As a result, fewer air bubbles were generated in the solder 5, and the volume ratio of air bubbles in the solder 5 below the semiconductor element 6 could be reduced to 5% or less. Note that in the method of suppressing the semiconductor element 6 by placing a weight on the semiconductor element 6, etc., the solder 5 is brought to an activation temperature of 7 lux before being brought to an activation temperature of 7 lux in order to become thinner.
たとき、上記のガスの側方への移動が良好に行われない
。し、たがって気泡の発生が相対的に多くなｔ）気泡の
面積比を１０％以下とすることはできな力１つだ。When this occurs, the above-mentioned lateral movement of gas is not performed satisfactorily. However, the generation of bubbles is relatively large. t) It is impossible to reduce the bubble area ratio to 10% or less.
（２１温度下降期の後学の半田５の流動性が完全溶融状
態よりも抽なわれた期間に半導体素子６を抑圧するので
、半田５の層厚を確実に肉薄化できる。また、半田５の
層厚の変動を防止できる。また、温度下降期で押圧治具
７を当接させるので。(Since the fluidity of the solder 5 in the 21st temperature decline period suppresses the semiconductor element 6 during the extracted period rather than the completely molten state, the layer thickness of the solder 5 can be reliably reduced. Also, since the pressing jig 7 is brought into contact during the period of temperature decline, variations in the layer thickness can be prevented.
半導体素子６及び手出５の冷却が助長され、半田５の固
化の促進に有効である。This facilitates cooling of the semiconductor element 6 and the handle 5, and is effective in promoting solidification of the solder 5.
（３１半導体素子６が押圧されることで半田５を広範囲
に広げることが可能である。し、たがって、半導体素子
６の下面全体に半田５を広け′ることができる。また、
供給する半田５の量を少量化できる効果も付加的に得ら
れる。(31 By pressing the semiconductor element 6, it is possible to spread the solder 5 over a wide range. Therefore, the solder 5 can be spread over the entire lower surface of the semiconductor element 6.
An additional effect of reducing the amount of solder 5 to be supplied is also obtained.
［変形例〕 本発明は上述の実施例に限定されるものでなく。[Modified example] The invention is not limited to the embodiments described above.
例えは次の変形が可能なものである。For example, the following transformations are possible:
（１１第４囚のように押圧治具７を冷却装置８によって
冷却し、てもよい。この場合、実施例よりも更に半田５
の薄型化効果及び半田５の固化促進の効果が期待できる
。(The pressing jig 7 may be cooled by the cooling device 8 as in the fourth case of 11. In this case, the solder 5 is further cooled than in the embodiment.
The effect of reducing the thickness of the solder 5 and promoting the solidification of the solder 5 can be expected.
（２） 第５図のように空気孔９を有する押圧治具７
を使用し、押圧治具７を半導体素子６に当接する際に、
圧縮空気噴出装置１０７１１・ら空気孔９に冷却空気を
供給し、、この突気孔９から冷却空気を噴出し、でもよ
い。このようにＴることで、第４図の押圧治具と同等の
効果が得られる。また、第５図の押圧治具の場合、押圧
治具７を半導体素子６から廂関させておき、全気孔９か
ら噴出する圧ｌａ全空気よ！ｌｌ＃−導体素子６を押圧
し、てもよい。(2) Pressing jig 7 with air holes 9 as shown in Fig. 5
When bringing the pressing jig 7 into contact with the semiconductor element 6 using
The compressed air blowing device 10711 may supply cooling air to the air holes 9, and blow out the cooling air from the blow holes 9. By making T in this way, the same effect as the pressing jig shown in FIG. 4 can be obtained. In addition, in the case of the pressing jig shown in FIG. 5, the pressing jig 7 is separated from the semiconductor element 6, and the pressure la that is blown out from all the pores 9 is equal to the total air! ll#-conductor element 6 may be pressed.
（３１半導体素子６を押圧する第２の期間を、半田５に
含有した７ラツクスの活性化温度以上の温度期間の一部
を経たのちに設定子ｆ″Ｌば気泡の発生の防止効果はそ
ｔ′Ｌなジに祷られる。し、かし、、十分な気泡の発生
防止効果を得るためには７ラツクスの活性化温度以上の
期間を約５秒以上とし、てその後に半田５を肉薄化する
ことがよい。し、たがって。(If the second period in which the semiconductor element 6 is pressed is carried out after part of the period at which the temperature is higher than the activation temperature of the 7 luxes contained in the solder 5, the effect of preventing the generation of bubbles will be reduced. However, in order to obtain a sufficient effect of preventing the generation of bubbles, the period of time above the activation temperature of 7 lux should be approximately 5 seconds or more, and then the solder 5 should be applied thinly. Therefore, it is better to become
本実施例の温度一定期間の後期に押圧し、てもよい。The pressure may be applied in the latter half of the constant temperature period in this embodiment.
し、かし、温度一定期間に押圧することによる格別な利
点はなく、むし、ろ正妃のガスも、 ＜は７ラツクスの
残渣の移動が良好に行われる期間が減少するし、手出５
０層厚に変動が生じ易（、決し６て望まし、いとはいえ
ない。したがって、実施例のように半田５の温度が最高
温度から溶融温度に下降し。However, there is no special advantage to pressing during a constant temperature period, and on the contrary, the period during which the residue of <7 lux can be transferred well is reduced, and the method 5
The thickness of the solder layer 5 tends to fluctuate (which is by no means desirable or desirable. Therefore, as in the embodiment, the temperature of the solder 5 falls from the maximum temperature to the melting temperature.
て半田５の流動性が低下する期間、さらに望まし。It is even more desirable to have a period during which the fluidity of the solder 5 decreases.
くは上ｋＸＡ／ｉＪＪの後期の７ラツクス活性化温＆以
下となる期間が良い。A period during which the activation temperature is below 7 lux activation temperature in the latter half of upper kXA/iJJ is better.
（４１支持体は導体層を有する回路基板等であってもよ
い。(The support 41 may be a circuit board or the like having a conductor layer.
（５１手出中への気泡の発生を十分に防止するため半田
の最高温度はフラックス活性化温度より５℃以上筒いこ
とが望まし、い。又、手出５０層厚を肉薄化するのはフ
ラックス活性化温度以上の期間の５秒以上経たのちに行
うのが良い。さらに、半田５の層摩は押圧前記は１５Ａ
ｍ以上とするのが望−！し、い。(It is desirable that the maximum temperature of the solder is at least 5°C higher than the flux activation temperature in order to sufficiently prevent the generation of bubbles in the solder. Also, the thickness of the solder 50 layer should be reduced. It is best to carry out the process after a period of 5 seconds or more that the temperature is above the flux activation temperature.Furthermore, the layer of solder 5 is applied with a pressure of 15A.
I hope it is more than m! Yes, yes.
（６１本実施例では押圧治具７を半田５が溶融温度に近
づいた際に半導体素子６に当＃Ｌ、、溶融温度に通した
際に半導体素子６から離間し、ているが。(61 In this embodiment, the pressing jig 7 is placed on the semiconductor element 6 when the solder 5 approaches the melting temperature, and is separated from the semiconductor element 6 when the solder 5 reaches the melting temperature.
こ九に限られない。例えは温度下降期間中連続して当接
させていてもよいし、溶融温度以下に温度が下ってから
離間ニーでもよい。また、軽い押圧治具７を加熱全期間
において半導体素子６上に載置し、抑圧が要求されると
きにのみ駆動装置７ａ又は別の装置又は手で押圧治具７
を押圧し５．結果とし、て半田５の荷重を大きく Ｌ、
てもよい。It is not limited to these nine. For example, they may be brought into contact continuously during the temperature drop period, or they may be separated after the temperature drops below the melting temperature. In addition, a light pressing jig 7 is placed on the semiconductor element 6 during the entire heating period, and only when suppression is required, the pressing jig 7 is operated by the driving device 7a, another device, or by hand.
Press 5. As a result, the load on solder 5 is increased L,
You can.
（７１実施例では押圧治具７を駆動装置７ａで上下方向
に移動することによって押圧治具７を半導体素子６に当
接させ、半田５Ｖｃ必要な＃重を与えているが、押圧治
具７を固定し、、支持板２及び半導体素子６を上下動さ
せることによって必要な荷重を半田５に与えることがで
きる。(In the 71st embodiment, the pressing jig 7 is brought into contact with the semiconductor element 6 by moving the pressing jig 7 in the vertical direction by the driving device 7a, and the necessary # weight of the solder 5Vc is applied, but the pressing jig 7 A necessary load can be applied to the solder 5 by fixing the solder 5 and moving the support plate 2 and the semiconductor element 6 up and down.
＋８１ 同相温度と液相温度が異なる半田の場合。+81 For solder with different in-phase temperature and liquidus temperature.
半田層を相対的に肉薄にするのは半田の温度が固相温度
と液相温度の間もし、くは液相温度に近い温度のときに
行うのが良い。It is best to make the solder layer relatively thin when the solder temperature is between the solidus temperature and the liquidus temperature, or at a temperature close to the liquidus temperature.
本発明によれは電子素子と支持体との間に介在するろう
材層の熱抵抗を小さくすることができる。According to the present invention, the thermal resistance of the brazing material layer interposed between the electronic element and the support can be reduced.
Ｃｄ）
ｍ１図ｔａ＋ （ｂ＋ ｔｃＴＩま本発明の一実施例に
係わる半導体素子の固着方法を説明するための断面図。
第２図は半田の温度変化と抑圧期間との関係を示す崗。
第３囚は半導体素子を固着するためのリードフレームな
示す平面図。
第４囚は変形例の固着装置を示す断面図。
第５図は別の変形例の固着装置を示す断面図である。
２・・・支持板、５・・・半田、６・・・半導体素子、
７・・・押圧治具。Cd) m1 Figure ta+ (b+ tcTI) A cross-sectional view for explaining a method for fixing a semiconductor element according to an embodiment of the present invention. Fig. 2 shows the relationship between solder temperature change and suppression period. Fig. 4 is a plan view showing a lead frame for fixing a semiconductor element. Fig. 4 is a sectional view showing a modified example of the fixing device. Fig. 5 is a sectional view showing another modified example of the fixing device. 2. ...Support plate, 5...Solder, 6...Semiconductor element,
7... Pressing jig.
Claims (1)
材を供給し、前記ろう材の上に電子素子を載置し、前記
ろう材を加熱して溶融することで前記電子素子を前記支
持体に対してろう材を介して固着する方法において、 前記ろう材の溶融期間における溶融開始時点から前記フ
ラックスの活性化期間中又は後の任意の時点までを第１
の期間とし、かつ前記溶融期間の前記第１の期間よりも
後の一部又は全部の期間を第２の期間とした場合に、前
記第２の期間での前記ろう材の荷重を前記第１の期間で
の前記ろう材の荷重よりも大きくすることによつて前記
第２の期間での前記ろう材の層厚を前記第１の期間での
前記ろう材の層厚よりも小さくすることを特徴とする電
子素子の固着方法。[Scope of Claims] [1] By supplying a brazing material containing flux to a predetermined location of a support, placing an electronic element on the brazing material, and heating and melting the brazing material. In the method of fixing the electronic element to the support via a brazing material, the first step is from the start of melting during the melting period of the brazing material to any time during or after the activation period of the flux.
and when a part or all of the period after the first period of the melting period is a second period, the load of the brazing material in the second period is equal to the first period. The layer thickness of the brazing filler metal in the second period is made smaller than the layer thickness of the brazing filler metal in the first period by making the load on the brazing filler metal larger than the load on the brazing filler metal in the period. Features a method for fixing electronic devices.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63176386A JPH0682697B2 (en) | 1988-07-15 | 1988-07-15 | Electronic element fixing method |
| US07/377,906 US4927069A (en) | 1988-07-15 | 1989-07-10 | Soldering method capable of providing a joint of reduced thermal resistance |
| KR1019890010016A KR920005801B1 (en) | 1988-07-15 | 1989-07-14 | Fixing method for electronic element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63176386A JPH0682697B2 (en) | 1988-07-15 | 1988-07-15 | Electronic element fixing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0226038A true JPH0226038A (en) | 1990-01-29 |
| JPH0682697B2 JPH0682697B2 (en) | 1994-10-19 |
Family
ID=16012740
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63176386A Expired - Fee Related JPH0682697B2 (en) | 1988-07-15 | 1988-07-15 | Electronic element fixing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0682697B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015167187A (en) * | 2014-03-04 | 2015-09-24 | 日立化成株式会社 | Electronic part manufacturing method and intermediate product of electronic part |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016129205A (en) | 2015-01-09 | 2016-07-14 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method |
-
1988
- 1988-07-15 JP JP63176386A patent/JPH0682697B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015167187A (en) * | 2014-03-04 | 2015-09-24 | 日立化成株式会社 | Electronic part manufacturing method and intermediate product of electronic part |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0682697B2 (en) | 1994-10-19 |
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