JPH0225934A - Data processor - Google Patents

Abstract

PURPOSE:To accurately and quickly carry out an instruction with a small quantity of hardware by controlling the stack pointer where the transfer of value is controlled by an address calculation stage to the stack pointer controlled by an execution stage based on the presence or absence of replacement of the address calculation stage. CONSTITUTION:The value of a stack pointer is transferred to another stack pointer which is controlled by an execution stage 205 synchronously with the flow of an instruction in a pipeline only in the case the stage stack pointer ASP of an address calculation stage 203 is replaced when an address is calculated at the stage 203. Thus it is possible to obtain a data processor which performs the correct control of the stack pointer without stopping the relevant instruction at the stage 203 with a small quantity of hardware and even in the case the instruction following the instruction which rewrites the value of the stack pointer at the execution stage produces no conflict related to the stack pointer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device that achieves high processing capacity by using an advanced pipeline processing mechanism.

(Prior Art) As a prior art, there is a stack pointer circuit shown in Japanese Patent Application No. 145852/1983.

FIG. 33 is a block diagram of a conventional stack pointer calculation section. The data processing device shown in the conventional example executes instructions by pipeline processing, and the instruction fetch stage (
IF stage), instruction decode stage (D stage)
, operand address calculation stage (A stage), operand fetch stage (F stage), and execution stage (E stage). 61 is a stage stack pointer (ASP) managed in the address calculation stage, 62 is an ASP output latch, 63 is a stage stack pointer (FSP) managed in the operand fetch stage, 64 is an FSP output latch, 65
is the stage stack pointer (C5P) managed in the execution stage, and 66.67.68 is the stack pointer at the software level (SPI, SPO, 5).
PI).

Figure 34 shows an instruction that includes a stack bush, such as the MOV instruction (which writes the value of a register to the top of the stack (pointed to by the value obtained by decrementing the value of the stack pointer)).
MOV:Rn -> 1il-5P (Rn represents the nth register, a-sp represents the address pointed to by the value obtained by decrementing the stack pointer) is a flowchart showing the operation of the stack pointer at each stage. . The value of ASl'61 before instruction execution is 1nitS
It is assumed that the stack pointer value is consistent with the stack pointer value at the end of the instruction immediately before this instruction.

First, since the source of this instruction is a register, in the A stage, a register designation signal is sent to the next stage, the F stage. The value of ASP61 is decremented by 1 nitsP-
4), and A is decremented in synchronization with the instruction flow.
The value of SP61 (initsP-4) is transferred to PSP63.

The F stage receives a register designation signal and sends a register access signal to the next E stage. When the instruction reaches the E stage, the value of FSP63 (iriitsP-
4) is also sent to C5P65 in the E stage.

In the E stage, the instruction is executed using the value of C3P65 (inftsP-4) as the destination address. That is, the value of the designated register is written to the data register, the value of C3P61 is written to the address register, and the value of the data register is stored at the address indicated by the address register.

Also, regarding 5P166.5PO67, 5P16B,
During instruction execution, these stack pointers retain their previous values, and at the end of each instruction, the value of CSl'65 is changed to the stack pointer (SPI) at the level seen from the software.
, SPO, ,5PI).

Figure 35 shows the case of an instruction that loads data by viewing the stack pointer as a general-purpose register (MOV: “100
"->SP"100" is an immediate value, SP is a stack pointer).

At the A stage, the immediate value "100" is sent to the next F stage. The ASP 61 is transferred to the FSP 63 without change.

This instruction uses the A stage stack pointer (ASP6
The value of 1) remains the previous value until the instruction ends and the value is written to the stack pointer, so if the subsequent instruction refers to the stack pointer (if there is a conflict regarding the stack pointer) ), AS
If address calculation is performed with reference to P61, an incorrect value will be generated. Therefore, the stack pointer is reserved for writing until the instruction ends and the value of the stack pointer is rewritten, and if a later instruction refers to the stack pointer, the write reservation is canceled until the write reservation is canceled. Waiting on stage without performing address calculation. Then, after the write reservation is canceled, A
Start address calculation on stage.

In the F stage, take the immediate value "100" and leave it as is.
100” to the next E stage.

FSP63 is transferred to C5P65.

In the E stage, data "100" is simultaneously written to the ASP 61 and C3P 65 through the port 0 bus 85.

If the instruction after this instruction refers to the stack pointer, the stack pointer (
Since the ASP61) has not been rewritten yet and the stack pointer cannot be referenced, it is waiting in the A stage where address calculation is performed. Then, when the write reservation is released and address calculation starts, the correct value is stored in the ASP61, so when this instruction reaches the E stage, it is accompanied by the correct stack pointer value, and that value is 5P166.5PO67, 5P16B
written to either.

However, if the later instruction does not use the stack pointer, even if the stack pointer is reserved for writing,
There is no need to wait without performing address calculation in the A stage. Therefore, the previous instruction is processed in the E stage and the ASP
By the time 61 is rewritten, processing at the address calculation stage or operand fetch stage may have already been completed. The instruction would then reach the execution stage with an incorrect stack pointer value, the incorrect value would be transferred to the C3P65, and the incorrect value would be sent to SP! at the end of the instruction. 66.5PO67, 5P168
will be written to either.

Therefore, to avoid this, when the value of the stack pointer is rewritten in the E stage, all stage stacks are Either put values into the pointer and each stack pointer output latch at the same time, or if the stack pointer is reserved for writing, make sure that the next instruction stops at the address calculation stage, so that the value of ASP61 is not rewritten. After that, the next instruction needs to start processing in the A stage 33.

[Problem to be solved by the invention]

As described above, in conventional stack pointer processing during vibe line processing, if the value of the stack pointer is updated in the execution stage, the value of the stage stack pointer in the execution stage is attached to that instruction when the next instruction is executed. In order to obtain the correct value, it is necessary to write values to all stage stack pointers and stage stack pointer output latches, or to make sure that the next instruction is stopped at the address calculation stage.

This invention was made in order to solve the above problems, and it uses less hardware and even when the instruction following the instruction that rewrites the stack pointer value in the execution stage does not cause a conflict regarding the stack pointer.
An object of the present invention is to obtain a data processing device that correctly manages a stack pointer without stopping the instruction at an address calculation stage.

[Means to solve the problem]

The data processing device according to the present invention includes a working stage stack pointer in the address calculation stage in the vibe line, and displays an updated value only when the stack pointer managed in the address calculation stage is updated in the address calculation stage. Transferred to the stack pointer managed by the execution stage.

[Effect]

The data processing device according to the present invention is an execution stage in which the value of the stack pointer is synchronized with the flow of instructions in the vibe line only when the stage stack pointer (ASP) of this stage is updated during address calculation in the address calculation stage. Transfer to the stack pointer managed by .

[Embodiments of the Invention] Hereinafter, the present invention will be described in detail based on drawings showing embodiments thereof.

(1) “Instruction format of the data processing device of the present invention”
The instructions of the data processing device of the present invention have a variable length in units of 16 bits, and instructions with an odd number of bytes are not used.

The data processing device of the present invention has an instruction format system that is particularly devised for the purpose of shortening high-frequency instructions. For example, for 2-operand instructions, there is a general format that basically has a configuration of "4 hides + extension part" and all addressing modes can be used, and a general format in which only frequently used instructions and addressing modes can be used. There are two formats: short-han-shuku-gata format.

The meanings of the symbols appearing in the instruction format of the data processing device of the present invention are as follows.

-: Part where operation code is entered #: Part where literal or immediate value is entered Ea: Part that specifies the operand in 8 mini 8-bit addressing mode Sh: Part that specifies the operand in 6-bit abbreviated addressing mode Rn: In the partial format in which operands on registers are designated by register numbers, as shown in FIG. 3, the right side is the LSB side and the higher address. address N and address N
The instruction format cannot be determined without looking at the +1 2-hide, but this is because, as mentioned above, it is assumed that instructions are always fetched and decoded in 16-bit (2-hide) units. .

In the data processing apparatus of the present invention, in any format, the extended part of Ea or sh of each operand is always located immediately after the halfword containing the basic part of Ea or sh. This overrides any immediate data or extensions of the instruction implicitly specified by the instruction. Therefore, 4
For instructions of Hyde or higher, the operation code of the instruction may be separated by the extension part of Ea.

Further, as will be described later, even when an extension part is added to the extension part of Ea in the multi-stage indirect mode, that part is given priority over the next instruction operation code. For example, the first
Halfword contains Eal, second halfword contains Ea
Consider the case of a 6-byte instruction containing 2 and up to the third halfword. Because we used multi-stage indirect mode for Eal,
Assuming that the multi-indirect mode extension is included in addition to the normal extension, the actual instruction bit pattern is the first halfword of the instruction (including the basic part of Eal), the extension of Eat, and the multi-indirect mode of Eal. mode extension, the second halfword of the instruction (including the base of Ea2), the extension of EaL,
This is the order of the third halfword of the instruction.

(1,1) r Shortened Two-Operand Instruction" FIGS. 4 to 7 are schematic diagrams showing the shortened format of a two-operand instruction.

FIG. 4 is a schematic diagram showing the format of an operation instruction between memory registers. This format includes L-format, where the source operand side is memory, and S-format, where the destination operand side is memory.
There is at.

In L-format, Sh represents a specification field of the source operand, Rn represents a specification field of a destination operand register, and RR represents a specification of the sh operand size. The size of the destination operand located on the register is fixed at 32 bits. Sign extension is performed when the size of the register side and the memory side are different and the size of the source side is small.

In the S-format, sh represents a destination operand specification field, Rn represents a source operand register specification field, and RR represents an sh operand size specification. The size of the source operand located on the register is fixed at 32 bits. If the size of the register side and the memory side are different and the size of the source side is large, the overflow portion is truncated and an overflow check is performed.

Figure 5 is the format of the register-register operation instruction)
(R-format). Rn is a destination register designation field, and Rm is a source register designation field. The operand size is only 32 bits.

Figure 6 shows the format of literal-memory operation instructions (
It is a schematic diagram showing Q-format). The question is the destination operand size specification field, ##
# is a literal specification field of the source operand, and sh is a specification field of the destination operand.

Figure 7 shows the format of the immediate value-memory operation instruction) (1
4ormat). property is the operand size specification field (common to source and destination), and sh is the destination operand specification field. The size of the immediate value of I-format is 8.16.32 bits, which is the same as the size of the destination operand, and zero extension and sign extension are not performed.

(1, 2) r-ship-shaped one-operand instruction” Figure 8 shows the single-layer format (Gl-forma) of the one-operand instruction.
It is a schematic diagram showing t). Goods is a specified field of operand size. Some Gl-format instructions have extensions in addition to the Ea extension. There are also instructions that do not use ■.

(1, 3) r-Ship Type 2-Operand Instruction" FIGS. 9 to 11 are schematic diagrams showing the general format of the 2-operand instruction. This format includes instructions that have a maximum of two operands in general addressing mode specified by 8 bits. The total number of operands itself may be three or more.

FIG. 9 is a schematic diagram showing the format (G-format) of an instruction whose first operand requires memory reading. Ea is the destination operand specification field, property is the destination operand size specification field, EaR is the source operand specification field, and R1? is a field specifying the source operand size. In some G-forn+at instructions, Ea
There are extensions other than those of M or [iaR.

FIG. 10 is a schematic diagram showing the format (E-format) of an instruction whose first operand is an 8-bit immediate value.

EaML is a destination operand specification field, item is a destination operand size specification field, and . . . is a source operand value.

Although E-format and I-format are similar in function, they are very different in terms of way of thinking. Specifically, E-format only has two operands.
It is a derivative of the G-format, and the source operand size is fixed at 8 bits, and the destination operand size can be selected from 8, 16, or 32 bits. In other words, E-format is based on the premise of operations between different sizes, and the 8-bit source operand is zero-extended or sign-extended to match the size of the destination operand. On the other hand, I-form
is a shortened form of an immediate value pattern that is frequently used especially in transfer instructions and comparison instructions, and the size of the source operand and destination operand are equal.

FIG. 11 is a schematic diagram showing the format (GA-format) of an instruction whose first operand is only address calculation. Ea- is a destination operand designation field, 4 is a destination operand size designation field, and Ea8 is a source operand designation field. The execution address calculation result itself is used as the source operand.

FIG. 12 is a schematic diagram showing the format of a short branch instruction. cccc is a branch condition specification field, disp:8 is a displacement specification field with respect to the jump destination, and in the data processing device of the present invention, when specifying a displacement with 8 points, the specified value in the bit pattern is doubled. Let it be a displacement value.

(1, 4) r Addressing Mode There are two methods for specifying the addressing mode of the data processing device of the present invention: a short form in which the addressing mode is specified using 6 bits including registers, and a general form in which the addressing mode is specified using 8 pins.

If an undefined addressing mode is specified, or if a semantically inappropriate combination of addressing modes is specified, a reserved instruction exception will occur in the same way as when an undefined instruction is executed. and exception handling is triggered.

This applies in cases where the destination is in immediate mode, or when immediate mode is used in the addressing mode designation field that should involve address calculation.

The meanings of the symbols used in the format diagram are as follows.

Rn: Register specification mem EA: Memory contents of the address indicated by EA (Sh): Specification method in 6-bit abbreviated addressing mode (Ea): Specification method in 8-bit general addressing mode Broken line in the format diagram The area surrounded by indicates an extension.

(1, 4, 1) r Basic Addressing Mode” The data processing device of the present invention supports various addressing modes. Among them, the basic addressing modes supported by the data processing device of the present invention include register direct mode, register indirect mode, register relative indirect mode, immediate value mode, absolute mode, PC (program counter), relative indirect mode, and stack point. There are push mode and stack mode.

In register direct mode, the contents of the register are used as operands. A schematic diagram of the format is shown in FIG.

Rn indicates the number of a general-purpose register.

In register indirect mode, the operand is the contents of the memory whose address is the contents of the register. A schematic diagram of the format is shown in FIG. 14, where Rn indicates the number of the general-purpose register.

In register relative indirect mode, the displacement value is 1.
There are two types depending on whether it is 6 bits or 32 bits. 16 bits or 32 bits for register contents, respectively.
The operand is the contents of the memory whose address is the value plus the bit displacement value. A schematic diagram of the format is shown in FIG. Rn does not indicate the number of a general-purpose register. disp:16 and disp:32 are respectively 16-bit displacement values or 3
The displacement value, which indicates a 2-bit displacement value, is treated as signed.

In the immediate mode, the bit pattern specified in the instruction code is treated as a binary number and used as an operand. A schematic diagram of the format is shown in FIG.

imm-data indicates an immediate value. The size of i+u+-data is specified in the instruction as the operand size.

In absolute mode, the address value is indicated by 16 bits or 32
There are two types depending on whether it is indicated by a bit. Each operand is the contents of the memory whose address is a 16-bit or 32-bit bit pattern specified in the instruction code. A schematic diagram of the format is shown in FIG. a
bs:16 and abs:32 indicate a 16-bit or 32-bit address value, respectively.

When an address is indicated by abs:16, the specified address value is sign-extended to 32 bits.

There are two types of PC relative indirect mode depending on whether the displacement value is 16 bits or 32 bits. Each operand is the contents of the memory whose address is the value obtained by adding a 16-bit or 32-bit displacement value to the contents of the program counter.

A schematic diagram of the format is shown in FIG. disp:
16 and disp:32 each indicate a 16-bit displacement value or a 32-bit displacement value. Displacement values are treated as signed. In PC relative indirect mode, the referenced program counter value is the start address of the instruction containing the operand. When the value of the program counter is referenced in the multi-stage indirect addressing mode, the first address of the instruction is similarly used as the PC-relative reference value.

The stack pop mode uses the contents of the memory whose address is the contents of the stack pointer (SP) as the operand.

After accessing the operand, increment the stack pointer by the operand size.

For example, when handling 32-bit data, SP is updated (incremented) by +4 after operand access. It is also possible to specify stack pop mode for operands of size B and H, each with SP +1.
It is updated (incremented) by +2. A schematic diagram of the format is shown in FIG. A reserved instruction exception is generated for operands for which the stack pop mode has no meaning.

Specifically, the reserved instruction exception is the stack pop mode specification for the write operand and read-modify-write operand.

In stack bush mode, the operand is the contents of the memory whose address is the contents obtained by decrementing the contents of the stack pointer by the operand size. In stack bush mode, the stack pointer is decremented before operand access. For example, when handling 32-bit data, SP is updated (decremented) by -4 before operand access. It is also possible to specify stack bush mode for operands of size B and H, and SP is updated (decremented) by -1 and -2, respectively. A schematic diagram of the format is shown in FIG. For operands for which stacked bush mode has no meaning, a reserved instruction exception is generated. Specifically, the reserved instruction exception is the read operand, r
This is the stack bush mode specification for the ead-modify-write operand.

(1, 4, 2) Multi-stage indirect addressing mode No matter how complex addressing is, it is basically broken down into a combination of addition and indirect references. Therefore, if addition and indirect reference operations are provided as addressing primitives and can be combined arbitrarily, any complex addressing mode can be realized. The multi-stage indirect addressing mode of the data processing device of the present invention is an addressing mode based on this idea. Complex addressing modes are particularly useful for inter-module data references or AI (artificial intelligence) language processing systems.

When specifying the multi-stage indirect addressing mode, specify one of three types of specification methods: register-based multi-stage indirect mode, PC-based multi-stage indirect mode, and absolute-based multi-stage indirect mode in the basic addressing mode I specification field. do.

The register-based multi-stage indirect mode is an addressing mode in which the value of a register is used as the base value for multi-stage indirect addressing to be expanded. A schematic diagram of the format is shown in FIG. 21, where Rn indicates the number of the general-purpose register.

The PC-based multi-stage indirect mode is an addressing mode in which the value of the program counter is used as the base value for multi-stage indirect addressing. The second schematic diagram of the format
Shown in Figure 2.

The absolute base multi-stage indirect mode is an addressing mode that uses zero as the base value of extended multi-stage indirect addressing. A schematic diagram of the format is shown in FIG.

The multi-stage indirect mode specification field to be expanded has a unit of 16 bits, and this is repeated any number of times.

One-stage multi-stage indirect mode allows displacement addition and index register scaling (XI,
2. X4. X8) and performs indirect reference to memory. A schematic diagram of the format of the multi-stage indirect mode is shown in FIG. Each field has the meaning shown below.

E=0: Continuation of multi-stage indirect mode E・1 Near address calculation end tmp ==> address of opera
nd■・0: No memory indirect reference tmp + disp + Rx * 5cale =
=> tmpI・1: With memory indirect reference nelltmp + disp + RX * 5ca
le ==>tmpM=0: Use <RX> as index M, 1: Special index <Rx>=O Do not add index value (Rx=0) <Rx>= 1 Use program counter as index value ( Rx=PC) <Rx>=2~ reserved Port 20: 4-bit field d4 in the top 0 code of the multi-stage frontage
The value of is multiplied by 4 as a displacement value, and this is added. d4 is treated as signed and is always multiplied by 4 regardless of the size of the operand. 0, 1: Specified in the extension part of multi-stage indirect mode. d
The displacement value is 1spx (16/32 bits), and the size of the extension section to which this is added is specified in the d4 field. d4=0001 dispx is 16 bits d4=0
010 dispx is 32 bits×x; index scale (scale=1/2/4/8) X2. X4. When scaling by x8 is performed, an undefined value is entered as the intermediate value (tmp) after the processing of that stage is completed. Although the effective address obtained by this multi-stage indirect mode is an unpredictable value, no exceptions occur. Do not specify scaling for the program counter.

Variations of instruction formats in the multi-stage indirect mode are shown in FIGS. 25 and 26.

FIG. 25 shows variations on whether the multi-stage indirect mode continues or ends.

FIG. 26 shows variations in displacement size.

If a multi-stage indirect mode with an arbitrary number of stages can be used, there is no need for the compiler to differentiate between cases based on the number of stages, which has the advantage of reducing the burden on the compiler. Even if the frequency of multiple indirect references is very low, the compiler must always be able to generate correct code. Therefore, any number of stages is possible in the format.

(1, 5) r Exception Handling” The data processing device of the present invention has abundant exception handling functions to reduce the software load. In the data processing device of the present invention, exception handling is re-execution of instruction processing (exception).
They are divided into three types and named: , those that complete instruction processing (traps), and interrupts. Furthermore, in the data processing apparatus of the present invention, these three types of exception handling and system failure are collectively referred to as BIT.

(2) RA Functional Block Configuration” FIG. 1 is a block diagram showing the configuration of a data processing device of the present invention.

Functionally, the inside of the data processing device of the present invention can be roughly divided into an instruction fetch unit 101. Instruction decoding unit 102, P
C calculation section 103. Operand address calculation unit 104゜Micro ROM unit 105. Data calculation unit 106. It is divided into an external bus interface section 107.

In addition, in FIG. 1, an address output circuit 108 for outputting an address to the outside of the CPU, and a data input/output circuit 109 for inputting/outputting data to/from the outside of the CPU are shown separately from other functional blocks.

(2,1) r Instruction fetch unit The instruction fetch unit 101 includes a branch buffer, an instruction queue 301, its control unit, etc., and determines the address of the next instruction to be fetched and transfers it to the branch buffer or CP.
II Fetch instructions from external memory. It also registers instructions to the branch buffer.

Since the branch buffer is small, it operates as a selective cache. The details of the operation of the branch buffer are described in detail in Japanese Patent Application No. 61-202041.

The address of the next instruction to be fetched is stored in the instruction queue 30.
It is calculated by a dedicated counter as the address of the instruction to be input into the address number 1. When a branch or jump occurs, the address of a new instruction is transferred from the PC calculation unit 103 or the data calculation unit 106.

When fetching an instruction from a memory external to the CPU, the address of the instruction to be fetched is sent from the address output circuit 108 to the CPU via the external bus interface unit 107.
The instruction code is output from the U and fetched from the data input/output circuit 109. Then, among the buffered instruction codes, the instruction code to be decoded next is output to the instruction decoding unit 102.

(2, 2) r Instruction Decoding Unit” The instruction decoding unit 102 basically decodes instruction codes in units of 16 bits (halfwords). This block includes an FHW decoder that decodes the operation code contained in the first halfword, a second . It includes an NFll-decoder that decodes the operation code included in the third halfword, and an addressing mode decoder that decodes the addressing mode. These FHW decoder, NFll-decoder, and addressing mode decoder are collectively referred to as a first decoder 303.

A second decoder 305 further decodes the output of the FH-decoder or NFHW decoder to calculate the entry address of the micro ROM, a branch prediction mechanism that predicts branches of conditional branch instructions, and checks pipeline conflicts when calculating operand addresses. Also included is an address calculation conflict checking mechanism.

The instruction decode unit 102 converts the instruction code input from the instruction fetch unit 101 to 0 every 2 clocks (1 step).
~Decode 6 bytes at a time. Among the decoding results, information regarding the calculation in the data calculation unit 106 is stored in the micro ROM.
Information related to operand address calculation is outputted to section 105, and information related to PC calculation is outputted to operand address calculation section 104 and pc calculation section 103, respectively.

(2, 3) ``Micro ROM section'' The micro ROM section 105 mainly includes a data calculation section 106.
It includes a micro ROM, a micro sequencer, a micro instruction decoder, etc. in which a micro program for controlling the micro program is stored. Microinstructions are read from the micro ROM once every two clocks (one step). In addition to the sequence processing indicated by the microprogram, the microsequencer accepts processing of exceptions, interrupts, and traps (these three are collectively referred to as BIT) using hardware.

The micro 120M unit 105 also manages store buffers. The micro ROM unit 105 is manually supplied with flag information based on interrupts or arithmetic execution results that do not depend on instruction codes, and outputs from the instruction decoding unit such as the output from the second decoder 305. The output of the micro-decoder is mainly output to the data calculation unit 106, but some information, such as other preceding processing stop information due to execution of a jump instruction, is also output to other blocks.

(2, 4) r Operand Address Calculation Unit The operand address calculation unit 104 is hard-wired controlled by information related to operand address calculation output from the address decoder of the instruction decoding unit 102, etc. This block performs most of the processing related to operand address calculation. A check is also made to see if the address of the memory access for memory indirect addressing and the operand address fall within the l10Sff area mapped to memory.

The address calculation result is sent to the external path interface section 107.
sent to. The general purpose register and program counter values necessary for address calculation are input from the data calculation section.

When indirect memory addressing is performed, the address output circuit 108 outputs the memory address to be referenced to the outside of the CPU through the external bus interface section 107, and the indirect address value input manually from the data output section 109 is fetched through the instruction decoding section 102. .

(2, 5) rPC calculation unit” The PC calculation unit 103 is hard-wired controlled by information related to PC calculation output from the instruction decoding unit 102, and calculates the PC value of the instruction. The data processing device of the present invention has a variable length instruction set, and the length of the instruction cannot be determined unless the instruction is decoded. For this reason, PC
The calculation unit 103 creates the pc value of the next instruction by adding the instruction length output from the instruction decoding unit 102 to the pc value of the instruction being decoded. In addition, the instruction decoding unit 1
When 02 decodes a branch instruction and instructs a branch at the decoding stage, the pc value of the branch destination instruction is calculated by adding the branch displacement instead of the instruction length to the pc value of the branch instruction. In the data processing apparatus of the present invention, branching to a branch instruction at the instruction decoding stage is called a branch branch.

Regarding this Bribranch method, please refer to Japanese Patent Application No. 612045.
00 and Japanese Patent Application No. 61-200557.

The calculation result of the pc calculation unit 103 is output as the pc value of each instruction together with the instruction decoding result, and at the time of branching, it is output to the instruction fetch unit 101 as the address of the next instruction to be decoded. It is also used as an address for branch prediction of the next instruction to be decoded by the instruction decoding unit 102.

The branch prediction method is described in detail in Japanese Patent Application No. 8394/1983.

(2, 6) r Data Operation Unit The data operation unit 106 is controlled by a microprogram, and uses registers and arithmetic units to execute operations necessary to realize the function of each instruction according to the output information of the micro ROM unit 105. When the operand to be operated on is an address or an immediate value, the address or immediate value calculated by the operand address calculation unit 104 is passed through the external path ink face unit 107 and obtained. Furthermore, if the operand to be operated on is in the memory outside the CPt1, the path interface section outputs the address calculated by the address calculation section 104 from the address output circuit 108, and reads the quenched operand from the memory outside the CPU. It is obtained from the data input/output circuit 109.

Examples of arithmetic units include LIJ313, barrel shifter, priority encoder or counter, and shift register. The registers and the main arithmetic unit are connected by three paths, and one microinstruction instructing one register-to-register operation is processed in two clocks (l steps).

When it is necessary to access memory outside the CPU during data calculation, the address is output from the address output circuit 108 to the outside of the CPU through the external hash interface section 107 according to instructions from the microprogram, and the target data is output through the data input/output circuit 109. fetch

When storing data in a memory external to the CPU, an address is output from the address output circuit 108 through the external hash interface section 107, and at the same time, data is output from the data input/output circuit 109 to the outside of the CPU. In order to efficiently store operands, the data calculation unit 106
is equipped with a 4-byte store buffer.

When the data calculation unit 106 obtains a new instruction address by performing jump instruction processing or exception processing, it outputs this to the instruction fetch unit 101 and the pc calculation unit 103.

(Remainder 2 below; white) (2, 7) r External path interface unit The external path interface unit 107 controls communication on the external path of the data processing device of the present invention. All memory accesses are performed in clock synchronization, with a minimum of 2 clock cycles (1
This can be done in steps).

The instruction fetch unit 101 issues an access request to the memory.
Operand address calculation unit 104 and data calculation unit 10
arises independently from 6. External path interface section 10
7 arbitrates these memory access requests. Furthermore, when accessing data at a memory address that straddles a 32-bit (1 word) aligned boundary, which is the data bus size that connects the memory and the CPU, it is automatically detected within this block that it straddles a word boundary. This is done by breaking it down into multiple memory accesses.

It also performs conflict prevention processing when the pre-fetch operand and store operand overlap, and bypass processing from the store operand to the fetch operand.

(3) “Pipeline mechanism” The pipeline processing function of the data processing device of the present invention is
As schematically shown in the figure.

The instruction fetch stage (IF
Stage) 201. Decode stage (D stage) 202 for decoding instructions. Operand address calculation stage (to stage) that calculates the address of the operand
203. Micro ROM access (especially R stage 20
Operand fetch stage (F stage) 204 . A five-stage configuration of an execution stage (E stage) 205 for executing instructions is the basis of pipeline processing.

In addition to having a one-stage store buffer in the E stage 205,
Some of the high-performance instructions pipeline the instruction execution itself, so there is actually a pipeline processing effect of five or more stages.

Each stage operates independently of the other stages, and in theory the five stages operate completely independently.

Each stage can perform one process in a minimum of two clocks (one step). Therefore, ideally two clocks (
Pipeline processing progresses one after another for each step (1 step).

The data processing device of the present invention has some instructions that cannot be processed with just one basic pipeline process, such as memory-to-memory operations or memory indirect addressing, but the data processing device of the present invention can handle these processes. It is designed to perform pipeline processing as balanced as possible. An instruction having a plurality of memory operands is decomposed into a plurality of pipeline processing units (step codes) at the decoding stage based on the number of memory operands, and pipeline processing is performed.

Regarding the decomposition method of pipeline processing units, please refer to the patent application 1986.
It is described in detail in No.-236456.

The information passed from the IF stage 201 to the D stage 202 is the instruction code 211 itself. D stage 2
There are two types of information passed from 02 to the A stage 203: information related to the operation specified by the instruction (referred to as D code 212), and information related to operand address calculation (referred to as A code 213).

The information passed from the A stage 203 to the F stage 204 is an R code 214 that includes the microprogram entry address or microprogram parameters, and an F code 215 that includes the operand address and access method instruction information. .

The information passed from the F stage 204 to the E stage 205 is two types: an E code 216 including arithmetic control information and literals, and an S code 217 including operands or operand addresses.

A BIT detected at a stage other than the E stage 205 is a BIT until the code reaches the E stage 205.
Only instructions processed in the E stage 205 that do not start processing are instructions in the execution stage, and are not executed in the IF stage 201.
This is because the instructions being processed between F stage 204 and F stage 204 have not yet reached the execution stage. Therefore, when an EIT is detected at a stage other than the E stage 205, the fact that it has been detected is recorded in the step code and only transmitted to the next stage.

(3,1) r vibe line processing unit" (3,1,1) r instruction code field classification" The pipeline processing unit of the data processing device of the present invention is determined using the characteristics of the format of the instruction set. There is.

As described in section (1), the instructions of the data processing device of the present invention are variable length instructions in 2-byte units, and basically the "2-byte basic instruction part + 0 to 4-byte addressing extension part" is divided into 1 An instruction is constructed by repeating ~3 times.

The instruction basic part often has an operation code part and an addressing mode specification part, and if index addressing or memory indirect addressing is required, a "2-byte multi-stage indirect mode specification part" is used instead of the addressing extension part. ~4 Hyde's Atranging Extension” is optionally available. Also, depending on the command, 2 or 4
An instruction-specific extension of bytes is appended at the end.

The instruction basic part includes the instruction operation code, basic addressing mode, literal, etc. Addressing extensions include displacement, absolute address,
Either an immediate value or a displacement of a branch instruction. Instruction-specific extensions include a register map, immediate value specification for the I-forn+at instruction, and the like. FIG. 27 is a schematic diagram showing the characteristics of the basic instruction format of the data processing device of the present invention.

(3, 1, 2) Decomposition of instructions into r-step codes The data processing device of the present invention performs pipeline processing that takes advantage of the characteristics of the instruction format described above.

In the D stage 202, “2 Hyde’s instruction basic part +0 to 4
"byte addressing extension", "multi-stage indirect mode specification part addressing extension", or instruction-specific extension are processed as one decoding unit.The decoding result of each time is called a step code, and from the A stage 203 onwards, this step Code is the unit of pipeline processing.The number of step codes is unique for each instruction, and if multi-stage indirect mode is not specified, one instruction is divided into a minimum of 1 step code and a maximum of 3 step codes.Multi-stage When the indirect mode is designated, the step code increases accordingly.However, as will be described later, this only occurs at the decoding stage.

(3, 1, 3) ``Program counter management'' It is possible that all the step codes existing on the pipeline of the data processing device of the present invention are for different instructions,
Therefore, the value of the program counter is managed for each step coat. Every step code has the program counter value of the instruction that the step code is based on. The program counter value that accompanies the step code and flows through each stage of the pipeline is referred to as the step program counter (SPC). The SPC is passed between pipeline stages one after another.

(3, 2) Processing of Each Vibration Line Stage The input and output step codes of each pipeline stage are named for convenience as shown in FIG. Further, the step code performs processing related to the operation code, and there are two series: a series that becomes the entry address of the microprogram and parameters for the E stage 205, and a series that becomes the operand for the microinstruction of the E stage 205.

(3, 2, 1) r instruction fetch stage The instruction fetch stage (IF stage) 201 fetches instructions from memory or branch buffer and stores them in the instruction queue 30.
1 and outputs the instruction code to the D stage 202. The manual operation of the instruction queue 301 is performed in aligned 4-byte units. When fetching instructions from memory, a minimum of 2 clocks (1 step) per 4 aligned bytes
It takes.

If the branch buffer is hit, it can be fetched in 1 clock per aligned 4 bytes. The output unit of the instruction queue 301 is variable every 2 bytes, and up to 6 bytes can be output during 2 clocks. Immediately after a branch, the instruction queue 301 is bypassed and the instruction basic unit 2
It is also possible to transfer the bytes directly to the instruction decoder.

Control of registering and clearing instructions in the branch buffer,
Management of the address of the instruction to be fetched and instruction queue 3
01 is also controlled by the IF stage 201.

EITs detected at the IF stage 201 include bus access exceptions when fetching instructions from memory, address translation exceptions due to memory protection violations, and the like.

(3, 2, 2) r instruction decode stage” The instruction decode stage (D stage) 202 is the IF stage 201
Decodes the instruction code input from. Decoding is performed by the FHW decoder of the instruction decoding unit 102, NFI
Using the first decoder 303, which is a combination of a W decoder and an addressing mode decoder, decoding is performed once every two clocks (one step), and in one decoding process, 0 to
A 6-byte instruction code is consumed (the instruction code is not consumed in output processing of a step code including the return destination address of the R[iT instruction, etc.). A code 21 as address calculation information for A stage 203 with one decoding
3, the control code and address modification information, and the D code 212 as the intermediate decoding result of the operation code.
A control code and 8-bit literal information are output.

The D stage 202 also performs control of the PC calculation unit 103 for each instruction, branch prediction processing, branch processing for a branch instruction, and instruction code output processing from the instruction queue 301.

The BITs detected in the D stage 202 include reserved instruction exceptions and odd address jump traps during branching. Further, various BITs transferred from the IF stage 201 are encoded into step codes and transferred to the A stage 203.

(3, 2, 3) r operand address calculation stage”
Operand address calculation stage (to stage) 203
The processing functions are broadly divided into two. One is a process in which the second decoder 305 of the instruction decoding unit 102 is used to decode the operation code at a later stage, and the other is a process in which the operand address calculation unit 104 calculates an operand address.

The subsequent decoding process of the operation code is D code 2.
12 as an input, and outputs an R code 214 including register and memory write reservations, microprogram entry addresses, parameters for the microprogram, and the like. Note that the register or memory write reservation is intended to prevent incorrect address calculation from being performed due to the contents of the register or memory referenced in address calculation being rewritten by a preceding instruction on the pipeline. Register or memory write reservations are made for each instruction, not for each step code, to avoid deadlock. The reservation of writing to registers and memory is described in detail in Japanese Patent Application No. 144394/1983.

The operand address calculation process takes the A code 213 as input, and operates the operand address calculation unit 1 according to the A code 213.
Address calculation is performed in combination with addition or memory indirect reference in step 04, and the calculation result is output as F code 215. At this time, a comma lift check is performed when reading registers and memory during address calculation, and if a conflict is indicated because the preceding instruction has not finished writing to the register or memory, the preceding instruction performs the writing process at E stage 205. Wait until it finishes. It also checks whether the operand address and the memory indirect reference address fall within the 1108N area mapped to memory.

The BIT detected in the A stage 203 includes a reserved instruction exception,
privileged instruction exception, bus access exception, address translation exception,
There is a debug trap due to an operand breakpoint hit during memory indirect addressing. If the D code 212 or A code 213 itself indicates that an EIT has occurred, the A stage 203 does not perform address calculation processing on that code, and transfers the BIT to the R code 21.
4 and F code 215.

(3, 2, 4) r Micro ROM access stage
The operand fetch stage (F stage) 204 is also roughly divided into two processes. One is access processing of the micro ROM, and is particularly referred to as the R stage 206. The other is operand prefetch processing, particularly referred to as OF stage 207. The R stage 206 and the OF stage 207 do not necessarily operate simultaneously, but operate independently depending on whether memory access rights can be acquired or not.

Micro ROM access processing, which is the processing of the R stage 206, is performed on the R code 214 at the next E stage 205.
E code 21 which is the execution control code used for execution in
This is micro ROM access and micro instruction decoding processing to generate 6. When processing for one R code 214 is broken down into two or more microprogram steps, the micro ROM is used in the E stage 205 and the next R code 214 waits for micro ROM access. The micro ROM access to the R code 214 is performed at the time of execution of the last micro instruction in the previous E stage 205. In the data processing device of the present invention, most basic instructions are executed in one microprogram step, so in reality, microRO)1 accesses to the R code 214 are often executed one after another.

There is no new EIT detected in the R stage 206.

When the R code 214 indicates an instruction processing re-execution type EXT, the microprogram for that BIT processing is executed, so the R stage 206 executes the R code 21.
Fetch the microinstruction according to 4.

If R code 214 indicates an odd address jump trap, R stage 206 sends it to E code 216.
convey by. This is for Bribranch,
In the E stage 205, if a branch does not occur in the E code 216, the pre-branch is made valid and an odd address jump trap is generated.

(3, 2, 5) r Operand Fetch Stage The operand fetch stage (OF stage) 207 performs operand prefetch processing of the above two processes performed in the F stage 204.

Operand brief fetch is done manually using F code 215.
The fetched operand and its address are sent to S code 21.
Output as 7. One F code 215 specifies operand fetch of 4 bytes or less, although it may span word boundaries. The F code 215 also includes a designation as to whether or not to access the operand, and the A stage 203
When transferring the operand address itself or the immediate value calculated in , to the E stage 205, operand prefetch is not performed, and the contents of the F code 215 are transferred as the S code 217. If the operand to be pre-fetched matches the operand to be written by the E stage 205, the operand pre-fetch is not performed from memory but is bypassed. Further, for the [10 area], operand prefetch is delayed, and operand fetch is performed after waiting until all preceding instructions are completed.

BITs detected in the leaf stage 207 include bus access exceptions, address translation exceptions, and debug traps based on breakpoint hints for operand prefetch. F code 215 is BI other than debug trap
When it shows T, transfer it to S code 217,
Operand prefetch is not performed. When F code 215 indicates a debug trap, the F code 21
5, performs the same processing as when no BIT is indicated, and also transmits a debug trap to the S code 217.

(3, 2, 6) r Execution Stage” The execution stage (E stage) 205 operates with the E code 216 and the S code 217 as input. This E stage 205 is a stage for executing instructions, and all processing performed in stages before the F stage 204 is preprocessing for the E stage 205. When a jump instruction is executed or BIT processing is started at E stage 205, all processing from IF stage 201 to F stage 204 is invalidated. E stage 20
5 is controlled by a microprogram, R code 21
The instructions are executed by executing a series of microprograms starting from the microprogram entry address shown in 4.

Micro RO? + reading and microinstruction execution are performed in a pipelined manner. Therefore, when a branch occurs in a microprogram, one microstep becomes available. In addition, the E stage 205 includes the data calculation section 10
Using the store buffer in 6, it is also possible to perform pipeline processing for storing operands within 4 bytes and executing the next microinstruction.

In the E stage 205, the write reservation for registers and memory made in the A stage 203 is canceled after the operand is written.

Further, if a conditional branch instruction issues a branch at the E stage 205, the branch prediction for that conditional branch instruction was incorrect, so the branch history is rewritten.

BITs detected in the E stage 205 include bus access exceptions, address translation exceptions, debug traps, odd address jump traps, reserved function exceptions, illegal operand exceptions, reserved stack format exceptions, divide-by-zero traps, unconditional traps, and conditional traps. There are , delayed context traps, external interrupts, delayed interrupts, reset interrupts, and system failures.

All BITs detected at E stage 205 are processed, but BITs from IF stage 201 before E stage
EIT detected during stage 204 and reflected in R code 214 or S code 217 is not necessarily B.
It does not necessarily have to be processed by IT. It was detected between IF stage 201 and F stage 204, but the preceding instruction was
All EITs that have not reached E stage 205 due to a jump instruction being executed at stage 205 or the like are cancelled. This means that the instruction that caused the BIT was never executed in the first place.

External interrupts and delayed interrupts are processed at E stage 20 at the end of instructions.
5, the bones are directly attached, and the necessary processing is executed by a microprogram. Other various BIT processes are performed by microprograms.

(3, 3) rState control of each pipeline stage Each stage of the pipeline has an input latch and an output latch, and basically operates independently of other stages. At each stage, when the previous processing is completed, the processing result is transferred from the output latches to the input latches of the next stage, and when all the human input signals necessary for the next processing are available in the input latches of the stage, the next stage is started. start processing.

In other words, in each stage, all input signals for the next process output from the previous stage are valid, the current processing result is transferred to the input latch of the next stage, and when the output latch becomes empty, the next process starts. Start.

All input signals must be available at the clock timing immediately before each stage starts operating. If the human power signals are not available, the stage is in a waiting state (waiting for human power). When transferring from the output latch to the next stage's manual latch, the input latch of the next stage must be free, and even if the input latch of the next stage is not free, the pipeline stage will wait. state (waiting for output). If a necessary memory access right cannot be acquired, a wait is inserted into the memory access being processed, or other pipeline conflicts occur, the processing itself at each stage will be delayed.

(3, 4) Operation of stack pointer FIG. 28 is a block diagram showing an embodiment of the present invention. Reference numeral 61 is a working stage stack pointer ASP of the operand address calculation stage (A stage 203), which indicates the value of the stack pointer associated with the instruction being executed in the A stage 203. 63 is a working stage stack pointer (FSP) of the operand fetch stage (F stage 204), and 65 is a working stage stack pointer C3P of the execution stage (E stage 205). 66 is a group of stack pointers at the software level (there are multiple stack pointers due to rings, interrupts, etc.), 64 is an ASP output latch, and 65 is an F
SII output latches and ASP61. FSP
This is a latch that holds 63 output data.

72 is an address register (AA register) of the E stage 205; 73 is a data register (DD register) of the E stage 205 for data exchanged with the outside;
75 is an address addition section of the A stage 203, and 8087 is an internal data calculation section. 106 is a data calculation unit of the E stage 205, and 90a to 90e are A stages of the A stage 203.
This is an ASP update signal indicating that SP61 has been updated. 91 is an ASP increment signal in the A code 213, and 92 is an ASP decrement signal in the A code 213. 611, 621, 631, 641 are respectively ASP6
1, to sp output latch 62, FSP63, a latch that transfers the ASP update signal 90a as part of the FSP output latch 64.

FIGS. 29 and 30 are diagrams showing processing regarding the stack pointer at each stage of several instructions executed in the data processing device of the present invention. (a) is A stage 203, (f) is F stage 204,
(e) shows the processing of the E stage 205.

FIGS. 31 and 32 are diagrams showing pipeline processing when the step code following the instruction in FIG. 30 refers to the stack pointer and when it does not. ■ is the step code for the instruction to transfer "100" to the stack pointer, ■ is the step code processed next to ■, ■ is the step code processed next to ■, (a) is the A stage 203, (f ) is F stage 204, (
e) shows stack pointer processing in the E stage 205, and the horizontal axis shows the passage of time.

Next, processing regarding the stack pointer will be explained using FIG. 28. A code 213 contains ^5l)61
An increment signal 91 and a decrement signal 92 are included, and these signals 91 and 92 control the ASP 61. Further, the ASP update signal 90 is generated by ORing the increment signal 91 and the decrement signal 92.

The increment signal 91 or decrement signal 92 is
1", that is, when the ASP 61 is updated in the A stage 203, the ASP update signal 90a becomes "1".

The ASP update signal 90a is transferred together with the value of the stack pointer in synchronization with the flow of step codes in the pipeline. In the E stage 205, the C5P65 is used only when the transferred ASP update signal 90e is "L".
Transfer the FSP63 value to.

Instructions that include operand specifications for stack addressing mode, such as the NOV instruction (MOV: Rn ->
FIG. 29 shows the processing regarding the stack pointer at each stage when 2-3P Rn represents the nth register and a-sp represents the address pointed to by the value obtained by decrementing the stack pointer. First, D stage 2
02 generates A code 213 including ASP610 update control and the like.

In the A stage 203, R code 2 including register specification
Outputs 14. Also, based on A code 213, 85
P61 is decremented by the size of the operand, and the updated value is transferred to FSP63. At this time A stage 2
At 03, the ASP update signal 90a indicating that the ASP61 has been updated becomes "1", and this signal is transferred together with the value of the ASP61. If the value of the ASP 61 cannot be transferred immediately because the F stage 204 is processing the previous step code, the ASP output latch 62 waits until the value can be transferred. In the data processing device of the present invention, in order to commonize processing between the stack push addressing mode and other addressing modes, in addition to decrementing the ASP 61, the address addition unit 75 also performs (ASP
O value - operand size) and transfers the result to the F stage 204 as an operand address.

In the F stage 204, an E code 216 containing a register access signal is generated from the R code 214, and an S code 21 containing this E code 216 and the value of the operand address is generated.
7 is transferred to the E stage 205. It also detects that the ^SP update signal 90e is "1', and transfers the value of the FSP 63 to the CSI" 65. Similarly to the above, if the data cannot be transferred to the C5P65 immediately, the FSP output latch 64 waits until the data can be transferred.

In the E stage 205, the value of the designated register is read out and sent to the DO from the data calculation unit 106 via the DO bus 5.
Write to register 73. The operand address transferred from the F stage 204 is written into the AA register 72. At the end of this instruction, the value of C3P65 is transferred to one of the stack pointer group 66 seen from the software, and the value of the stack pointer after execution of the instruction is set correctly from the outside. D to the address indicated by the static register 72.
Store the value of O register 73.

When this instruction finishes processing in the A stage 203, the value of the stack pointer at the end of this instruction is ASP61.
Therefore, even if a later instruction includes an addressing mode that refers to the stack pointer, the AS
By referring to the value of P61, the correct address can be obtained.

Next, for example, an instruction to write 100" to the stack pointer (MOVE"100'->SP '100' is an immediate value,
FIG. 30 shows processing related to the stack pointer (sp is the stack pointer).

In this instruction, when processing in A stage 203, go to 5P6
1 (Direct does not change. This ASP61 in i'5P63
The value of is transferred. In addition, a stack pointer write reservation is made to indicate that the value of the stack pointer will be rewritten in the E stage 205 so that a later instruction does not refer to an incorrect value when referencing the stack pointer. At this time, the HESP update signal 90a is 110#.

The F stage 204 outputs an E code 216 including stack pointer write control and the like, and an S code 217 including immediate value data "100". At this time, the ASP update signal 90e is "0", so I? The value of S P 63 is C3P
65 is not written to.

The E stage 205 reads immediate value data "100" based on the E code 216, and the data calculation unit 106, DO
Transfer to ^5P61 and C3P65 through path 85.

Then, at the end of the instruction, the value of C3P65 is transferred to sp group 66.

FIG. 31 shows a case where the step code after this instruction uses a stack pointer when calculating an address. At this time, the next step code ■ is reserved for writing the stack pointer in the step code ■, so the step code ■ is processed at the E stage 205, a value is written to the stack pointer, and the stack pointer write reservation is released. Until this happens, the process is suspended at the A stage 203 and waits. And the step coat is E
After the process at stage 205 is performed and the ASP61 is rewritten, the process at stage A 203 of step code ■ is started. In step code ■, change the value of FSP63 to C3P
Transfer to 65.

On the other hand, FIG. 32 shows a case where the subsequent step code does not refer to the stack pointer. This poet's step code ■ does not refer to stackbo ink, so there is no need to wait at A stage 203, and the step code ■ does not refer to stackbo ink.
A stage 20 occurs when the processing at stage 203 is completed.
Start the process in step 3.

Regarding this step code (3), the value of ASP61 is different from the value of the stack pointer that should originally accompany the execution of the instruction. However, in step code ■, the ASP update signal is "0", and the value of FSP63 is not written to C3P65. Therefore, when step code ■ is processed in the E stage 205, the correct stack pointer value (the value written to C3P65 in step code ■) is stored in C5P65. Then, at the end of the instruction, the value of C5P65 is written to the stack pointer 66 seen from the software.

Furthermore, if the step code ■ also does not use the stack pointer, the processing at the A stage 203 is started when the step code ■ finishes the processing at the A stage 203. In the step code ■, the ASP update signal 90 is "0" like ■, and no value is transferred from the FSP 63 to the C3P 65.

In this way, when each step code updates the value of the stack pointer in the A stage 203, the A stage 2
When the process ends in step 03, the value of the stack pointer at the end of this instruction has been written to the ASP61. Therefore, when the step code of a later instruction refers to the stack pointer in the A stage 203, the correct address can be obtained by referencing ^5P61. For example, the atregistration mode of the next instruction is (SP + di
sp), by executing (8sp+disp) in the address adder 75, the correct address can be obtained without waiting for the completion of the previous instruction.

Furthermore, when updating the value of the stack pointer in the process of the E stage 205, a stack pointer write reservation is made. If the next step code refers to the stack pointer at the A stage 203, processing of the next step code waits until the stack pointer write reservation is released at the A stage 203. On the other hand, if the next step code does not refer to the stack pointer, there is no need to wait at the A stage 203, and the processing at each stage is performed, and when the step code is sent to the E stage 205, it is transferred from the FSP 63 to the C3P 65. Prevent stack pointer value transfer. Thus C5P65
The value of the stack pointer 66 seen from the software, which is transferred at the end of the instruction, maintains the correct value.

〔Effect of the invention〕

As described above, according to the present invention, the address calculation stage has a stack pointer, and the address calculation stage updates the stack pointer managed by the address calculation stage to transfer a value to the stack pointer managed by the execution stage. By controlling based on whether or not the command is active, it is possible to execute instructions quickly and accurately using less hardware.

[Brief explanation of the drawing]

FIG. 1 is an overall block diagram of a data processing device according to an embodiment of the present invention, FIG. 2 is a schematic diagram of a pipeline of a data processing device according to an embodiment of the present invention, and FIGS. FIG. 28 is a diagram showing the characteristics of the instruction format of a data processing device according to an embodiment of the present invention. FIG. 28 is a configuration diagram of a stack pointer-related portion of a data processing device according to an embodiment of the present invention. FIGS. Execution flowchart of several instructions executed in data processing device, No. 31
figure. FIG. 32 is an execution flowchart including the next step code of the instruction shown in FIG. 30, FIG. 33 is a block diagram showing a conventional example, and FIGS. 34 and 35 are execution flowcharts of a conventional bush instruction. 203... Address calculation stage (A stage) 20
5... Execution stage (E stage) 212-217.
・Step code which is the unit of pipeline processing
61... Working stage stack pointer (ASP) of A stage 203 63... E stage 205
Working stage stack pointer (C5P) 75...
-Address addition unit 90 of A stage 203...^sp update signal indicating that ASP is updated in A stage 203 Note that the same reference numerals in the figure do not indicate the same or equivalent parts. Bit number through agent Masuo Oiwa><Bit number for each byte><Address> ← Low address ← MSB system high address → LSB side → → → Direction of instruction → → Figure BYTE: BYTE: BYTE: N+2- 1 N+2-1 Figure BYTE: N+2-1 BYTE; N+2 N+2+M-1 Figure BYTE: N+2-1 BYTE : N+2-1 BYTE: N+2 N+2+1 N+2+2 N+20M+2-1 Figure BYTE: N+2-1 BYTE: N+4-1 Figure BY T.E. : N+2-1 BYTE: N+2 N+2+1 N+2+2 -------- N+2+M+2-1 Figure BYTE: Figure Figure Figure (Sh) (Ea) ■= E Eco Figure (Sh) (Ea) F Box "Eco Figure Figure Figures, figures, figures, figures (2 bytes) (0 to 4 bytes) Illustration procedure correction book (voluntary) Showa 6% 11 layers, 8

Claims (1)

[Claims] 1. An addressing mode is provided for specifying an operand of an instruction using a stack pointer and at the same time specifying an update method for the stack pointer, and instruction processing is performed by pipeline processing in the first stage and the second stage. A data processing device that performs sequential processing, comprising: a first stack pointer that can be referenced in the first stage; a second stack pointer that can be referenced in the second stage; and a second stack pointer that can be referenced in the second stage; a first updating means for updating the first stack pointer; a second updating means controlled by the second stage and updating the first stack pointer; controlled by the second stage; third updating means for updating the second stack pointer, and updating the first stack pointer in synchronization with instruction processing by pipeline processing only when the first stack pointer is updated by the first updating means A data processing device comprising: transfer means for transferring a value of a stack pointer to the second stack pointer.