JPH02256030A - Production of matrix type display device - Google Patents
Production of matrix type display deviceInfo
- Publication number
- JPH02256030A JPH02256030A JP1079252A JP7925289A JPH02256030A JP H02256030 A JPH02256030 A JP H02256030A JP 1079252 A JP1079252 A JP 1079252A JP 7925289 A JP7925289 A JP 7925289A JP H02256030 A JPH02256030 A JP H02256030A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- matrix array
- display device
- static electricity
- matrix
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011159 matrix material Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 238000000034 method Methods 0.000 claims abstract description 23
- 239000000463 material Substances 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 26
- 230000005611 electricity Effects 0.000 abstract description 18
- 230000003068 static effect Effects 0.000 abstract description 18
- 239000011521 glass Substances 0.000 abstract description 6
- 239000010409 thin film Substances 0.000 abstract description 6
- 230000002093 peripheral effect Effects 0.000 abstract description 5
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 230000006378 damage Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000012769 display material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明はマトリクス型表示装置の製造方法に関し、特
にマトリクスアレイ基板の形成方法に関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a matrix type display device, and particularly to a method for forming a matrix array substrate.
従来のマトリクス表示装置は、−船釣にガラス等の透明
絶縁基板上に複数の行電極線と複数の列電極線とを交差
させて配設し、各々の行電極線と列電極線との交点にス
イッチング素子を設けてなる構造を有している。In a conventional matrix display device, a plurality of row electrode lines and a plurality of column electrode lines are arranged to cross each other on a transparent insulating substrate such as glass, and each row electrode line and column electrode line are connected to each other. It has a structure in which switching elements are provided at the intersections.
第3図はこのようなマトリクス表示装置の一例を示して
おり、図において、b、−b、は行電極線(ゲート電極
線)、a、〜asは列電極線(ソース電極線)であり、
CI+C!+ ・・・は各々の電極配線の交点に接続さ
れたスイッチング素子である。液晶表示装置はこのよう
な配線構造を少なくとも絶縁性基板、及び透明導電膜を
有する対向電極基板の一方に構成し、他方の基板との間
に液晶等の表示材料を挟持させることにより構成してい
る。FIG. 3 shows an example of such a matrix display device. In the figure, b and -b are row electrode lines (gate electrode lines), and a and ~as are column electrode lines (source electrode lines). ,
CI+C! +... is a switching element connected to the intersection of each electrode wiring. A liquid crystal display device is constructed by configuring such a wiring structure on at least one of an insulating substrate and a counter electrode substrate having a transparent conductive film, and sandwiching a display material such as liquid crystal between the two substrates and the other substrate. There is.
上記スイッチング素子CI+C!+ ・・・として、少
なくとも1ケの薄膜トランジスタ(以下、TPTと略す
)等の非線形素子を用いた場合、第4図に示すように各
電極線が互いに独立しているため、TFTおよびTFT
のドレイン電極に接続された透明電極及び上記配線から
なるTFTアレイ基板は静電気による絶縁破壊等をひき
起こしやすい。The above switching element CI+C! +... When using a nonlinear element such as at least one thin film transistor (hereinafter abbreviated as TPT), each electrode line is independent of each other as shown in FIG.
A TFT array substrate consisting of the transparent electrode connected to the drain electrode and the above-mentioned wiring is likely to cause dielectric breakdown due to static electricity.
このため、従来においては静電気による素子破壊の対策
として、各配線間を短絡することにより、各配線を同電
位に保ち、アレイ基板が静電気にさらされても影響を受
けないような構造がとられている。For this reason, in the past, as a countermeasure against element destruction due to static electricity, a structure was adopted in which each wiring was kept at the same potential by shorting each wiring, so that even if the array substrate was exposed to static electricity, it would not be affected. ing.
第2図は例えば特開昭58−116573号公報に示さ
れた従来の行電極線及び列電極線を短絡する方法を示す
マトリクスアレイ基板の構成例を示したものである。図
において、a1〜a6は列電極線、b1〜b、は行電極
線であって、CI+C!+・・・は各電極線の交差点に
設けたスイッチング素子である。ここで、列電極線a、
〜a6は図に示すようにすべて短絡線A及びDにより短
絡されており、また行電極線す、−b、も全での短絡線
B及びCにおいて短絡されている。さらに短絡線A−D
の相互間、つまり図中破線で示すようにA−B間を配線
E、A−C間を配線F、B−D間を配線H1C−D間を
配線Gでそれぞれ接続すると、すべての電極線は短絡状
態になり、マトリクスアレイ基板が静電気にさらされて
も、マトリクスアレイ基板内はいたる所で同電位である
ので、スイッチング素子CI+C!+ ・・・は静電気
により破壊されることはない。FIG. 2 shows an example of the structure of a matrix array substrate showing a conventional method of short-circuiting row electrode lines and column electrode lines, as disclosed in, for example, Japanese Patent Laid-Open No. 58-116573. In the figure, a1 to a6 are column electrode lines, b1 to b are row electrode lines, and CI+C! +... is a switching element provided at the intersection of each electrode line. Here, column electrode line a,
-a6 are all short-circuited by short-circuit lines A and D as shown in the figure, and row electrode lines S and -b are also short-circuited by short-circuit lines B and C. Furthermore, short circuit wire A-D
In other words, as shown by the broken lines in the figure, if A-B is connected by wire E, A-C is connected by wire F, B-D is connected by wire H1, and C-D is connected by wire G, all electrode wires Even if the matrix array substrate becomes short-circuited and is exposed to static electricity, the potential is the same everywhere within the matrix array substrate, so the switching elements CI+C! +... will not be destroyed by static electricity.
従来のマトリクス型表示装置では以上のような方法によ
り静電気からスイッチング素子等を保護しているので、
短絡線を形成する製造工程前での基板帯電及びそれによ
る静電気障害は防ぎようがなく、また短絡線を形成した
後の工程において帯電した場合、短絡線により各配線間
が同電位になるだけで、周辺部等の表示機能に関係しな
い部分は絶縁性基板が表面に露出したままであるため、
プレイ基板全体としては帯電しやすい状態であることに
は変わりがない。従って特に基板の電位とは逆極性の静
電気等による高電位の短パルス電圧出している面積の大
きい部分の周辺部等において局所的な静電気障害が発生
しやすい等の問題があった。Conventional matrix display devices use the methods described above to protect switching elements from static electricity.
There is no way to prevent the board from being charged before the manufacturing process that forms the short-circuit line and static electricity damage caused by it, and if the board is charged during the process after the short-circuit line is formed, the short-circuit line will simply cause each wiring to have the same potential. , since the insulating substrate remains exposed on the surface in areas not related to the display function such as the peripheral area,
There is no change in the fact that the play board as a whole is easily charged. Therefore, there has been a problem in that local electrostatic damage is likely to occur, particularly in the periphery of a large-area portion where a high-potential short pulse voltage is generated due to static electricity having a polarity opposite to that of the substrate potential.
この発明は上記のような問題点を解消するためになされ
たもので、アレイ基板工程初期からマトリクス型表示装
置の製造工程の全体にわたり、基板自体の帯電を抑さえ
ることができ、しかも基板の接地が容易なマトリクス型
表示装置の製造方法を得ることを目的とする。This invention was made in order to solve the above-mentioned problems, and it is possible to suppress the charging of the substrate itself from the initial stage of the array substrate process to the entire manufacturing process of the matrix type display device, and also to prevent the substrate from grounding. An object of the present invention is to obtain a method for manufacturing a matrix type display device that is easy to manufacture.
この発明に係るマトリクス型表示装置の製造方法は、マ
トリクスアレイプロセス中の初期に機能素子や配線の形
成のために用いる導電膜を、基板の周辺部や基板内部の
基板露出部にも残こすようにしたものである。The method for manufacturing a matrix display device according to the present invention leaves the conductive film used for forming functional elements and wiring in the initial stage of the matrix array process on the periphery of the substrate and on the exposed substrate inside the substrate. This is what I did.
この発明においては、マトリクスアレイプロセス中の初
期に機能素子や配線の形成のために用いる導電膜を、基
板の周辺部や基板内部の基板露出部にも帯電防止膜とし
て残こすようにしたから、静電気が発生、帯電しやいす
ガラス基板上での静電気障害を無くすことができる。し
かも上記帯電防止膜は素子等の形成のための導電膜を利
用して形成しているため、プロセスが増加することはな
く、コストアップを招くことはない、さらに該帯電防止
膜はアレイ基板工程初期に作製されるため、マトリクス
型表示装置の製造プロセス全体にわたり基板帯電を抑制
して静電気障害を防ぐことができ、これにより装置の製
造歩留を著しく向上することができる。In this invention, the conductive film used for forming functional elements and wiring in the early stage of the matrix array process is left as an antistatic film on the periphery of the substrate and on the exposed parts of the substrate. It is possible to eliminate static electricity damage on the chair glass substrate, which generates static electricity and is easily charged. Moreover, since the above-mentioned antistatic film is formed using a conductive film for forming elements, etc., there is no increase in the number of processes and no increase in cost. Since it is manufactured at an early stage, it is possible to suppress substrate charging and prevent electrostatic damage throughout the manufacturing process of a matrix type display device, thereby making it possible to significantly improve the manufacturing yield of the device.
以下、本発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第1図は本発明の一実施例によるマトリクス型表示装置
の製造方法を説明するためのマトリクスアレイ基板構成
図であり、図において、1はガラス等の絶縁性基板、a
、〜a、及びす、〜b3はそれぞれ該基板1上に配設さ
れた列電極線及び行電極線であって、該列及び行電極線
の各交差点には薄膜トランジスタ等のスイッチング素子
C4〜c1を設けており、該素子近傍には該素子に接続
された素子電極rl+f!+ ・・・f、%を配設して
いる、ここでは上記薄膜トランジスタの活性層にはアモ
ルファスシリコン膜または多結晶シリコン膜等を用いて
おり、また上記スイッチング素子、電極線等により基板
1の画面表示部10が構成されている。FIG. 1 is a configuration diagram of a matrix array substrate for explaining a method of manufacturing a matrix type display device according to an embodiment of the present invention. In the figure, 1 is an insulating substrate such as glass;
, ~a, and ~b3 are column electrode lines and row electrode lines arranged on the substrate 1, respectively, and switching elements C4 to c1 such as thin film transistors are provided at each intersection of the column and row electrode lines. is provided near the element, and an element electrode rl+f! connected to the element is provided near the element. Here, an amorphous silicon film or a polycrystalline silicon film is used as the active layer of the thin film transistor, and the screen of the substrate 1 is provided with the switching elements, electrode wires, etc. A display section 10 is configured.
またdl+d!+ ・・・は画面表示用のスイッチング
素子と外部駆動回路とを接続するための接続用端子、2
はその一部が表示用薄膜トランジスタ。dl+d again! + ... is a connection terminal for connecting the switching element for screen display and an external drive circuit, 2
Some of these are thin film transistors for display purposes.
配線、引き出し配線部等に用いられるAIl、 Cr等
の金属膜で、表示機能上本来必要でない基板の周辺部に
も形成されている。e、、ex、・・・はスイッチング
素子と接続用端子との間の絶縁性基板が表面に露出する
部分に、端子配線を太線化して形成した引き出し配線部
である。ここでは列電極線a1〜a3+行電極線す、〜
b、は金属膜2により全て短絡されている。A metal film such as Al or Cr used for wiring, lead-out wiring parts, etc., and is also formed in peripheral areas of the substrate that are not originally necessary for the display function. e, , ex, . . . are lead-out wiring portions formed by thickening the terminal wiring in the portion where the insulating substrate between the switching element and the connection terminal is exposed on the surface. Here, column electrode lines a1 to a3 + row electrode lines, ~
b, are all short-circuited by the metal film 2.
次に製造方法について説明する。Next, the manufacturing method will be explained.
マトリクスアレイ基板作製プロセスにおいて、ガラス等
の絶縁性基板1上に薄膜トランジスタ等のスイッチング
素子、配線等に用いるAj!、 Cr等の導電膜、及
びSiN等の絶縁膜を順次形成してマトリクスアレイ基
板を製造する。In the process of manufacturing a matrix array substrate, Aj! , a conductive film such as Cr, and an insulating film such as SiN are sequentially formed to manufacture a matrix array substrate.
ここで配線等に用いる導電膜は表示機能上本来必要でな
い基板の周辺部、さらには画面表示部10と接続用端子
との間の、絶縁性基板が表面に露出する部分等にも残る
よう形成する。Here, the conductive film used for the wiring etc. is formed so as to remain on the periphery of the substrate which is not originally necessary for the display function, and also on the part where the insulating substrate is exposed to the surface between the screen display section 10 and the connection terminal. do.
このように本実施例では、マトリクスアレイプロセス中
の初期に形成される導電膜を表示機能上本来必要でない
基板の周辺部や、画面表示部と接続用端子との間の基板
露出部等にも残しているので、静電気の発生、帯電しや
すいガラス基板での静電気等による素子の破壊等を防止
できる。さらにこの帯電防止用の金属膜はマトリクスア
レイプロセスや液晶配向膜のラビング工程等のマトリク
ス型表示装置組立・実装プロセス中においても、マトリ
クスアレイ基板上に残っていて、該基板が帯電しにく(
なっているため、薄膜トランジスタや配線間等での静電
気障害の発生を防止しあるいは軽減することができる。In this way, in this embodiment, the conductive film formed at the beginning of the matrix array process is applied to the periphery of the substrate, which is not originally necessary for the display function, and to the exposed parts of the substrate between the screen display part and the connection terminals. This prevents generation of static electricity and destruction of elements due to static electricity on the glass substrate, which is easily charged. Furthermore, this antistatic metal film remains on the matrix array substrate even during matrix type display device assembly and mounting processes such as the matrix array process and the rubbing process of the liquid crystal alignment film, making it difficult for the substrate to be charged (
Therefore, it is possible to prevent or reduce the occurrence of electrostatic damage between thin film transistors, wiring, etc.
また上記帯電防止膜は配線等として用いる金属膜を利用
して形成しているため、プロセスを増加させることなく
形成することができ、コストアップを招くことはない。Further, since the antistatic film is formed using a metal film used as wiring, etc., it can be formed without increasing the number of processes, and does not result in an increase in cost.
また基板周辺部の大部分に導電膜が形成されているので
、マトリクス型表示装置の製造工程の全体にわたって接
地しやすい構造となっている。Further, since a conductive film is formed on most of the peripheral portion of the substrate, the structure is easy to ground throughout the manufacturing process of the matrix type display device.
以上のように、本発明に係るマトリクス型表示装置の製
造方法によれば、マトリクスアレイプロセス中の初期に
機能素子や配線の形成のために用いる導電膜を、基板の
周辺部や基板内部の基板露出部にも残こすようにしたの
で、静電気が発生。As described above, according to the method for manufacturing a matrix type display device according to the present invention, the conductive film used for forming functional elements and wiring in the initial stage of the matrix array process is applied to the periphery of the substrate or the inside of the substrate. Because it was left on exposed parts, static electricity was generated.
帯電しやすいガラス基板上での静電気障害を無くすこと
ができ、これによりマトリクスアレイ基板の素子歩留り
を向上して生産性を高め、製造コスト低減及び装置の信
鯨性の向上を図ることができる効果がある。It is possible to eliminate static electricity disturbances on glass substrates that are easily charged, thereby improving the element yield of matrix array substrates, increasing productivity, reducing manufacturing costs, and improving reliability of equipment. There is.
第1図はこの発明の一実施例によるマトリクス型表示装
置の製造方法を説明するための図、第2図は従来の静電
気対策を施したマトリクス型表示装置を示す図、第3図
は従来のマトリクス型表示装置を示す図である。
1は絶縁性基板、2は帯電防止膜、al+ a2+・
・・は列電極線、b、、b、、・・・は行電極線、CI
+’−R+ ・・・はスイッチング素子及び表示電極、
dI。
d!、・・・は接続用端子、el + ex + ・
・・e7は引き出し配線部、f+、fz、・・・f、は
表示電極である。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a diagram for explaining a method of manufacturing a matrix type display device according to an embodiment of the present invention, FIG. 2 is a diagram showing a matrix type display device with conventional static electricity countermeasures, and FIG. FIG. 1 is a diagram showing a matrix type display device. 1 is an insulating substrate, 2 is an antistatic film, al+ a2+・
... is a column electrode line, b,,b,,... is a row electrode line, CI
+'-R+ ... is a switching element and a display electrode,
dI. d! , ... are connection terminals, el + ex + ・
. . . e7 is an extraction wiring portion, f+, fz, . . . f is a display electrode. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
的に形成して、画面表示を行うための機能素子及び電極
配線を含む機能領域を形成し、さらに該絶縁性基板上に
表示材料を介して対向電極基板を配置してマトリクス型
表示装置を製造する方法において、 上記導電膜の選択的な形成の際、該導電膜を、上記機能
領域以外の、基板露出部分に帯電防止膜として残すよう
にしたことを特徴とするマトリクス型表示装置の製造方
法。(1) A conductive film and an insulating film are sequentially and selectively formed on a transparent insulating substrate to form a functional area including functional elements and electrode wiring for screen display, and further display is performed on the insulating substrate. In a method of manufacturing a matrix display device by arranging a counter electrode substrate through a material, when selectively forming the conductive film, the conductive film is applied to an exposed portion of the substrate other than the functional area as an antistatic film. A method for manufacturing a matrix type display device, characterized in that the matrix type display device is left as
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1079252A JPH02256030A (en) | 1989-03-29 | 1989-03-29 | Production of matrix type display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1079252A JPH02256030A (en) | 1989-03-29 | 1989-03-29 | Production of matrix type display device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02256030A true JPH02256030A (en) | 1990-10-16 |
Family
ID=13684662
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1079252A Pending JPH02256030A (en) | 1989-03-29 | 1989-03-29 | Production of matrix type display device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02256030A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105247317A (en) * | 2013-03-15 | 2016-01-13 | 博世汽车服务解决方案公司 | Combination gauge tool |
US9335593B2 (en) | 2013-01-22 | 2016-05-10 | Seiko Epson Corporation | Electro-optic device comprising a data line disposed between a transistor and a capacitor and electronic apparatus |
US9645458B2 (en) | 2013-01-22 | 2017-05-09 | Seiko Epson Corporation | Electrooptical device, method of manufacturing electrooptical device, and electronic apparatus |
-
1989
- 1989-03-29 JP JP1079252A patent/JPH02256030A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9335593B2 (en) | 2013-01-22 | 2016-05-10 | Seiko Epson Corporation | Electro-optic device comprising a data line disposed between a transistor and a capacitor and electronic apparatus |
US9645458B2 (en) | 2013-01-22 | 2017-05-09 | Seiko Epson Corporation | Electrooptical device, method of manufacturing electrooptical device, and electronic apparatus |
CN105247317A (en) * | 2013-03-15 | 2016-01-13 | 博世汽车服务解决方案公司 | Combination gauge tool |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3029531B2 (en) | Liquid crystal display | |
JP7356360B2 (en) | Array substrate and display device | |
US7724314B2 (en) | Method for repairing a short in a substrate for a display and display repaired according to that method | |
KR0160062B1 (en) | Array substrate for flat display device | |
US5504348A (en) | Thin-film transistor array and liquid crystal display device using the thin-film transistor array | |
EP2508943B1 (en) | Liquid crystal display device | |
JPH10288950A (en) | Liquid crystal display device | |
CN102473368A (en) | Active matrix substrate and active matrix display device | |
US6384878B1 (en) | Liquid crystal display having an electrostatic protection circuit | |
KR0151296B1 (en) | Lcd device with structure for preventing static electricity | |
JP2660528B2 (en) | Driving method of liquid crystal display device | |
JP2921864B2 (en) | Liquid crystal display | |
EP0504792B1 (en) | Liquid crystal display device | |
JP3491080B2 (en) | Matrix type array substrate for liquid crystal display device and manufacturing method thereof | |
JPH02256030A (en) | Production of matrix type display device | |
CN105676499A (en) | Liquid-crystal display panel and static electricity discharging circuit thereof | |
JPH06186592A (en) | Liquid crystal display device and its manufacture | |
JP4018913B2 (en) | Manufacturing method of liquid crystal display device | |
JP2746408B2 (en) | Matrix type display device | |
JPH028817A (en) | Manufacture of electric device | |
JPH09146112A (en) | Liquid crystal display element | |
JPH05232511A (en) | Manufacture of active matrix type liquid crystal display device | |
JP5121809B2 (en) | Display device substrate and liquid crystal display device using the same | |
JP3153369B2 (en) | Liquid crystal display device and driving method thereof | |
JPS59208877A (en) | Thin film device |