JPH02253769A - Synchronous detection window width set circuit - Google Patents

Abstract

PURPOSE:To improve the effect of noise reduction even to a signal from a TV camera, for which the timing of synchronization is out of specification, by writing optimum timing to open and close an window to a register to a synchronizing signal and executing the opening and closing of the window based on the data. CONSTITUTION:A counter CU2 of a time measuring circuit 2 counts a falling signal <C1> with a clock CLK as a basic clock. A counter CU1 executes count-up each time the falling signal <C1> falls. Then, an address signal ADD to a memory 3 is made. Data DA written to the memory 3 determine the timing to open and close the window by a microprocessor 4 and writes the timing to respective registers R1-R16. A decode circuit 6 compares outputs COUNT1 and COUNT2 of the counter to be obtained in a rising window generation circuit and a falling window generation circuit with the data from the respective registers. Then, window signals <W0>-<W4'> are generated to open and close the window.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a synchronization detection window width setting circuit applied to a synchronization signal reproducing device that reproduces a synchronization signal included in a video signal such as a television. More specifically, the present invention relates to a synchronization detection window width setting circuit that allows a synchronization signal reproducing circuit for reducing the influence of noise contained in synchronization signals to be applied to various TV right cameras or TVs.

<Prior art> The present applicant previously developed a synchronization signal regeneration circuit designed to reduce the influence of noise contained in synchronization signals in 1932.
The patent application was filed on October 20, 1982 as Japanese Patent Application No. 1983-264916.

FIG. 6 is a waveform diagram of this synchronizing signal, and FIG. 7 is a block diagram of its configuration.

In this circuit, as shown in FIG. 6, the period from the rising edge of the pulse to the rising edge of the synchronizing signal is ■, ■.

There are three types of ■, and the period from rise to fall is ■,■
There are five types: , ■, ■, and ■, and these periods are approximately fixed at 1°I according to the standard. Therefore, by detecting the falling or rising edge of synchronization, a window signal of an appropriate width is generated near the time elapsed between ■ and ■ or ■ and ■. Therefore, only the falling signal is regarded as a synchronization signal, and the rest are judged as noise.

In other words, this circuit uses the synchronizing signal <SYN>(<SYN> means the inversion of SYN) as shown in Figure 7.
A falling detection circuit DPC detects the falling edge of the synchronizing signal by applying a signal, a rising edge detecting circuit UPC detects the rising edge, and a known plurality of signals included in the synchronizing signal are synchronized with the output of the falling edge detecting circuit DPC. Synchronized with the output of the q rising window generation circuit UWC, which generates a rising edge window signal of a predetermined width every time the time elapses from the rising edge of F to the rising edge of A falling window generation circuit DWC that generates a falling window signal of a predetermined width every time the time from a plurality of known rising edges included in a signal to a falling edge F passes, and a falling detection circuit DP.
The rise detection circuit U is set to a predetermined level by the output of C.
Set/reset means SR, F1 .
．． It consists of SR and F2.

With this configuration, each window generation circuit UWC, D
By operating the rising or falling detection circuit only when there is a window signal from the WC and masking it at other times, it is possible to remove noise mixed in between the regular synchronous signals. .

<Problem to be solved by the invention> However, the synchronization signal ilTl regeneration with such a configuration is based on the assumption that the synchronization signal is generated according to the regular standard, and it is assumed that the synchronization signal is generated according to the standard. In order to satisfy the permissible width of the video signal and synchronization signal standards of the TV left camera, it is necessary to set the window width considerably wide, and in this case, the problem is that the noise removal effect is reduced. was there.

The present invention has been made in view of the above problems, and is applicable to video signals from a TV left camera, etc., where the timing of the state change of the synchronization signal (vertical, vertical or vertical) deviates from the standard. It is an object of the present invention to provide a synchronization detection window width setting circuit that makes it possible to apply the synchronization signal reproducing circuit configured as described above.

Means for Solving the Problems> FIG. 1 is a block diagram of the basic configuration of the present invention. In the figure, 1 inputs a composite synchronization signal <C-8YNC> and a clock signal CLK, detects a change in the state of the synchronization signal (rising or falling), and signals <CI> and <C
2> and a state change detection circuit that outputs a clear signal <CLR>; 2 inputs a signal C] which indicates the rise of the synchronization signal; and a signal C2 which indicates the rise and fall of the synchronization signal; From <C
This is the time full rotation for measuring the time up to 2>.

3 is a memory into which time data DA from the time measuring circuit 2 is written; 4 is a data reading means for reading out the data written in the memory 3; a microprocessor (CPU) is used for this.

5 is a register group that inputs the data read from the memory 3 and stores the timing of opening and closing the synchronization detection window; 6 is a decoding circuit that generates a window signal for opening and closing the window based on the data from the register group; 7
is a control circuit which inputs a control signal from the microprocessor 4 and controls the time measurement operation in the time measurement circuit 2 and the writing of data into the memory 3.

<Operation> The timing of each synchronization signal included in the composite synchronization signal is measured by a time measurement circuit and written to the memory. The timing data is read by the microprocessor, and the window opening/closing timing suitable for the synchronization signal is written into the register group. The decoding circuit creates a window signal for opening and closing the window based on the data from the register group.

<Example> Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, parts corresponding to those in FIG. 1 are designated by the same reference numerals.

The state change detection circuit 1 receives a composite synchronization signal <C-5YNC>
, a vertical synchronization signal <VD>, and a measurement mode designation signal UD/ that notifies a total of 1111 modes of whether to measure the time from rise to fall or the time from fall to rise of the composite synchronization signal. <DU> and a clock CLK for measuring time are input.

The time measurement circuit 2 includes a counter CU2 that counts and latches the time from <C1> to C2, and a register R.
EG, a counter CUI that generates an address ADD to the memory 3, and a D-flip-flop DFF that generates a write signal <WR> from <C2> and a clock CLK.

The memory 3 includes a memory 30 and a memory interface 31 that controls a bus when reading and writing data to this memory.

The decoding circuit 6 uses the data from each register of the register group 5 and the outputs C0UNT1 and C0UNT2 of the counters obtained in the qI: rewindow generating circuit UWC and standing window generating circuit DWC in the circuit of FIG.
Comparator group CMP 1 to CM that generates windows
P16 and a Nant gate NG that inputs signals from these comparators.

The control circuit 7 includes a comparator CMPO, a gate G1, an RS flip-flop R5FF, and a CPU interface IF that interfaces with the CPU, and includes enable signals <ENB> for the counters CUI and CU2 in the time measurement circuit 2; It is configured to generate a measurement end signal.

The operation of the apparatus configured as described above will be explained as follows.

3 to 5 are time charts for explaining the operation.

Here, to simplify the explanation, we will use the measurement mode designation signal UD / It is assumed that <DU> is at the rLJ level and is in a mode for measuring the time from falling to rising.

The state change detection circuit 1 detects the composite synchronization signal <C- shown in FIG. 3(b) at the rising edge of the clock signal CLK shown in FIG. 3(a).
9YNC> is detected, and a falling signal C1> is output as shown in (e), and when the rising edge is detected,
A rising signal <C2> is output as shown in (d).

As shown in (f), the counter CU2 of the time measuring circuit 2 uses the clock signal CLK as a basic clock, and starts counting from the time when the falling signal <C1> changes from the rLJ level to the rHJ level. This count value is latched in the register REG as shown in (g) when the rising signal <C2> reaches the rLJ level, and the output data DA is output from the flip-flop DFF (e
) At the timing of the write signal <WR> shown in
will be written to.

The counter CUI counts up every time the falling signal C1> rises and outputs the address signal A to the memory 3.
I'm making DD.

Here, the clear signal <CLR> of the counter CUI is (
The state change detection circuit 1 is configured to go low at the timing shown in b).

In the control circuit 7, the CPU interface IF is
2. Receive a control signal sent from the microprocessor 4; ill constant mode UD/<DU> signal,
Create a measurement start signal <S>, latch these,
A signal indicating the measurement mode UD/<DU> is sent to the state change detection circuit 1, and a measurement start signal <S> is applied to the gate G1 and the flip-flop R5FF.

In FIG. 5, (a) is this measurement start signal <S>
, and as shown here, <S> is, for example, 16
．． By keeping the level "L" for a period of 7 mS or more, the counter CU1. ．． CU2 is enabled. The comparator CMPO compares the count value ADD of the counter CUi with the set value C0N5T.
becomes larger than the set value C0N5T, the output <0
VER> is set to rLJ level as shown in (C), flip-flop R9FF is set and turned on, and each counter CU
The enable signal <ENB> to I and Cu2 is disabled as shown in (e), and the end of the measurement is notified to the CPU interface IF.

As a result, the value counted by the counter CU2 is latched into the register REG, and this data D (this data D corresponds to the timing of the synchronization signal) can be written to a predetermined address ADD of the memory 3. .

The data DA written in the memory 3 is read by the microprocessor 4, and based on this data, the timing for opening and closing the window is determined, and the timing is written to each register R1 to R16.

The decoding circuit 6 receives data from each register R1 to R16 and the rising window generation circuit T in the circuit shown in FIG.
JWC, the counter output C0UNTI obtained in the falling window generation circuit DWC.

Compare C0UNT2 and open/close a window appropriate for the synchronization signal.
4- Generate >.

<Effects of the Invention> As described above in detail, according to the present invention, the timing of the synchronization signal is written in the memory in advance, this data is read out, and the optimal window opening/closing timing for the synchronization signal is registered. Since the window is opened and closed based on that data, it is possible to improve the noise removal effect even for signals from TV cameras whose synchronization timing is out of the standard. becomes.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the basic configuration of the present invention, FIG. 2 is a block diagram of a configuration showing an embodiment of the present invention, FIGS. 3 to 5 are time charts for explaining the operation, and FIG. 6 is a block diagram of the basic configuration of the present invention. FIG. 7 is a waveform diagram of the synchronizing signal handled by the synchronizing signal reproducing circuit, and is a block diagram of its configuration. 1... State change detection circuit 2... Hour meter M) circuit 3
...Memory 4...Microprocessor 5...Register group 6...Decoding circuit 7.
・Control circuit

Claims (1)

[Claims] A state change detection circuit that inputs a composite synchronization signal and a clock signal, detects a state change (rising or falling) of the synchronization signal, and outputs a signal indicating the same and a clear signal; A time measurement circuit that inputs a signal indicating a falling edge and a signal indicating a rising edge and measures the time between both signals; A memory into which time data (DA) from the time measurement circuit is written; A microprocessor that reads the data read out from the memory, a register group that inputs the data read out from memory and stores the timing of opening and closing the synchronization detection window, and a window signal that opens and closes the window based on the data from the register group. 1. A synchronization detection window width setting circuit, comprising: a decoding circuit that generates a synchronization detection window, and a control circuit that receives a control signal from a microprocessor and controls a time measurement operation in a time measurement circuit and data writing to a memory.