JPH02253486A - Program table input/output circuit - Google Patents

Abstract

PURPOSE:To contrive the standardization of a program table input/output circuit by providing a command decoder, pipe line adjusting and delay circuit and a gate circuit and increasing a time table on an external part. CONSTITUTION:The program table input/output circuit is composed of program tables 1-4, selectors 7-11 for input switching, multiplexers 17-20, gates 12-16 for monitoring the contents of the program table, a gate 5 to obtain interface with the program table added in the external part, a pipe line adjusting and a delay circuit for matching with the pipe line of an arithmetic circuit and a command decoder to decode the control signal of the program table from an external input signal. Thus, since the program decoder 6 to synthesize the program tables 1-4 in bit direction and word direction, input/output gate circuit 5 to increase the program tables 1-4 in the external part and pipe line adjusting circuit 50 to adjust the pipe line are provided, the program table input/output circuit can be composed of one kind of the circuit and efficiently formed to make an LSI.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a program table input/output circuit, and in particular to a program ID, calculation parameters, and data ID loaded into a program table from a low-speed bus connected to a microcomputer.
The present invention relates to a program table input/output circuit, which is one of the circuits constituting an arithmetic module of a data flow processor, for reading out and referencing the data flow processor at the time of starting an operation.

[Conventional technology]

As shown in FIG. 2, the data flow processor has a configuration in which arithmetic modules with different functions are connected in parallel to a high-speed bus 80 for arithmetic data and a low-speed bus 90 for program loading.

The calculation data has a data ID and is input to the calculation modules 70 to 72 from the high-speed bus. Arithmetic module 70~
At 72, the data ID is input to the program table input/output circuit, and the calculation parameters are read out and sent to the calculation circuit. The arithmetic data is input to the arithmetic circuit, processed in accordance with the arithmetic parameters, and outputted to the high-speed bus 80 again with the data ID output from the program table input/output circuit and the module ID indicating the data destination.

[Problem to be solved by the invention]

The conventional program table input/output circuit described above has the disadvantage that the size and number of program tables are fixed, so it is necessary to prepare a different program input/output circuit for each calculation module, making it difficult to standardize the circuit. there were.

[Means to solve the problem]

The program table input/output circuit of the present invention includes a program ID of a calculation module, a data ID added to data of calculation parameters and calculation results, a program table into which the module ID is loaded, and control signals, selectors, and gates of the program table. and a command decoder that generates a multiplexer switching signal, a selector that switches the address of the program table, a pipeline adjustment delay circuit that adjusts the number of pipeline stages, and a gate circuit that adds a program table. be done.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

This embodiment includes program tables 1 to 4, selectors 7 to 11 for switching their inputs, multiplexers (hereinafter referred to as MPX) 17 to 20, and gates 12 to 16 for monitoring the contents of the program tables. A gate 5 that interfaces with an externally added program table, a pipeline adjustment delay circuit 50 that matches the pipeline of the arithmetic circuit, and a command decoder 6 that decodes the control signal of the program table from an external input signal. Become.

In this embodiment, a program table 3.4 for loading calculation parameters into the calculation circuit 100 and a gate 5 for interfacing with an externally added program table are provided.
It is configured so that it can be matched with the pipeline (three stages) of the arithmetic circuit 100. The arithmetic circuit 100 is composed of a three-stage pipeline, with the first pipeline referring to the computation parameter 1, the second pipeline referring to the computation parameter 2, and the third pipeline referring to the computation parameter 2 through the gate 5. The output of the program table added in the controlled arithmetic circuit 10 is referred to. Pipeline adjustment delay circuit 50
is composed of registers 21 and 22, and the number of stages can be selected using MPX17 to MPX20. In this embodiment, for example, M
The output of PX18 is used as the program ID signal PIDI, the output of MPX19 delayed by the register 21 is used as the program ID signal PID2, and the output of MPX20 further delayed by the register 21 is used as the program ID signal PI.
It is designed to switch to D3.

Each program table 1 to 4 and gate 5 for external expansion
switching signals C1, C5, C9, C13, C17 of selectors 7 to 11, which are control signals of , and write enable signals C2, C6 applied to write enable terminal W.
, CIO, C14°C18, read enable signals C3, C7, C11, applied to read enable terminal R;
C15, C19, chip select signals C4, C8, CI2 . C16, C2
0 is an external input read control signal RC, write control signal WC, table select signal TBO~
4. It is generated by decoding the high-speed bus access signal HBA and low-speed bus access signal LBA by the command decoder 6.

In addition, each program table 1 to 4 has an address signal C
By switching the selectors 7 to 11 to which A is input, it is possible to access from the low-speed bus access signal LBA and the high-speed bus access signal HBA. When accessing from a low-speed bus, the program is loaded and the loaded program is monitored. Access from the high-speed bus occurs during calculations, and calculation parameters are sent to the calculation circuit, and module IDs and data IDs are output in synchronization with calculations.

Zero-order program tables 3 and 4 whose operation was explained above
In this embodiment, the program tape J3.4 is used as 16 bits x 128 words. 32 bits x 128 words, or 1
It can be used as 6 bits x 256 words.

Furthermore, if two tables of 16 bits x 128 words are insufficient, a program table added outside the gate 5 can be connected as shown in this embodiment.

Gate 5 is a write enable terminal W that controls the program table.

This is an input/output gate that can be switched by signals from read enable terminal R and chip select terminal C8.

In FIG. 1, a connection line with a number inside a circle indicates that it is connected to a connection line with the same number inside a circle.

〔Effect of the invention〕

As explained above, the present invention replaces the program table input/output circuit, which had to be designed as a separate circuit because the size, number, and pipeline of the program tables for loading calculation parameters by the calculation circuit differ, by converting the program table into bits. It has a command decoder that can be synthesized in the direction and word direction, an input/output gate circuit for externally adding a program table, and a pipeline adjustment circuit for adjusting the pipeline, so it can be configured with one type of circuit and is highly efficient. It has the effect of being able to be integrated into an LSI.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a general explanatory diagram showing the module configuration of a data flow processor. 1-4...Program table, 5...Gate for external expansion, 6...Command decoder, 7-11...
Selector, 12-16... Gate, 17-20...
Multiplexer, 21.22...Register, 100.
...Arithmetic circuit.

Claims (1)

[Claims] Program ID of the calculation module, data ID added to calculation parameters and calculation result data, module I
A program table into which D is loaded, a command decoder that generates control signals for the program table and switching signals for selectors, gates, and multiplexers, a selector that switches addresses of the program table, and a pipe that adjusts the number of pipeline stages. A program table input/output circuit comprising a line adjustment delay circuit and a gate circuit for adding a program table.