JPH02252236A - Semiconductor device and manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce contact resistance by forming a P-type impurity region by implanting boron ion, burying a semiconductor layer containing impurity in an aperture part of an insulating layer formed on the impurity region, and performing heat treatment. CONSTITUTION:A P-type impurity region 2 is formed in a semiconductor region 1 of a silicon substrate by implanting boron ion, and an aperture 4 is arranged in an insulating layer 3 composed of SiO2 and the like on the impurity region 2. A semiconductor layer 5 containing impurity is formed by ion-implanting BF2<+> into the aperture 4. By heat-treating said layer from the arrow direction 6, the contact resistance between the region 2 and the semiconductor layer 5 is reduced. By using boron ion in this manner, the growth of polysilicon grain is not restrained at the time of activation RTA, and large grain is grown, so that resistance can be sufficiently reduced.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

Industrial Application Field Overview of the Invention Prior Art and Problems Purpose of the Invention Means for Solving the Problems Example-1 (Fig. 1A, 1st Example-2 (Fig. 2A, 2nd Example) Figure 2C, 2nd Example-3 (Figure 3A, 3rd Example-4 (Figure 4A, 4th Example-5 (Figure 5A)) Example-6 (Figure 5B) Effect of the invention B Figure) Figure B, Figure D) Figure B) Figure B) [Field of Industrial Use] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. The present invention is particularly applicable to a semiconductor device in which a semiconductor layer (or a conductive layer) is formed in an opening of an insulating layer, or a method for manufacturing such a semiconductor device.

[Summary of the invention]

The inventions of claims 1 to 3 of the present application provide a method for manufacturing a semiconductor device in which an opening is formed in an insulating layer over a P-type impurity region, in which the impurity region or the semiconductor layer in the opening is ionized with boron ions. It is formed by injection or combined with heat treatment to reduce the resistance when used as a contact. Further, the invention of claim 4 of the present application reduces the contact resistance by making the contact area between the contact semiconductor layer and the contacted region smaller than the contact area between the semiconductor layer and the wiring layer. . Further, the invention of claim 5 of the present application reduces the resistance by heat-treating the surface of the impurity region by laser irradiation and forming a conductive layer in the opening of the insulating layer thereon.

[Conventional technology and problems]

Conventionally, a semiconductor or the like is buried in an opening provided in an insulating layer to form a conductive layer, and it is used as a contact, for example.
Alternatively, techniques such as a so-called trench capacitor have been proposed and put into practical use.

On the other hand, in the field of semiconductor devices, miniaturization and integration are progressing rapidly. With such miniaturization, various problems have arisen that need to be solved in the technology for forming a conductive layer or the like in the above-mentioned openings.

For example, with the miniaturization of semiconductor devices, a technology for filling and planarizing contact holes with a high aspect ratio (that is, a depth that is large compared to the opening area) has become necessary. However, as miniaturization progresses in this way, a problem arises in that the resistance of the conductive portion obtained by filling the holes is not sufficiently reduced, making it impossible to make good contact. For example, one technique for filling and planarizing the holes is to deposit a semiconductor material such as polysilicon by CVD or the like, and then perform etchback to achieve the planarization. When using this method, polysilicon is typically deposited on a P-type semiconductor (P diffusion layer), holes are filled, and impurities are introduced into the polysilicon to impart conductivity. Generally, as a means of introducing impurities, ion implantation of BF2'' is carried out, and this is subjected to, for example, RT.
It is activated by heat treatment such as A (Rapid Thermal Anneal).

As a result, the polysilicon dalein grows sufficiently, and the resistance can be lowered.

However, as mentioned above, when miniaturization progresses and, for example, a hole with a large aspect ratio has to be used as an opening and a conductive part is formed therein, the above-mentioned conventional technology does not necessarily reduce the resistance of the conductive part. If this is not sufficient, good contact may not be obtained when used for forming contact holes.

[Purpose of the invention]

The present invention solves the above problems and provides a semiconductor device having a conductive part in an opening of an insulating layer, and a method for manufacturing such a semiconductor device, which can achieve low resistance even when the device is miniaturized and integrated. It is an object of the present invention to provide a method for manufacturing a semiconductor device, which can form a conductive part.

[Means for solving problems]

In order to solve the above-mentioned problems and achieve the above-mentioned objects, each invention according to the present application takes the following technical means.

The invention according to claim 1 includes a step of implanting boron ions into a semiconductor region to form a P-type impurity region, and forming a semiconductor layer containing an impurity in an opening of an insulating layer formed on the P-type impurity region. A method of manufacturing a semiconductor device includes a burying step and a heat treatment step of reducing contact resistance between the P-type impurity region and the semiconductor layer.

The invention according to claim 2 includes a step of embedding a semiconductor layer in an opening of an insulating layer on a P-type impurity region formed in a semiconductor region, a step of ion-implanting boron ions into the semiconductor layer, and a heat treatment step. 1 is a method of manufacturing a semiconductor device comprising:

The invention according to claim 3 is a method for manufacturing a semiconductor device according to claim 2, wherein the heat treatment is performed by laser irradiation.

In the invention according to claim 4, a semiconductor layer is embedded in an opening of an insulating layer formed on a contact area (9N), and a wiring formed on the contact area and the semiconductor layer is connected via the semiconductor layer. A semiconductor device in which a contact area between the semiconductor layer and the contact area) is smaller than a contact area between the semiconductor layer and the wiring layer. be.

The invention according to claim 5 provides a semiconductor comprising the steps of heat-treating the surface of an impurity region formed in a semiconductor region by laser irradiation, and forming a conductive layer in an opening of an insulating layer formed on the impurity region. This is a method for manufacturing the device.

[For production]

The invention according to claim 1 of the present application is characterized in that boron ions are implanted into a semiconductor region to form a P-type impurity. By forming the Iw4 region and including a heat treatment process, the contact resistance is reduced.

The invention according to claim 2 of the present application achieves low resistance by implanting boron ions into the semiconductor layer buried in the opening of the insulating layer on the P-type impurity region formed in the semiconductor region and heat-treating the semiconductor layer. be done.

In the invention according to claim 3 of the present application, the resistance can be effectively reduced by performing the heat treatment according to claim 2 by laser irradiation.

The invention according to claim 4 of the present application is a semiconductor layer formed on an insulating layer formed on a contact area (to be contacted), and a semiconductor layer is embedded in an opening of an insulating layer formed on an SM region, and a semiconductor layer is formed on the contact area and the semiconductor layer via the semiconductor layer. In a semiconductor device in which a wiring layer is electrically connected, the contact area between the semiconductor layer and the contacted region is smaller than the contact area between the semiconductor layer and the wiring layer, so that the contact area is reduced due to good contact. Resistance and miniaturization can be achieved.

The invention of claim 5 of the present application includes the steps of heat-treating the surface of an impurity region formed in a semiconductor region by laser irradiation, and forming a conductive layer in an opening of an insulating layer formed on the impurity region. By doing so, the resistance can be lowered.

〔Example〕

Next, examples of the present invention will be described. It should be noted that, as a matter of course, the present invention is not limited in any way by the embodiments described below.

Example 1 This example embodies the invention according to claim 1 of the present application, and is a low-resistance contact portion by filling polysilicon into an opening forming a contact hole and flattening the polysilicon. The present invention is applied so that a semiconductor device having the following characteristics can be obtained.

In the semiconductor device manufacturing method of this embodiment, as shown in cross-sectional views in the order of steps in FIG. 1A, boron ions (B
A step of ion-implanting the P-type impurity region 2 (the state after this step is shown in FIG. 1A(a));
Opening 4 (first
A process of embedding the semiconductor layer 5 containing an impurity in the semiconductor layer (see FIG. 1A (b)) (the state after this process is shown in FIG. 1A (C)), and contact between the P-type impurity region 2 and the semiconductor layer 5. A heat treatment step (see FIG. 1A (d)) for reducing resistance is included.

In this embodiment, in this way, contact between the P-type impurity region 2 and the wiring formed on the insulating layer 3 is established by the semiconductor layer 5 containing the impurity.

The semiconductor region 1 in this embodiment is a silicon semiconductor region in a silicon substrate. Furthermore, in this embodiment, polysilicon was used as the semiconductor material to be filled in and planarized in the opening 4 forming the contact hole.

That is, the present example will be described in more detail as follows.

First, as shown in FIG. 1(a), boron ions (Bo) are ion-implanted into a semiconductor region 1 of a silicon substrate.
Form a type impurity region.

Next, as shown in FIG. 1A (b), a P-type impurity region 2 is formed.
An opening 4 is formed in the insulation N3 made of 5iOz or the like formed above.
will be established. In this embodiment, the opening 4 can be formed arbitrarily depending on the material of the insulating layer 3 by using an appropriate deposition method such as CVD and an etching technique using an appropriate mask. In this embodiment, polysilicon is deposited in the opening 4 above the P-type impurity region 2, and the hole is filled and
Flatten. For this purpose, any means such as CVD commonly used for depositing polysilicon can be used, and for planarization, a general method such as etch-back can be used. In this embodiment, appropriate impurity introduction is performed in order to contain impurities in the polysilicon. Here, BF2+ is ion-implanted, thereby introducing impurities into the polysilicon, and forming a semiconductor layer 5 containing impurities. And so. As a result, the structure shown in FIG. 1A (C) is obtained.

It is also possible to use Bo ion implantation.

However, instead of introducing impurities by ion-implanting impurities into pure polysilicon in this way, doped polysilicon (referred to as DOP OS) that has been doped with impurities in advance is used and deposited. For example, the semiconductor layer 5 containing impurities can be obtained.

Next, as a heat treatment step, for example, PTA (Rapi
dThermal Anneal) is performed, thereby activating and reducing the contact resistance between the P-type impurity region 2 and the semiconductor layer 5 containing impurities. In Figure 1A + dl,
Such heat treatment is schematically shown with arrow 6.

The above configuration makes it possible to make a contact with low resistance.

The reason why this configuration can achieve low resistance is considered to be due to the following mechanism.

Polysilicon is deposited on P-type impurity regions such as P-type diffusion layers.
In the conventional technique of depositing by VD method etc. and then filling and planarizing by etching back, it was common to ion-implant BFg'' when forming the above-mentioned P-type impurity region. For example, ion implantation (BP t '' ion implantation, etc.) is performed on the polysilicon deposited and filled on the P-type impurity region, and then RT
When activated by A, the resistance can be lowered if polysilicon grains grow sufficiently, but polysilicon grains do not grow sufficiently on the P-type impurity region as described above. This is due to Bp! when forming a P-type impurity region. This is thought to be because in ion implantation, a damaged layer is formed near the silicon surface, which suppresses grain growth.

On the other hand, in the invention of claim 1 of the present application, Bo is used instead of BF2+ ions to form the P-type impurity region, and according to this, for example, the growth of polysilicon grains is prevented during activation RTA. It is thought that large grains grow without being inhibited, and thus a sufficiently low resistance can be achieved.

A fact supporting this is that when an An-3i alloy wiring is brought into contact with a P-type semiconductor (diffused N), which is a P-type impurity region, a P-type head region 10a obtained by ion implantation of BF2'' ions If it is above, (a) in Figure 1B
St nodule l where silicon grows from the periphery as in
On the P type region obtained by ion implantation of Bo- ions, P la grows as shown in FIG. 1B (b).
Si nodule llb with good crystallinity tightly attached to the mold region
It has been reported that nodules grow differently.

As described above, according to this embodiment, the opening (contact hole) made to connect the wiring in the semiconductor element and the P-type impurity region (P-type semiconductor) of the silicon substrate is filled with polysilicon and flattened. By using ion implantation of boron ions (B1) to form a P-type impurity region in the silicon substrate prior to this, the contact resistance between the wiring and the silicon substrate can be sufficiently reduced. .

Example 2 This example embodies the invention according to claim 2 of the present application. In this embodiment, the present invention is particularly applied to a technique for filling and planarizing polysilicon into an opening forming a contact hole.

This embodiment will be described below with reference to FIG. 2A.

In the method for manufacturing a semiconductor device according to this embodiment, a semiconductor region l
Opening 4 of insulating layer 3 on P-type impurity region 2 formed in
(The step of embedding the semiconductor layer 5 in FIG. 2A (see al) (the state after this step is shown in FIG. 2A (b)) and the step of ion-implanting boron ions into the semiconductor layer 5 (see FIG. 2A)
(See Figure (C)) and heat treatment process (See Figure 2A (d))
and.

More specifically, in this example, a P-type doped layer is obtained by implanting source/drain ions into a silicon substrate, which is a semiconductor region 1, and this is used as a P-type impurity region 2. A silicon dioxide film is formed to a certain thickness, and this is used as the insulating layer 3. This insulating layer 3 can function as a glabellar membrane. An opening 4 is formed in the insulating layer 3 by an appropriate means, and this is used as a contact hole. As a result, the structure shown in FIG. 2A (a) is obtained.

Next, the semiconductor layer 5 is buried in the opening 4.
In this example, polysilicon is buried, especially LP.
By depositing 5,000 layers of polysilicon using the (low-pressure) CVD method and etching it back, the holes were filled.
and planarization and embedding. This results in
The structure shown in FIG. 2A(b) is obtained.

Next, boron ions B' are implanted into this semiconductor layer 5, as schematically shown in FIG. 2A (C).

Here, boron ions B+ were doped under the conditions of 30 KeV and a dose of IXIO''/cIa.
Conventionally, BF2" was 60KeV and the dose I
0"/cjteF-7").

Next, the heat treatment in this example (Fig. 2A (see dl) is shown in R
TA was performed at 1100° C. in nitrogen for 10 seconds.

As a result, activation and diffusion were performed to obtain a P-type impurity diffusion region 2'.

After the steps up to FIG. 2A (d), the wirings are formed as appropriate. For example, AJ! -3i alloy (St content 1%)
/T i ON/T i wiring layer is formed.

In this embodiment, if high-energy boron ions are implanted before the step shown in FIG. 2A (C), that is, before the boron ion implantation, the contact resistance can be further reduced.

The effects of this example can be summarized as follows: BF? FIGS. 2B and 2C show a comparison between the case of B+ ion implantation and the case of B+ ion implantation (in the case of the present invention).

That is, FIG. 2B is a graph showing the relationship between contact area and contact resistance, and 1 in the same figure is boron
This is a graph for the case of the present invention in which B+ is doped by ion implantation under the conditions of 30 KeV and a dose of I
This is a graph for comparison when doping was performed by ion implantation under the condition of 1×10 1 th/C1a. Each graph was obtained based on the measurement point values for each case (black inverted triangles are data for the present invention, white triangles are data for comparison). . The etch-back conditions for polysilicon in both cases were such that etching was continued for 1 minute in addition to the just etch conditions. Graph I and graph■
As is clear from the comparison with
) has lower contact resistance when the contact area is the same compared to the comparison case (graph ■).
It can be seen that the resistance value has been improved. In this example, an improvement of about 38% is achieved.

Like two, BF? By changing the value to 81, it is possible to lower the resistance by about 40%.

This is thought to be due to the following effects.

That is, Fig. 2C shows the relationship between the dose and the sheet resistance (sheet resistance of polysilicon/SiO□), where ■ indicates the case of the present invention in which boron ions B were implanted at 30 KeV. Graph, ■ is BF? This is a graph for comparison when ions were implanted at 60 eV. In each case, the thickness of the polysilicon film was 8000 mm, and activation was performed by infrared heating at 1100° C. for 10 seconds in a nitrogen atmosphere. Both dose amounts are 2X10”/c
1i. As is clear from the comparison between graph (2) and graph (2), if the dose is the same, the present invention can obtain a lower sheet resistance value. It can be seen that there is an improvement of about 25%.

In FIG. 2C, data for cases I and IV in which heating was performed at 900° C. for 20 seconds in a nitrogen atmosphere are indicated by symbols V and Vl, respectively.

It can be seen that even in such a case, the present invention is able to achieve lower resistance.

Also, shown in Figure 2D is Al-3i (1%)/S
In the evaluation of the contact resistance between the i/T i ON/T i structure (first layer Af) and polysilicon, the horizontal axis represents the contact area and the vertical axis represents the resistance value. It can be seen that in contrast to the graph (2) in the case of ion implantation, the graph (2) in the case of the present invention in which Bo ion implantation is performed, which is indicated by a black circle, has a lower resistance.

From what has been explained using FIGS. 2C and 2D above, it is presumed that the effect of the present invention is that the contact resistance is reduced as shown in FIG. 2B.

As described above, according to this embodiment, in a method for manufacturing a semiconductor device that uses a semiconductor layer made of polysilicon to fill and planarize an opening, a layer on a P-type semiconductor (diffusion layer), which is a P-type impurity region, is used. By using boron ions B9 instead of the conventional BF2+ as an impurity to be ion-implanted and doped into the polysilicon buried in the contact, the contact resistance can be reduced.

Example 3 This example embodies the invention according to claim 3 of the present application, and in particular, ion implantation of boron ions B+ was performed to fill the opening on the P-type impurity region with polysilicon. By combining and laser annealing,
This structure is designed to reduce contact resistance.

As shown in FIG. 3A, this embodiment includes a step of embedding a semiconductor layer 5 in an opening 4 of an insulator 713 on a P-type impurity region 2 formed in a semiconductor region 1, and the state after this step is as follows. As shown in FIG. 3A (a), this embodiment further includes a step of implanting boron ions B into the semiconductor layer 5 (
(See FIG. 3A(b)). Furthermore, in this example,
Laser irradiation is performed as a heat treatment step, and for example, laser annealing is performed for excimer laser or the like (see FIG. 3A (e)).

More specifically, in this example, an opening 4 is formed in the insulating layer 3 of the semiconductor region l, which is a silicon substrate, by an appropriate means as described in each of the above examples.
A semiconductor layer 5 is formed by embedding polysilicon. This cross-sectional state after the polysilicon hole filling process is 3A.
It is figure (a).

Next, boron ions B1 are implanted into the third A(b) as shown schematically by reference numeral 7. For example, B” is 30
KeV, ion implantation is performed at a dose of approximately 2×101b. At this time, high-energy B+ ion implantation may be performed.

Next, activation is performed by heating means such as RTA, and the third
A P-type diffusion layer 2' is formed as shown in Figure A (C).

Next, in this embodiment, a reflective film 81 is formed using A1 or the like. This reflective film 81 is provided with an opening 82 at the corresponding contact portion. As a result, the structure shown in FIG. 3A (d) is obtained.

Next, as shown in FIG. 3A (81), laser annealing is performed. For example, an excimer laser can be preferably used. In this example, laser irradiation was performed at 0.7 J/cat. In the figure, reference numeral 9 indicates The laser irradiation is schematically shown below, whereby the surface layer of the semiconductor layer 5 becomes a highly activated layer 5' as schematically shown in FIG. 3A (e).

Next, the reflective film 81 is peeled off and a wiring layer 8' such as A1 is formed to obtain the structure shown in FIG. 3A (f).

In this example, boron ion B is used;
In addition to the overall activation, annealing by laser irradiation can be used to increase the activation rate of the polysilicon surface that is the semiconductor layer 5, so that a sufficiently low resistance can be achieved.

For example, the results of this example show that even if the thickness of the polysilicon hole filling is as thick as about 8,000, the contact resistance is
The diameter of the opening 4 is 0.6μmφ and 65Ω, which is a sufficient resistance of 10
Since it is less than 0Ω and is about 135Ω even at 0.4 μmφ, it can be used up to the 0.35 μm rule.

This is because in the conventional technology, the solid solubility limit of phosphorus P is large in contacts on N-type semiconductors, so it is easy to lower the resistance by increasing the dose, whereas in contacts on P-type semiconductors, The solid solubility limit of boron B is as large as P (,
For example, when using N, , R, TA at 1100°C for 110 seconds, in BF, + ion implantation, the dose amount I
There is no significant difference in resistance between 0"Cl11-" and 2X10"Ca1-", so for example when filling a polysilicon hole into a contact hole 8000 people deep,
This is a significant improvement compared to the case where even 0.6 μmφ did not fall below 100Ω.

The following table shows the contact resistance when the opening is filled with polysilicon and is treated with laser at various powers for various hole sizes.From this, the effect of laser treatment is clear. Will. For example, compared to the case without laser treatment, 0.7J
/c- treatment and contact resistance (unit: 2 ohms) In addition, Fig. 3B shows the relationship between the contact area and contact resistance in this example when each measurement point was taken following Fig. 2B, which explained the relationship between the contact area and the contact resistance. Based on this, it is expressed by a straight line (the illustration of each measurement point is omitted), and the figure is designated by the symbol IXa.
When BF2+ is ion-implanted at a dose of 2XIO"cm-", IXb is the same as B+ at 2 x 1016 c
This is data in the case of the present invention in which "2 and Bo were subjected to laser annealing at 240 KeV and 1X10" as in the example. The effects of the present invention can be understood from a comparison of graphs IXb and IXc.

Example 4 Next, Example 4 will be described. This embodiment embodies the invention according to claim 4 of the present application, and is particularly applicable to a semiconductor element in which polysilicon is used as a contact by filling an opening above a contact region with polysilicon as a semiconductor layer. It is designed to reduce resistance, reduce the contact area with a semiconductor region such as a silicon substrate, and increase the degree of integration.

In this embodiment, as shown in FIG. 4A(d), semiconductor N
5 is embedded, and the contact region 2 and the wiring layer 8 formed on the semiconductor layer are electrically connected via the semiconductor layer 5. This semiconductor device is characterized in that a contact area S1 with the IF region 2 is smaller than a contact area S2 between the semiconductor M5 and the wiring layer 8.

In the semiconductor device of this embodiment, the contact region 2 is a source/drain region formed in a silicon substrate, which is the semiconductor region 1, and the insulating layer 5 is made of Si, which is an interlayer film or the like.
0□, etc., and the semiconductor layer 5 is formed by embedding polysilicon.

The semiconductor device of this example can be manufactured through the steps shown in FIGS. 4A (a) to (d).

First, as shown in FIG. 4A (a), an opening 4 that will become a contact hole is opened. The size of the opening 4 is made slightly larger than the area 41 of the conventionally formed contact hole. That is, it is made slightly larger than the original size conventionally thought to be necessary. In this example, the present invention was applied to a structure having Sing's LOCO3II as an element isolation region, but by making the opening 4 larger, the opening 4 may extend over the LOGOS edge, etc. as shown in the figure.

Next, a sidewall 42 is formed in the opening 4 by CVDL and then etching back (not shown) to obtain the structure shown in FIG. 4A (b).

Next, the opening 4 is filled with polysilicon and planarized using an appropriate means to obtain the structure shown in FIG. 4A (C) having a semiconductor layer 5 made of polysilicon.

After appropriate activation, an arrangement a layer (may be Ajl! etc.) is formed.

As a result, it is possible to obtain the structure shown in FIG. 4A (d) in which the contact area S1 between the semiconductor layer 5 and the contact region 2 is smaller than the contact area S2 between the semiconductor layer 5 and the wiring layer 2.

The shape of the opening 4 forming the contact hole is arbitrary;
For example, the contact hole may have a tapered shape.

For example, it may be as shown in FIGS. 4B (a) to (C).

In this embodiment, as described above, the semiconductor layer 5 is formed by filling the opening 4 which forms the contact hole between the wiring layer 8 and the contact region 2 such as a diffusion layer in a silicon substrate etc. with polysilicon. In the semiconductor device, the opening area of the opening 4 on the wiring layer 8 is made larger than the opening area on the contact region 2, so that the semiconductor layer 5
(and contact) The contact area with the I region 2 is smaller than the contact area between the semiconductor region 5 and the wiring layer 8.

As a result, the reduction in contact resistance can be reduced.

This is because the contact area between the wiring layer 8 such as metal wiring and the semiconductor layer 5 such as polysilicon is large.

Note that since the dimensions of the wiring layer 8 are generally larger than the hole size of the opening 4, the vertical dimensions of the opening 4 usually define the respective contact areas.

Furthermore, when forming the opening 4 forming the contact hole, it is advantageous in that it is only necessary to make the opening larger than the conventional one, and the opening can be made larger than the limit value.

Furthermore, if a sidewall or the like is used as in the above-mentioned specific example, the contact area (near the contact hole 2) can be made smaller than the critical resolution, and integration can be achieved.

Conventionally, hole filling and planarization technology using polysilicon, etc., has been used for wiring connections.
Among the contact resistance of silicon, the resistance of polysilicon, and the wiring/polysilicon contact resistance, resistance (2) is large and defines the contact hole. It is possible to lower the overall resistance by lowering the resistance.

In addition, as lithography technology progresses in miniaturization,
It becomes difficult to form minute contact holes, and as a result,
It is normal to form a contact hole with a width slightly larger than the minimum line width used in the device, and it is said that the limit is usually 1.3 to 1.4 times the line and space width. Even in such a situation, there is no problem with the technique of claim 4 because the opening 4 that is initially opened can be set to be larger.

In addition, in a semiconductor device, the contact hole is LOG
If it gets on the OS edge or gate sidewall, it will have a negative effect on the semiconductor device characteristics, and if it gets on the LOCOS edge, for example, there is a problem of increased leakage current, but as mentioned above, this configuration solves this problem. be done.

Example 5 Next, Example 5 will be described. This example embodies the present invention according to claim 5 of the present application, and is a method for manufacturing a semiconductor device in which the contact resistance between a wiring layer and an impurity region (P-type, N-type diffusion layer, etc.) is reduced. This is what has become concrete. In particular, it is applied to hole-filling and planarization of tungsten (W) by selective CVD.

As illustrated in FIG. 5A (the same applies to FIG. 5B related to Example-6 described later), this embodiment includes a step of heat-treating the surface of an impurity region 2 formed in a semiconductor region 1 by laser irradiation, and a step of heat-treating the surface of an impurity region 2 formed in a semiconductor region 2, forming a conductive layer 51 in the opening 4 of the insulating layer 3 formed on the insulating layer 3.

Specifically, in this embodiment, ion implantation for forming a source/drain is carried out according to a conventional method, and diffusion for forming a junction is carried out to form an impurity region 2 as shown in FIG. 5A (a). Impurity region 2 may have a so-called LDD structure. In the figure,
11 is a locos area.

Next, the surface of the impurity region 2 is irradiated with a laser as shown schematically by reference numeral 9 to form the surface as shown in FIG. 5A (bl).
(drain region) This is a highly activated layer in which the activation rate of impurities on the surface is increased.

Next, an insulating layer 3 serving as an interlayer film is formed using 5i02 or the like. This is the state shown in FIG. 5A (C1).

Next, an opening 4 is formed and used as a contact hole (FIG. 5A(d)).

After that, fill the hole with selective CVD of tungsten W and flatten it.
A conductive layer 51 is formed (FIG. 5A(e)).

Next, the wiring layer 8 is made of aluminum or aluminum alloy (S
(e.g. one containing 1% i) or other molding materials.

In this example, unlike Example 6 described below, the entire surface of the impurity region 2 (diffusion layer) becomes highly active by laser irradiation.

According to this embodiment, by performing laser irradiation, the activation rate of impurities on the surface of the impurity region (diffusion layer) 2 can be increased, and thereby the wiring layer 8 such as a metal wiring and the semiconductor region such as a silicon substrate Contact resistance with impurity region (diffusion layer) 2 on top of layer 1 can be reduced. Note that during annealing to achieve the above, other parts are not affected.

Example-6 Next, Example-6 will be described. This example is a modification of Example-5, and like Example-5, it embodies the invention of claim 5 of the present application. be.

In this example, as shown in FIG. 5B, an impurity region 2 is formed in a semiconductor region 1 such as a silicon substrate, and as shown in FIG.
) is obtained, and then an insulating layer 3 forming a glabellar membrane is formed using SiO□ or the like, as shown in FIG. 5B (b).

Next, for example, All is applied as the reflective film 81, and the fifth B
Do as shown in figure (C).

Next, an opening 4 is formed as a contact hole. This results in the structure shown in FIG. 5(d).

In this state of FIG. 5(d), laser annealing (indicated by reference numeral 9 in the figure) is performed (FIG. 5B(e)). As a result, a highly activated layer 21 is obtained.

Next, as in Example 5, holes are filled and flattened by W selective CVD. As a result, the structure of FIG. 5B (fl) is obtained.

Next, a wiring layer 8 such as A1 alloy or other metal wiring is formed. This is the structure shown in Figure 5B fg).

This example can also produce the same effects as Example-5.

Note that in FIG. 5B (C1(d)), the process of forming the reflective film 81 and the process of forming the opening 4 may be reversed, and the reflective film 81 may be formed after the opening 4 is formed.

Further, it is better to remove the reflective film 81 inside the shell after laser annealing and before selective CVD of W, but it may be left in place.

〔Effect of the invention〕

As described above, according to each invention of the present application, it is possible to provide a semiconductor device with reduced resistance such as contact resistance, and a method for manufacturing such a semiconductor device.

[Brief explanation of drawings]

Figure 1A, Figure 2A, Figure 3A, Figure 4A, Figure 5A,
FIG. 5B shows Examples-1, -2, and -3 of the present invention, respectively.
, -4, -5, -6 are shown in cross-sectional views in the order of steps. Figure 1B, Figure 2B, Figure 2C, and Figure 2
FIG. D and FIG. 3B are the examples ~l, -2, and -3, respectively.
It is a figure explaining the effect|action. FIG. 4B is a diagram showing a modification of Example-4. 1... Semiconductor region, 2... P-type impurity region, 3...
- Insulating layer, 4... Opening, 5... Semiconductor layer, 51.
...Conductive layer.

Claims (1)

[Claims] 1. A step of implanting boron ions into a semiconductor region to form a P-type impurity region, and forming a semiconductor layer containing an impurity in an opening of an insulating layer formed on the P-type impurity region. A method for manufacturing a semiconductor device, comprising: a burying step; and a heat treatment step for reducing contact resistance between the P-type impurity region and the semiconductor layer. 2. Manufacturing a semiconductor device comprising: embedding a semiconductor layer in an opening of an insulating layer on a P-type impurity region formed in a semiconductor region; implanting boron ions into the semiconductor layer; and heat treatment. Method. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the heat treatment is performed by laser irradiation. 4. A semiconductor layer is embedded in the opening of the insulating layer formed on the contact region, and the contact region and the wiring layer formed on the semiconductor layer are electrically connected via the semiconductor layer. In the semiconductor device, the contact area between the semiconductor layer and the contacted region is
A semiconductor device characterized in that the contact area between the semiconductor layer and the wiring layer is smaller than the contact area between the semiconductor layer and the wiring layer. 5. A method for manufacturing a semiconductor device, comprising: heat-treating the surface of an impurity region formed in a semiconductor region by laser irradiation; and forming a conductive layer in an opening of an insulating layer formed on the impurity region.