JPH02251142A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH02251142A
JPH02251142A JP7338889A JP7338889A JPH02251142A JP H02251142 A JPH02251142 A JP H02251142A JP 7338889 A JP7338889 A JP 7338889A JP 7338889 A JP7338889 A JP 7338889A JP H02251142 A JPH02251142 A JP H02251142A
Authority
JP
Japan
Prior art keywords
semiconductor layer
substrate
layer
semiconductor
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7338889A
Other languages
Japanese (ja)
Inventor
Hitoshi Nishimura
仁 西村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujikura Ltd
Original Assignee
Fujikura Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujikura Ltd filed Critical Fujikura Ltd
Priority to JP7338889A priority Critical patent/JPH02251142A/en
Publication of JPH02251142A publication Critical patent/JPH02251142A/en
Pending legal-status Critical Current

Links

Landscapes

  • Weting (AREA)

Abstract

PURPOSE:To facilitate the unified formation of a cantilever structure and a stopper by removing the first semiconductor layer that is exposed from a window by electrochemical etching while impressing voltage to the second semiconductor layer as well as a semiconductor substrate. CONSTITUTION:The second semiconductor layer 3 is removed by etching from the window 42 of a mask film. When electrochemical etching is performed after causing the first semiconductor layer 2 to be exposed, both the second semiconductor layer 3 and a semiconductor substrate 1 are protected from electrochemical etching and only the first semiconductor layer 2 is removed because the second semiconductor layer 3 and the semiconductor substrate 1 each have a conductivity type that is opposite to that of the first semiconductor layer 2; besides, the above layer 3 and substrate 1 are impressed by voltage. As only the above layer 2 which is sandwiched between the layer 3 and the substrate 1 is in this way removed, etching goes crosswise and a cavity 21 is formed below the layer 3 and as a result, a cantilever structure made up by the second semiconductor layer 3 is formed. A stopper on the substrate side of a cantilever is easily formed to be integral with the cantilever.

Description

【発明の詳細な説明】[Detailed description of the invention] 【産業上の利用分野】[Industrial application field]

この発明は、半導体装置の製造方法に関し、とくに片持
ちばっとストッパとを一体に形成する半導体装置の製造
方法に関する。
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device in which a cantilever and a stopper are integrally formed.

【従来の技術】[Conventional technology]

半導体を用いた加速度センサや加速度スイッチなどでは
、片持ちばり構造を形成する必要のある場合がある。こ
のような場合、従来では、n型及びp型の単結晶シリコ
ンの2層構造のうちp型の部分をエレクトロケミカルエ
ツチングで除去して片持ちばつを作製するようにしてい
る。 すなわち、たとえば第2図に示すように、p型車結晶シ
リコン基板7の上にn型単結晶9912層3をエピタキ
シャル成長させ、さらにその表裏両面にマスク膜4.5
を設ける。そして第2図Aのようにマスク膜4にエツチ
ング窓42を設けて、この窓から、通常のエツチングに
よりシリコン層3の一部を除去して基板7を露出させ、
第2図Bのような構造とする。その後、エレクトロケミ
カルエツチングによりこのエツチング窓42からp型の
基板7の部分のみをエツチングして第2図Cのようにn
型のシリコン層3の下に空洞71を形成する。このよう
に空洞71が形成されることにより、空洞71の上の部
分のn型シリコン層3が片持ちぼり10となる。 また、第3図のようにする場合もある。まず第3図Aの
ように、p型車結晶シリコン基板7グ〕上にn型単結晶
9932層3をエピタキシャル成長させ、さらにその表
裏両面にマスク膜4.5を設けた後、裏面のマスク膜5
にエツチング窓51を設ける。つぎに第3図Bのように
、エレクトロケミカルエツチングにより裏面からエツチ
ング窓51を通してp型基板7の部分に空洞71を設け
る。 その後、第3図Cのように通常のウェッ1〜エッヂング
またはCF4プラズマエツチングにより11型シリコン
層3(及びマスク膜4)の一部に孔31を設けると、片
持ちぼり10が形成できる。 こうして片持ちぼり構造を作る場合、はっとして形成さ
れたシリコ〉・は非常に破壊され易いのて、振幅量に制
限を加えて破壊から守る必要かある。 すなわち、片持ちばり10が振れる両側にストッパを取
り付けて、片持ちばつがある程度以上には湾曲しないよ
うにして片持ちばつが破壊されないようにする。 従来では、片持ちばり10の強度が大きい場合や基板7
か十分に薄い場合には第4図に示すように、基板7の裏
面側に下部ストッパ1]を接着するとともGこ、片持ち
はり10の上側に上部ストッパ12を接着している。ま
た、片持ちはり10が薄い等でその強度が小さいときは
、振幅を小さくするために第5図のような片持ちばり1
0の下側の空洞に対応した形状の下部ストッパ11を基
板7の裏面側に接着するとともに、片持ちはり10の上
側にはガラスやシリコンの上部ス1ヘツパ1.2を接着
剤13で取り付けるようにしている。この接着剤13と
し、ては、上部ストッパ12がガラスのときアノ−デイ
ックボンディングによるものとし、上部ストッパ12が
シリコンのときは片持ちぼり10側に蒸着されたC r
 −A uなどを用いる。
In acceleration sensors, acceleration switches, and the like using semiconductors, it may be necessary to form a cantilever structure. In such a case, conventionally, the p-type portion of the two-layer structure of n-type and p-type single crystal silicon is removed by electrochemical etching to create a cantilever. That is, for example, as shown in FIG. 2, an n-type single crystal 9912 layer 3 is epitaxially grown on a p-type wheel crystal silicon substrate 7, and a mask film 4.5 is further formed on both the front and back surfaces.
will be established. Then, as shown in FIG. 2A, an etching window 42 is provided in the mask film 4, and a part of the silicon layer 3 is removed through this window by normal etching to expose the substrate 7.
The structure is as shown in FIG. 2B. Thereafter, only the p-type substrate 7 is etched from this etching window 42 by electrochemical etching to form an n-type substrate 7 as shown in FIG. 2C.
A cavity 71 is formed under the silicon layer 3 of the mold. By forming the cavity 71 in this manner, the n-type silicon layer 3 above the cavity 71 becomes a cantilever 10. In addition, there are cases where it is done as shown in FIG. First, as shown in FIG. 3A, an n-type single crystal 9932 layer 3 is epitaxially grown on a p-type crystalline silicon substrate 7, and a mask film 4.5 is provided on both the front and back surfaces of the layer 3, and then a mask film 4.5 is formed on the back surface. 5
An etching window 51 is provided in the. Next, as shown in FIG. 3B, a cavity 71 is formed in the p-type substrate 7 through the etching window 51 from the back side by electrochemical etching. Thereafter, as shown in FIG. 3C, a cantilever 10 can be formed by forming a hole 31 in a part of the 11-type silicon layer 3 (and mask film 4) by ordinary etching or CF4 plasma etching. When creating a cantilevered structure in this way, the silico formed in a sudden manner is very easily destroyed, so it is necessary to protect it from destruction by limiting the amount of amplitude. That is, stoppers are attached to both sides of the cantilever beam 10 to prevent the cantilever beam from being bent beyond a certain level, thereby preventing the cantilever beam from being destroyed. Conventionally, when the strength of the cantilever beam 10 is high or when the substrate 7
If the cantilever beam 10 is sufficiently thin, a lower stopper 1 is bonded to the back side of the substrate 7, and an upper stopper 12 is bonded to the upper side of the cantilever beam 10, as shown in FIG. In addition, if the cantilever beam 10 is thin or has low strength, the cantilever beam 10 as shown in Fig. 5 may be used to reduce the amplitude.
A lower stopper 11 having a shape corresponding to the lower cavity of 0 is glued to the back side of the substrate 7, and an upper stopper 1.2 made of glass or silicon is attached to the upper side of the cantilever beam 10 using adhesive 13. That's what I do. This adhesive 13 is made by anodic bonding when the upper stopper 12 is made of glass, and by Cr vapor deposited on the cantilever 10 side when the upper stopper 12 is made of silicon.
-Au etc. are used.

【発明が解決しようとする課題】[Problem to be solved by the invention]

しかしながら、このように片持ちばつの振幅方向両側に
ストッパを設ける場合、基板とは反対側のストッパ(上
記では上部ストッパ)は比較的容易に取り付けることが
可能であるが、基板側のストッパ(上記では下部ストッ
パ)については、片持ちばつの強度が小さいときは問題
が多い。すなわち、下部ストッパは第5図のように片持
ちはりの基板側の空洞に対応した形状としなければなら
ないので、困難であるとともに、片持ちばっとストッパ
との間の間隔を正確に定めることは非常に難しい。 この発明は、片持ちはりの基板側のストッパを片持ちば
っと一体に、容易に形成することができるとともに、片
持ちはりとストッパとの間隔も非常に正確に制御できる
、半導体装置の製造方法を提供することを目的とする。
However, when providing stoppers on both sides of the cantilever in the amplitude direction, the stopper on the side opposite to the substrate (the upper stopper in the above example) can be attached relatively easily, but the stopper on the substrate side (in the above case, the upper stopper) can be attached relatively easily. Regarding the lower stopper), there are many problems when the strength of the cantilever is small. In other words, the lower stopper must have a shape that corresponds to the cavity on the board side of the cantilever beam as shown in Figure 5, which is difficult, and it is difficult to accurately determine the distance between the cantilever beam and the stopper. extremely difficult. This invention provides a method for manufacturing a semiconductor device in which a stopper on the substrate side of a cantilever beam can be easily formed integrally with the cantilever beam, and the distance between the cantilever beam and the stopper can be controlled very accurately. The purpose is to provide

【課題を解決するための手段】[Means to solve the problem]

上記目的を達成するため、この発明による半導体装置の
製造方法においては、一導電型半導体基板の一表面上に
上記基板と反対の導電型の第1半導体層と、上記基板と
同一の導電型の第2半導体層とを順次エピタキシャル成
長させる工程と、」1記第2半導体層の上にマスク膜を
形成する工程と、該マスク膜の窓から上記第2半導体層
をエツチングして第1半導体層を露出させる工程と、上
記の窓より露出した第1半導体層を、上記第2半導体層
及び半導体基板に電圧を印加しながらエレクトロケミカ
ルエツチングにより除去する工程とが備えられる。
In order to achieve the above object, in a method for manufacturing a semiconductor device according to the present invention, a first semiconductor layer of a conductivity type opposite to that of the substrate is formed on one surface of a semiconductor substrate of one conductivity type, and a first semiconductor layer of a conductivity type of the same conductivity type as the substrate is formed on one surface of a semiconductor substrate of one conductivity type. a step of sequentially epitaxially growing a second semiconductor layer, a step of forming a mask film on the second semiconductor layer, and a step of etching the second semiconductor layer through a window of the mask film to form the first semiconductor layer. and a step of removing the first semiconductor layer exposed through the window by electrochemical etching while applying a voltage to the second semiconductor layer and the semiconductor substrate.

【作  用】[For production]

マスク膜の窓よりエツチングして上記第2半導体層を除
去し第1半導体層を露出させた後、エレクトロケミカル
エツチングを行なうと、第2半導体層及び半導体基板は
第1半導体層とは反対導電型であり且つ電圧か印加され
ていることによりエレクトロケミカルエツチングから保
護され、第1半導体層のみが除去される。このように第
2半導体層と半導体基板との間に挟まれた第1半導体層
のみが除去されるので、エツチングは横方向に進み、第
2半導体層の下に空洞が形成されることになり、第2半
導体層による片持ちばり構造が形成されるとともに、基
板との間に所定の間隙が形成され、この基板が片持ちば
つのストッパとなることになる。 すなわち、半導体基板上に成長させる第1半導体層の厚
さか片持ちばつとス1−ツバとの間の間隔になるので、
この第1半導体層の厚さをコンl−ロールすることによ
り、片持ちばつとストッパとの間の間隔の精度を高くす
ることか容易である。 [実 施 例] つぎにこの発明の一実施例について図面を参照しながら
説明する。まず、第1図Aに示すように、n型単結晶シ
リコン基板1の表面上にp型車結晶シワ3フ エピタキシャル成長させた後、このn型単結晶9937
層3の上に及び基板1の裏面にマスク膜4、5をそれぞ
れ形成する。このマスク膜4、5はたとえばFll i
 O 2やSiNなとを成長させることにより作る。 つきに第1図Bに示すように、後述のエレクトロケミカ
ルエツチングの際のコンタク1〜となる耐領域6を形成
する。そのためマスク膜4の一部に拡散用の窓41を形
成し、この窓41から適当な不純物を拡散することによ
りn型層3及びn型層2を貫通して基板]にまで到達す
るn+領領域形成する。 その後、マスク膜4の別の箇所にエツチング用の窓42
を設け、この窓42からウェットエツチングを行なう。 このウェットエツチングは、たとえばエッチャントとし
てKOHやEDP (エチレンジアミン、ピロカテコー
ル、水の混合液)などを用いた通常のものでよい(マス
ク膜4としては前者の場合SiN.後者の場合SINま
たは5i02 )。 こうして第1図Cに示すように、最上層のn型層3の一
部を除去して、次の層であるn型層2を露出させる。 つぎにエレクトロケミカルエツチングを行い、表面側か
ら窓42を通してn型層2のみを除去する。この場合の
エッチャント(及びマスク膜4の材質との組合せ)は上
記と同じである。このとき、n+領域6をコンタク1−
としてIl型層3及びn型基板1に電圧を印加して、エ
レクトロケミカルエツチングによりこれらかエツチング
されないようにし、n型層2のみがエツチングされるよ
うにする。 すると、n型層2でエツチングが横方向に進み、第1図
りに示すように、基板1とn型層3との間に挟まれた空
洞21が形成されることになる。この空洞21の上の部
分のn型層3が片持ちばり10となる。 ここで、片持ちばり10は空洞21を間に挟んで基板1
の表面と対向することになり、この基板1か片持ちはり
10の下部ス)・ツバとして機能することになる。すな
わち、エレク)−ロケミカルエッチングの1工程により
片持ちばり10と下部ス1−ツバとが同時に形成てきる
。そして、この空洞21の巾、つまり片持ちはり10と
基板1の表面との間の間隔はp型車結晶シワ3フ 正確に一致するから、最初に基板1の表面にp型車結晶
シワ3フ ときに、その厚さをコントロールして置けは、片持ちは
り10と下部ストッパとの間隔を所望のものとすること
が容易である。その結果、数μI11というきわめて高
精度の間隔が容易に達成できる。 最後にマスク膜4、5を除去した後、第5図に示すよう
な、ガラスまたはシリコンの上部ストッパ12を接着剤
13で取り付ければ加速度センサや加速度スイッチのチ
ップが完成する。この場合、接着剤13としては、上部
ストッパ12がガラスのときアノ−デイックボンデイン
クによるものとし、上部ストッパ12がシリコンのとき
はn型単結晶9937層3の上に蒸着したCr−Auな
どを用いる。
When the second semiconductor layer is removed by etching through the window of the mask film and the first semiconductor layer is exposed, electrochemical etching is performed, so that the second semiconductor layer and the semiconductor substrate are of a conductivity type opposite to that of the first semiconductor layer. By applying a voltage and protecting the first semiconductor layer from electrochemical etching, only the first semiconductor layer is removed. Since only the first semiconductor layer sandwiched between the second semiconductor layer and the semiconductor substrate is removed in this way, the etching progresses laterally and a cavity is formed under the second semiconductor layer. A cantilever structure is formed by the second semiconductor layer, and a predetermined gap is formed between the second semiconductor layer and the substrate, which serves as a stopper for the cantilever. In other words, the thickness of the first semiconductor layer to be grown on the semiconductor substrate is the distance between the cantilever and the flange.
By controlling the thickness of the first semiconductor layer, it is easy to increase the precision of the distance between the cantilever and the stopper. [Example] Next, an example of the present invention will be described with reference to the drawings. First, as shown in FIG. 1A, after epitaxially growing p-type crystal wrinkles 3 on the surface of an n-type single crystal silicon substrate 1,
Mask films 4 and 5 are formed on the layer 3 and on the back surface of the substrate 1, respectively. These mask films 4 and 5 are, for example, Fll i
It is made by growing O 2 or SiN. At the same time, as shown in FIG. 1B, a resistant region 6 is formed which will serve as contacts 1 to 1 during electrochemical etching to be described later. Therefore, a diffusion window 41 is formed in a part of the mask film 4, and by diffusing an appropriate impurity from this window 41, the n+ region penetrates the n-type layer 3 and the n-type layer 2 and reaches the substrate. Form a region. After that, an etching window 42 is formed in another part of the mask film 4.
A window 42 is provided, and wet etching is performed from this window 42. This wet etching may be a conventional one using, for example, KOH or EDP (a mixed solution of ethylenediamine, pyrocatechol, and water) as an etchant (the mask film 4 is SiN in the former case, and SIN or 5i02 in the latter case). In this way, as shown in FIG. 1C, a portion of the uppermost n-type layer 3 is removed to expose the next layer, the n-type layer 2. Next, electrochemical etching is performed to remove only the n-type layer 2 from the front side through the window 42. The etchant in this case (and the combination with the material of the mask film 4) is the same as above. At this time, contact 1-
A voltage is applied to the Il type layer 3 and the n-type substrate 1 to prevent them from being etched by electrochemical etching, and only the n-type layer 2 is etched. Then, etching progresses laterally in the n-type layer 2, and a cavity 21 sandwiched between the substrate 1 and the n-type layer 3 is formed as shown in the first diagram. The n-type layer 3 above this cavity 21 becomes a cantilever beam 10. Here, the cantilever beam 10 is connected to the substrate 1 with a cavity 21 in between.
This substrate 1 functions as the lower part of the cantilever beam 10. That is, the cantilever beam 10 and the lower rib 10 can be formed at the same time by one step of electro-chemical etching. Since the width of this cavity 21, that is, the distance between the cantilever beam 10 and the surface of the substrate 1 exactly matches the p-type wheel crystal wrinkles 3, first the p-type wheel crystal wrinkles 3 are formed on the surface of the substrate 1. By controlling the thickness of the cantilever beam 10, it is easy to set the distance between the cantilever beam 10 and the lower stopper as desired. As a result, extremely precise spacing of a few μI11 can be easily achieved. Finally, after removing the mask films 4 and 5, an upper stopper 12 made of glass or silicon is attached using an adhesive 13 as shown in FIG. 5, thereby completing the chip of the acceleration sensor or acceleration switch. In this case, the adhesive 13 is anodic bonding ink when the upper stopper 12 is made of glass, and when the upper stopper 12 is made of silicon, it is made of Cr-Au etc. deposited on the n-type single crystal 9937 layer 3. use

【発明の効果】【Effect of the invention】

この発明の半導体装置の製造方法によれば、ス1〜ツバ
の取付工程を別に設けることなしに、片持ちばり構造と
ス1〜ツバとを、同じ工程で容易に、一体に形成するこ
とができる。また、片持ちばっとストッパとの間隔を非
常に精度高く制御できる。 その結果、片持ちばつの強度が小さい半導体装置でも歩
留まり良好に製造することができる。
According to the method for manufacturing a semiconductor device of the present invention, the cantilever structure and the ribs can be easily and integrally formed in the same process without providing a separate process for attaching the ribs. can. Additionally, the distance between the cantilever and the stopper can be controlled with high precision. As a result, even semiconductor devices with low cantilever strength can be manufactured with good yield.

【図面の簡単な説明】[Brief explanation of drawings]

第1図A.B,C,Dはこの発明の一実施例の各工程を
示す断面図、第2図A,B,C及び第3図A,B,Cは
従来例での片持ちぼり製造工程の各工程を示す断面図、
第4図及び第5図は従来例でのストッパ取付工程をそれ
ぞれ示す断面図である。 1・・・n型単結晶シリコン基板、2・・・p型単結晶
シリコン層、3・・・1)型単結晶シリコン層、4.5
・・・マスク膜、6・・・11+領域、7・・・p型車
結晶シリコン基板、10・・・片持ちばり、11・・下
部ストッパ12・・・上部ストッパ、13・・・接着剤
、21.71・・・空洞、41・・拡散窓、42.51
・・・エッヂ〉′グ窓。
Figure 1 A. B, C, and D are cross-sectional views showing each step of an embodiment of the present invention, and FIGS. 2A, B, and C, and 3 A, B, and C are each step of the conventional cantilever manufacturing process. A cross-sectional view showing
FIGS. 4 and 5 are cross-sectional views showing the stopper mounting process in a conventional example. 1... N-type single crystal silicon substrate, 2... P-type single crystal silicon layer, 3... 1) type single crystal silicon layer, 4.5
. . . Mask film, 6 . . 11+ region, 7 . . . P-type wheel crystal silicon substrate, 10 . , 21.71...Cavity, 41...Diffusion window, 42.51
...Edge〉'g window.

Claims (1)

【特許請求の範囲】[Claims] (1)一導電型半導体基板の一表面上に上記基板と反対
の導電型の第1半導体層と、上記基板と同一の導電型の
第2半導体層とを順次エピタキシャル成長させる工程と
、上記第2半導体層の上にマスク膜を形成する工程と、
該マスク膜の窓から上記第2半導体層をエッチングして
第1半導体層を露出させる工程と、上記の窓より露出し
た第1半導体層を、上記第2半導体層及び半導体基板に
電圧を印加しながらエレクトロケミカルエッチングによ
り除去する工程とを具備することを特徴とする半導体装
置の製造方法。
(1) A step of sequentially epitaxially growing a first semiconductor layer of a conductivity type opposite to that of the substrate and a second semiconductor layer of the same conductivity type as the substrate on one surface of a semiconductor substrate of one conductivity type; forming a mask film on the semiconductor layer;
etching the second semiconductor layer through the window of the mask film to expose the first semiconductor layer; and applying a voltage to the second semiconductor layer and the semiconductor substrate to remove the first semiconductor layer exposed from the window. 1. A method for manufacturing a semiconductor device, comprising the step of removing the semiconductor material by electrochemical etching.
JP7338889A 1989-03-24 1989-03-24 Manufacture of semiconductor device Pending JPH02251142A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7338889A JPH02251142A (en) 1989-03-24 1989-03-24 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7338889A JPH02251142A (en) 1989-03-24 1989-03-24 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02251142A true JPH02251142A (en) 1990-10-08

Family

ID=13516763

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7338889A Pending JPH02251142A (en) 1989-03-24 1989-03-24 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02251142A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5456117A (en) * 1993-04-21 1995-10-10 Kabushiki Kaisha Tokai-Rika-Denki-Seisakusho Pressure sensor apparatus and method of manufacturing wherein the silicon-crystal substrate of the sensor has inclined crystallographic axes and gage resistors formed in a cavity of the substrate
US5656512A (en) * 1991-06-12 1997-08-12 Harris Corporation Method of manufacturing a semiconductor accelerometer
US6020215A (en) * 1994-01-31 2000-02-01 Canon Kabushiki Kaisha Process for manufacturing microstructure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5656512A (en) * 1991-06-12 1997-08-12 Harris Corporation Method of manufacturing a semiconductor accelerometer
US5456117A (en) * 1993-04-21 1995-10-10 Kabushiki Kaisha Tokai-Rika-Denki-Seisakusho Pressure sensor apparatus and method of manufacturing wherein the silicon-crystal substrate of the sensor has inclined crystallographic axes and gage resistors formed in a cavity of the substrate
US6020215A (en) * 1994-01-31 2000-02-01 Canon Kabushiki Kaisha Process for manufacturing microstructure

Similar Documents

Publication Publication Date Title
US20020137348A1 (en) Electrochemical etching process
US6619133B1 (en) Semiconductor pressure sensor and its manufacturing method
KR100574575B1 (en) Micromechanical component
JP3347203B2 (en) Method for forming microcavities and microdevice having microcavities
KR20000028948A (en) Method for manufacturing an angular rate sensor
JP4168497B2 (en) Manufacturing method of semiconductor dynamic quantity sensor
JPH02251142A (en) Manufacture of semiconductor device
US4128467A (en) Method of ion etching Cd-Hg-Te semiconductors
JP2000277753A (en) Semiconductor accelerometer and its manufacture
JPH0797643B2 (en) Method for manufacturing pressure transducer
JPH01222489A (en) Manufacture of semiconductor device
JPH06302834A (en) Manufacture of thin-film structure
JPH02260333A (en) Manufacture of micro mechanical switch
JPS63177605A (en) Piezoelectric thin film resonator
JP3896780B2 (en) Manufacturing method of liquid crystal display device
JPH07101743B2 (en) Method for manufacturing semiconductor pressure sensor
JPH0797642B2 (en) Method for manufacturing pressure transducer
JPH05203519A (en) Manufacture of pressure sensor
JPH04240762A (en) Manufacture of stacked semiconductor device
JPH02281760A (en) Manufacture of single crystal thin-film member
JPH02199825A (en) Manufacture of electrode
JPH10284737A (en) Manufacture of capacitive semiconductor sensor
JPH04329676A (en) Manufacture of semiconductor acceleration sensor
JPH11340189A (en) Method for forming recess or through hole in micromachine production
JP2000077680A (en) Mesa structure and forming method thereof and mesa diaphragm and pressure sensor using the same