JPH02251140A - Thin film formation device - Google Patents
Thin film formation deviceInfo
- Publication number
- JPH02251140A JPH02251140A JP7216489A JP7216489A JPH02251140A JP H02251140 A JPH02251140 A JP H02251140A JP 7216489 A JP7216489 A JP 7216489A JP 7216489 A JP7216489 A JP 7216489A JP H02251140 A JPH02251140 A JP H02251140A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- substrate
- conductive thin
- bias voltage
- bias
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 83
- 230000015572 biosynthetic process Effects 0.000 title description 4
- 239000000758 substrate Substances 0.000 claims abstract description 73
- 238000004544 sputter deposition Methods 0.000 claims abstract description 36
- 239000004065 semiconductor Substances 0.000 abstract description 16
- 230000002159 abnormal effect Effects 0.000 abstract description 12
- 239000010408 film Substances 0.000 abstract description 10
- 238000009825 accumulation Methods 0.000 abstract description 7
- 210000000078 claw Anatomy 0.000 description 11
- 238000000034 method Methods 0.000 description 11
- 239000011248 coating agent Substances 0.000 description 8
- 238000000576 coating method Methods 0.000 description 8
- 238000002788 crimping Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 238000003825 pressing Methods 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- -1 tungsten (W) Chemical class 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置製造工程で用いられる、配線用導電
性薄膜形成装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an apparatus for forming a conductive thin film for wiring, which is used in a semiconductor device manufacturing process.
（発明の概要〕
本発明は半導体装置製造工程で用いられる、配線用導電
性薄膜形成装置に関し、更に詳しくは、バイアススパッ
タリング法により、導電性薄膜を形成する際の異常放電
を防止し、高品位の導電性薄膜の形成を可能とする薄膜
形成装置に関する。(Summary of the Invention) The present invention relates to an apparatus for forming a conductive thin film for wiring, which is used in a semiconductor device manufacturing process. The present invention relates to a thin film forming apparatus capable of forming a conductive thin film.
ＬＳＩ等の半導体装置は、その高集積度化、高速度化に
伴い、配線パターンの微細化および多層化が進んでいる
。多層配線における接続孔のアスペクト比は、例えば１
以上と大きくなってきており、深い接続孔や段差部分を
配線用導電材で埋め込む技術の重要性が高まってきた。2. Description of the Related Art As semiconductor devices such as LSIs become more highly integrated and operate at higher speeds, wiring patterns are becoming increasingly finer and multilayered. The aspect ratio of contact holes in multilayer wiring is, for example, 1
As the size of interconnects has increased, the importance of technology for filling deep connection holes and stepped portions with conductive material for wiring has increased.
多層配線形成に用いられる導電材としては、アルミニウ
ム（Ａ１）やその合金、タングステン（Ｗ）等の高融点
金属やそのシリサイド、あるいはポリシリコン等が用い
られ、ｍｌ形成にはスパッタリングによる方法が主とし
て用いられている。しかしこの方法は、アスペクト比の
大きな接続孔や段差部分等の底部には、いわゆるシャド
ウィング効果のため、配線用材料が充分に堆積されず、
被覆特性に限界があった。このため、接続孔や段差部分
での断線や、大電流密度でのエレクトロマイグレーショ
ンの発生など配線の信頼性に欠けるきらいがあった。The conductive materials used for forming multilayer wiring include aluminum (A1), its alloys, high-melting point metals such as tungsten (W), their silicides, and polysilicon, and sputtering is mainly used for ML formation. It is being However, with this method, the wiring material is not deposited sufficiently at the bottom of contact holes or stepped portions with large aspect ratios due to the so-called shadowing effect.
There were limits to the coating properties. For this reason, the reliability of the wiring tends to be poor, such as disconnections at connection holes or stepped portions, and electromigration at high current densities.
そこで前記被覆特性を改善するため、Ｓｉ等の半導体基
体にバイアス電圧を印加しながら、導電性薄膜を形成す
るバイアススパッタリング法がある。In order to improve the coating characteristics, there is a bias sputtering method in which a conductive thin film is formed while applying a bias voltage to a semiconductor substrate such as Si.
バイアス電圧としては、負のＤＣ電圧を印加する場合と
、ＲＦ雷電圧印加する場合があるが、目的とするところ
は同一である。バイアススパッタリング法においては、
基体側にもアルゴンイオン（Ａｒ′″）等のスパッタリ
ングガスイオンが入射する。このため、基体に一度堆積
した導電性薄膜の再スパツタリングが起こったり、ある
いは主として基体温度上昇によるマイグレーションが起
こる。As the bias voltage, there are cases where a negative DC voltage is applied and cases where an RF lightning voltage is applied, but the purpose is the same. In bias sputtering method,
Sputtering gas ions such as argon ions (Ar''') are also incident on the substrate side.As a result, re-sputtering of the conductive thin film once deposited on the substrate occurs, or migration occurs mainly due to an increase in substrate temperature.
これらの効果により、深い接続孔や段差等の底部へも導
電材が入り込み、導電性薄膜の被覆特性が向上するので
ある（例えば発明者らによる総説、月刊Ｓｅｍ１ｃｏｎ
ｄｕｃｔｏｒ Ｗｏｒｌｄ誌、１９８８年２月号、Ｐ、
７７参照）。Due to these effects, the conductive material penetrates into the bottom of deep connection holes and steps, improving the coating characteristics of the conductive thin film (for example, a review by the inventors, Monthly Sem1con).
ductor World magazine, February 1988 issue, P.
77).
上記したバイアススパッタリング法によれば、導電性薄
膜の被覆特性は改善されるが、通常大部分は絶縁物であ
る半導体基体表面に入射するＡｒ’等の電荷の蓄積によ
り、しばしば異常放電が発生する現象があった。この現
象が発生すると、半導体等の基体に損傷を与えたり、導
電性薄膜の膜質が悪化したりして、半導体装置製造工程
上の歩留まりの低下の原因の一つとなっていた。According to the bias sputtering method described above, the coating characteristics of the conductive thin film are improved, but abnormal discharge often occurs due to the accumulation of charges such as Ar' that are incident on the surface of the semiconductor substrate, which is usually an insulator. There was a phenomenon. When this phenomenon occurs, it damages the substrate such as a semiconductor or deteriorates the quality of the conductive thin film, which is one of the causes of a decrease in yield in the manufacturing process of semiconductor devices.
この異常放電を回避するため、基体へのバイアス電圧の
印加なしに、通常のスパッタリング法で導電性薄膜を薄
く形成してから、次にバイアス電圧を印加して同種の、
あるいは異種材料からなる導電性薄膜を所定の厚さにバ
イアススパッタリングする、例えば日型アネルバ■製Ｉ
ＬＣ−１０１２Ｍｋ Ｕ等のごとき装置による、２段階
製膜法があった。この従来の２段階製膜法を、第５図な
いし第７図に基づき説明する。In order to avoid this abnormal discharge, a thin conductive film is formed by normal sputtering without applying a bias voltage to the substrate, and then a bias voltage is applied to form a thin conductive film of the same type.
Alternatively, a conductive thin film made of different materials is bias-sputtered to a predetermined thickness.
There was a two-step film forming method using equipment such as the LC-1012Mk U. This conventional two-step film forming method will be explained based on FIGS. 5 to 7.
第５図は、従来の薄膜形成装置の模式的断面図、第６図
は従来の薄膜形成装置の基体支持治具の概略断面図であ
る。シリコン半導体ウェハ等による基体１を金属材料よ
りなる基体取付台座３に載置し、第６図（ａ）のごとく
チタン（Ｔｉ）等の弾性金属材料よりなる基体支持治具
の爪４により圧着して固定する。基体１は第６図（ｂ）
に示すように、金属材料よりなる基体支持治具のリング
５等を介して、基体支持治具の爪４により圧着して固定
する場合もある。１２は平行平板型ＤＣバイアススパッ
タリング装置のスパッタリング室であり、前記基体１に
対向して例えば＾ｌやＡ１合金等導電製薄膜形成用カソ
ード１１が配置されている。カソード１１には、ＤＣパ
ワー電源１３より負のＤＣ電圧が印加される。一方、基
体取付台座３へは、ＤＣバイアス電源１４より同じく負
の、例えば−２００Ｖ程度のバイアス電圧を印加する。FIG. 5 is a schematic sectional view of a conventional thin film forming apparatus, and FIG. 6 is a schematic sectional view of a substrate support jig of the conventional thin film forming apparatus. A base 1 made of a silicon semiconductor wafer or the like is placed on a base mounting pedestal 3 made of a metal material, and as shown in FIG. and fix it. The base 1 is shown in FIG. 6(b).
As shown in FIG. 2, the substrate may be fixed by being crimped by the claws 4 of the substrate support jig through a ring 5 or the like of the substrate support jig made of a metal material. Reference numeral 12 denotes a sputtering chamber of a parallel plate type DC bias sputtering apparatus, in which a cathode 11 for forming a conductive thin film, such as ^l or A1 alloy, is arranged opposite to the substrate 1. A negative DC voltage is applied to the cathode 11 from a DC power source 13 . On the other hand, a negative bias voltage of, for example, about -200V is applied to the base mounting pedestal 3 from the DC bias power supply 14.
すなわち、基体支持治具の爪４や基体支持治具のリング
５は、基体１表面にバイアス電圧を印加する機能をも兼
ねているのである。That is, the claws 4 of the substrate support jig and the ring 5 of the substrate support jig also have the function of applying a bias voltage to the surface of the substrate 1.
上述のように構成された従来の薄膜形成装置において、
スパッタ室１２に例えば数ｍＴｏｒｒの所定の圧力のＡ
ｒ等のスパッタリングガスを導入し、基体１を所定の温
度に予熱した後、まずＤＣバイアス電源１４の出力電圧
はＯｖとして通常のＤＣスパッタリングを行う。このよ
うにして基体１表面全体に例えば５００人程人程ごく薄
い第１の導電性薄膜２を形成して基体１表面を導電化し
ておいてから、次にＤＣバイアス電源１４の出力が電圧
を例えば２００ＶとしてＤＣバイアススパッタリングを
行い、例えば８０００人程度０所望の厚さに被覆特性に
優れた第２の導電性薄膜の形成を行うのである。In the conventional thin film forming apparatus configured as described above,
A predetermined pressure of several mTorr, for example, is applied to the sputtering chamber 12.
After introducing a sputtering gas such as R and preheating the substrate 1 to a predetermined temperature, first, the output voltage of the DC bias power supply 14 is set to Ov, and normal DC sputtering is performed. In this way, a very thin first conductive thin film 2 of, for example, about 500 layers is formed on the entire surface of the substrate 1 to make the surface of the substrate 1 conductive, and then the output of the DC bias power supply 14 is applied to For example, DC bias sputtering is performed at 200 V to form a second conductive thin film having excellent coating properties to a desired thickness of about 8,000 V, for example.
前記した２段階成膜法によれば、基体１表面はごく薄い
第１の導電性薄膜により導電化してから、引き続きバイ
アススパッタリングが形成されるので、基体１表面への
電荷の蓄積による異常放電は減少する。しかし、この２
段階成膜法によっても必ずしも異常放電を完全になくす
までには至っていなかった。According to the above-described two-step film formation method, the surface of the substrate 1 is made conductive by the extremely thin first conductive thin film, and then bias sputtering is performed, so that abnormal discharge due to charge accumulation on the surface of the substrate 1 is prevented. Decrease. However, these two
Even the stepwise film formation method has not always been able to completely eliminate abnormal discharge.
この原因について、発明者は詳細に検討した結果、次の
結論を得るに至った。すなわち、従来の薄膜形成装置の
基体支持治具部分における第１の導電性薄膜を示す断面
図である第７図において、同図（ａ）は基体支持治具の
爪４により、また同図（ｂ）は基体支持治具のリング５
を介して基体支持治具の爪４により基体１を圧着して固
定した場合である。同図に見られるように、通常のスパ
ッタリング法による第１の導電性薄膜２は、基体支持治
具の爪４や基体支持リング５と基体１とが接する開部分
においては、被覆特性の悪さから、膜厚が極端に薄く形
成されるか、あるいはほとんど形成されないことが判明
した。このため、引き続きバイアススパッタリング法に
より第２の導電性薄膜を形成するに際して、基体１表面
へ蓄積される電荷は、支持治具の爪４や支持治具のリン
グ５を介してスムーズに逃げることができない。従って
、異常放電を完全になくすには至らなかったのである。As a result of detailed study of this cause, the inventor came to the following conclusion. That is, in FIG. 7, which is a cross-sectional view showing the first conductive thin film in the substrate support jig portion of a conventional thin film forming apparatus, FIG. b) is the ring 5 of the base support jig.
This is a case where the base body 1 is crimped and fixed by the claws 4 of the base support jig via the base body support jig. As can be seen in the figure, the first conductive thin film 2 formed by the usual sputtering method has poor coating properties in the open areas where the claws 4 of the substrate support jig or the substrate support ring 5 and the substrate 1 are in contact with each other. It has been found that the film is formed extremely thin or is hardly formed at all. Therefore, when the second conductive thin film is subsequently formed by the bias sputtering method, the charges accumulated on the surface of the substrate 1 cannot smoothly escape through the claws 4 of the support jig and the ring 5 of the support jig. Can not. Therefore, it has not been possible to completely eliminate abnormal discharge.
よって、本発明の課題は、半導体等の基体上にバイアス
スパッタリング法により導電性’ｉｉｌ膜を形成する際
において、Ａｒ“等のスパッタリングガスイオンの入射
に起因する基体表面の電荷蓄積による異常放電をなくす
ことが可能な薄膜形成装置を提供することにある。Therefore, an object of the present invention is to prevent abnormal discharge due to charge accumulation on the surface of the substrate due to incidence of sputtering gas ions such as Ar, when forming a conductive 'IIL film on a substrate such as a semiconductor by bias sputtering. It is an object of the present invention to provide a thin film forming apparatus that can be eliminated.
［課題を解決するための手段］
本発明による薄膜形成装置は、半導体等の基体上にバイ
アススパッタリング法により導電性薄膜を形成する薄膜
形成装置において、基体上に形成された導電性薄膜表面
に直接に接触が可能なバイアス電圧印加端子を、基体支
持治具、すなわち基体支持治具の爪あるいは基体支持治
具のリングとは別体に配設することを特徴とする。[Means for Solving the Problems] A thin film forming apparatus according to the present invention is a thin film forming apparatus that forms a conductive thin film on a substrate such as a semiconductor by a bias sputtering method. The present invention is characterized in that a bias voltage application terminal that can come into contact with the substrate support jig is provided separately from the substrate support jig, that is, the claw of the substrate support jig or the ring of the substrate support jig.
本発明の薄膜形成装置により、導電性薄膜を形成する場
合には、まずバイアス電圧印加端子を基体から離して、
無バイアスの通常のスパッタリング法により第１の導電
性薄膜を薄く、すなわち基体表面の導電性がとれる程度
に形成する。次にバイアス電圧印加端子を形成された第
１の導電性薄膜表面に接触させ、バイアス電圧を第１の
導電性薄膜に印加しながら、第２の導電性薄膜を所望の
厚さにバイアススパッタリングするのである。When forming a conductive thin film using the thin film forming apparatus of the present invention, first, the bias voltage application terminal is separated from the substrate.
The first conductive thin film is formed to be thin enough to maintain conductivity on the surface of the substrate by a normal sputtering method without bias. Next, a bias voltage application terminal is brought into contact with the surface of the formed first conductive thin film, and while a bias voltage is applied to the first conductive thin film, a second conductive thin film is bias-sputtered to a desired thickness. It is.
バイアス電圧印加端子は、基体上に薄く形成された第１
の導電性薄膜表面に直接に接触する。このため、引き続
くバイアススパッタリングによる第２の導電性薄膜の形
成に際して、基体上に蓄積される電荷は、バイアス電圧
印加端子を経由してスムーズに基体表面から逃げること
ができ、異常放電をなくすことが可能となる。The bias voltage application terminal is a first terminal formed thinly on the base.
in direct contact with the conductive thin film surface. Therefore, when forming the second conductive thin film by subsequent bias sputtering, the charges accumulated on the substrate can smoothly escape from the substrate surface via the bias voltage application terminal, making it possible to eliminate abnormal discharge. It becomes possible.
以下、本発明の具体的な実施例について、図面を参照し
ながら説明する。なお、実施例を示す図面において、前
述した従来例と同じ機能を有する部分については、同じ
名称と番号を付しである。Hereinafter, specific embodiments of the present invention will be described with reference to the drawings. In the drawings showing the embodiment, parts having the same functions as those of the conventional example described above are given the same names and numbers.
夫旌拠土
第１図は本発明の第１の実施例による薄膜形成装置の模
式的断面図であり、その構成は前述した第５図の従来の
バイアススパッタリング装置の模式的断面図に準拠して
いるが、バイアス電圧印加端子６を、基体支持治具の爪
４や基体支持治具のリング５と別体に配設した点におい
て異なっている。これを本発明の実施例による薄膜形成
装置のバイアス電圧印加端子の平面配置図である第２図
に基づき説明する。同図は、カソード１１側から基体１
表面を見た模式的平面配置図であり、バイアス電圧印加
端子６が、基体支持治具の爪４や図示せざる基体支持治
具のリング５とは別体に配設されている。なお、基体支
持治具の爪４とバイアス電圧印加端子６の平面的な位置
関係については、第１図と第２図とは相違しているが、
これは図面の説明の都合上によるものであり、本発明の
本質とするところとは無関係である。バイアス電圧印加
端子６は、１カ所あるいは複数カ所配設してもよく、基
体１表面に任意に接触状態と非接触状態とを取りうるよ
うに構成されている。この構成を本発明の第１の実施例
による薄膜形成装置のバイアス電圧印加端子の動作説明
図である第３図に基づき説明する。FIG. 1 is a schematic cross-sectional view of a thin film forming apparatus according to a first embodiment of the present invention, and its configuration is based on the schematic cross-sectional view of the conventional bias sputtering apparatus shown in FIG. However, the difference is that the bias voltage application terminal 6 is provided separately from the claw 4 of the substrate support jig and the ring 5 of the substrate support jig. This will be explained based on FIG. 2, which is a plan layout diagram of bias voltage application terminals of a thin film forming apparatus according to an embodiment of the present invention. The figure shows the substrate 1 from the cathode 11 side.
This is a schematic plan layout diagram when looking at the front surface, and the bias voltage application terminal 6 is arranged separately from the claw 4 of the substrate support jig and the ring 5 of the substrate support jig (not shown). Note that the planar positional relationship between the claw 4 of the substrate support jig and the bias voltage application terminal 6 is different between FIG. 1 and FIG.
This is for convenience of explanation of the drawings and has nothing to do with the essence of the present invention. The bias voltage application terminal 6 may be provided at one location or at a plurality of locations, and is configured so that it can be in contact or non-contact with the surface of the base 1 as desired. This configuration will be explained based on FIG. 3, which is a diagram illustrating the operation of the bias voltage application terminal of the thin film forming apparatus according to the first embodiment of the present invention.
基体取付台座３の外周端部の凸起部には、ここを支点と
して略コの字形をした圧着レバー７が回動可能な状態で
図示せるごとく取付けられている。As shown in the figure, a substantially U-shaped crimping lever 7 is rotatably attached to the convex portion at the outer peripheral end of the base mounting pedestal 3, using the convex portion as a fulcrum.
圧着レバー７は、その端部が通常はスプリング８の縮小
偏寄力により第３図（ｂ）のごとく基体１の表面に接触
するように構成されている。また圧着レバー７の他端に
はバイアス電圧印加配線１ｏが接続されており、バイア
ス電圧は直接に基体１の表面に印加が可能となっている
。９はブツシュロッドであり、圧着レバー７の他端を押
すことにより、第３図（ａ）のごとく圧着レバー７の端
部が基体１表面から離れるように構成されている。ブツ
シュロッド９．の他端は、第１図に示されるように例え
ばメカニカルシールを介してスパッタ室１２外部へ導出
してマニュアルで押圧力を加えてもよいし、また例えば
スパッタ室１２内部に気密にシールされた電磁ソレノイ
ドを配設し、電磁力により押圧力を加えてもよい。以上
説明を加えた圧着レバー７、スプリング８、ブツシュロ
ッド９およびバイアス電圧印加配線１０によりバイアス
電圧印加端子６が構成されている。The crimping lever 7 is configured such that its end comes into contact with the surface of the base 1, as shown in FIG. 3(b), usually by the compressive biasing force of the spring 8. Further, a bias voltage application wiring 1o is connected to the other end of the crimp lever 7, so that the bias voltage can be applied directly to the surface of the base 1. Reference numeral 9 denotes a bushing rod, which is configured such that when the other end of the crimping lever 7 is pushed, the end of the crimping lever 7 is separated from the surface of the base 1, as shown in FIG. 3(a). Butschrod9. The other end may be led out to the outside of the sputtering chamber 12 via, for example, a mechanical seal and a pressing force may be applied manually, as shown in FIG. An electromagnetic solenoid may be provided to apply the pressing force by electromagnetic force. The bias voltage application terminal 6 is constituted by the crimp lever 7, the spring 8, the bushing rod 9, and the bias voltage application wiring 10 described above.
本実施例の薄膜形成装置により、基体１上にバイアスス
パッタリング法により導電性薄膜を形成する方法を次に
説明する。Next, a method of forming a conductive thin film on the substrate 1 by bias sputtering using the thin film forming apparatus of this embodiment will be described.
シリコン半導体等の基体１を基体取付台座３に載置し、
従来のバイアススパッタリング装置に準じて基体支持治
具の爪４あるいは基体支持治具のリング５を介して基体
支持治具の爪４により圧着して固定する。スパッタリン
グ室１２にＡｒ等のスパッタリングガスを導入乙、例え
ば数ｍＴｏｒｒの圧力に図示せざる真空ポンプで減圧排
気し、基体１を例えば１５０°Ｃに前加熱する。A substrate 1 such as a silicon semiconductor is placed on a substrate mounting pedestal 3,
In accordance with a conventional bias sputtering apparatus, the substrate is fixed by pressure bonding with the claws 4 of the substrate support jig via the claws 4 of the substrate support jig or the ring 5 of the substrate support jig. A sputtering gas such as Ar is introduced into the sputtering chamber 12 and evacuated to a pressure of, for example, several mTorr using a vacuum pump (not shown), and the substrate 1 is preheated to, for example, 150°C.
ＤＣバイアス電源１４の出力電圧はＯｖとし、ＤＣパワ
ー電源１３の出力電力は例えば７．８ＫＷとして、通常
のスパッタリング法によりＡ１やＡ１合金等の第１の導
電性薄膜２を、例えば５００人の厚さで基体１の表面全
面に形成する。このとき、バイアス電圧印加端子６の圧
着レバー７の端部は、ブツシュロッド９の押圧力により
第３図（ａ）のごと（基体１から充分に離しておく。次
にブツシュロフト９の押圧力を開放し圧着レバー７の端
部を基体１表面に形成された第１の導電性薄膜２に第３
図（ｂ）のごとく接触させ、ＤＣバイアス電源１４の出
力電圧を例えば−２００Ｖ、、ＤＣパワー電源１３の出
力電力を例えば７．８ＫＷとして、バイアススパッタリ
ングによりＡＩやＡ１合金等の第２の導電性薄膜を例え
ば８０００人の厚さに第１の導電性薄膜２上に形成する
。The output voltage of the DC bias power supply 14 is set to Ov, the output power of the DC power supply 13 is set to, for example, 7.8KW, and the first conductive thin film 2 of A1 or A1 alloy is deposited to a thickness of, for example, 500 mm by a normal sputtering method. Then, it is formed on the entire surface of the substrate 1. At this time, the end of the crimp lever 7 of the bias voltage application terminal 6 is kept sufficiently away from the base 1 by the pressing force of the bushing rod 9 (as shown in FIG. 3(a)).Next, the pressing force of the bushing loft 9 is released. The third end of the crimp lever 7 is attached to the first conductive thin film 2 formed on the surface of the base 1.
With the output voltage of the DC bias power supply 14 set to, for example, -200V, and the output power of the DC power supply 13 set to, for example, 7.8KW, the second conductive material such as AI or A1 alloy is A thin film is formed on the first conductive thin film 2 to a thickness of, for example, 8000 mm.
基体１へのＡｒ”の入射に基づく電荷の蓄積は、第１の
導電性薄膜２、圧着レバー７およびバイアス電圧印加配
線１０を経由してスムーズにアースされて逃げ、異常放
電を生ずることなくＡＩやＡ１合金からなる高品位の導
電性薄膜が形成された。本実施例による導電性薄膜は、
基体１に予め形成されていた接続孔や段差部分を滑らか
に平坦化しており、被覆特性に優れたものであった。Accumulation of charge due to the incidence of Ar on the base 1 is smoothly grounded and escapes via the first conductive thin film 2, the crimping lever 7, and the bias voltage application wiring 10, and the AI A high-quality conductive thin film made of A1 alloy was formed.The conductive thin film according to this example was
The connection holes and stepped portions previously formed in the base body 1 were smoothed and flattened, and the coating properties were excellent.
尖旌±業
本発明の第２の実施例による薄膜形成装置は、基体支持
治具とは別体に設けたバイアス電圧印加端子の形状に変
更がある他は、実施例１に準拠したものであるので、こ
のバイアス電圧印加端子部分を主として詳述する。なお
実施例１と同し機能を有する部分については、説明の図
面中で同じ番号と名称を付している。The thin film forming apparatus according to the second embodiment of the present invention is based on the first embodiment, except that the shape of the bias voltage application terminal provided separately from the substrate support jig is changed. Therefore, this bias voltage application terminal portion will be mainly described in detail. Note that parts having the same functions as those in the first embodiment are given the same numbers and names in the explanatory drawings.
第４図は本発明の第２の実施例による薄膜形成装置の模
式的断面図である。同図において、基体取付台座３の周
端部の孔を貫通して、断面が略り字型をした圧着レバー
７が配設されている。圧着レバー７の一端は、通常はス
プリング８の伸長偶奇力により第４図（ｂ）のごとく基
体１の表面に接触し、また圧着レバー７の他端をブツシ
ュロッド９により押圧すれば同図（ａ）のごとく基体１
の表面より離れるように構成されている。ブツシュロッ
ド９の押圧機構は、実施例１に準じており、基体１の裏
側から、すなわち基体１に対してカソード１１の反対側
から押圧力を加える点においてのみ異なっている。FIG. 4 is a schematic cross-sectional view of a thin film forming apparatus according to a second embodiment of the present invention. In the figure, a crimping lever 7 having an abbreviated cross-section is disposed so as to pass through a hole in the peripheral end of the base mounting pedestal 3. One end of the crimp lever 7 normally comes into contact with the surface of the base 1 as shown in FIG. ) as shown in the base 1
It is configured to be away from the surface of the The pressing mechanism of the bush rod 9 is similar to that of the first embodiment, and differs only in that the pressing force is applied from the back side of the base 1, that is, from the opposite side of the cathode 11 to the base 1.
本実施例の薄膜形成装置により基体１上にバイアススパ
ッタリング法により導電性薄膜を形成する方法は、前述
した実施例１による方法と同様である。形成された導電
性薄膜は、基体１に予め形成されていた多層配線用の深
い接続孔や段差部分を滑らかに平坦化しており、被覆特
性に優れたものであった。The method of forming a conductive thin film on the substrate 1 by bias sputtering using the thin film forming apparatus of this example is the same as the method of Example 1 described above. The formed conductive thin film smoothly flattened the deep connection holes and stepped portions for multilayer wiring that had been previously formed on the substrate 1, and had excellent covering properties.
以上、本発明の薄膜形成装置につき具体的な２実施例を
取り上げて説明を加えてきたが、本発明はこれら実施例
に限定されるものではない。要は半導体等の基体上に形
成される導電性薄膜表面に直接接触可能なバイアス電圧
印加端子を、基体支持治具とは別体に配設したことを特
徴とするものであり、バイアス電圧印加端子の具体的な
形状と構成については、本発明の趣旨に沿った別の形状
と構成をとることが可能である。また本実施例において
は、バイアス電源としてＤＣバイアス電源を例にとり説
明したが、本発明の効果は、ＲＦバイアス電源において
も、同じく異常放電の防止を達成することが可能である
。Although two specific embodiments of the thin film forming apparatus of the present invention have been described above, the present invention is not limited to these embodiments. The key point is that a bias voltage application terminal that can directly contact the surface of a conductive thin film formed on a substrate such as a semiconductor is provided separately from the substrate support jig. Regarding the specific shape and configuration of the terminal, it is possible to adopt another shape and configuration consistent with the spirit of the present invention. Further, in this embodiment, the DC bias power supply is used as an example of the bias power supply, but the effects of the present invention can be similarly achieved in the RF bias power supply as well.
本発明の薄膜形成装置により、半導体等の基体上に導電
性薄膜のバイアススパッタリングを施すことにより、基
体表面へのＡｒ”″等スパッタリングガスイオンの入射
に基づく電荷の蓄積による異常放電を効果的に防止する
ことが可能となる。By performing bias sputtering of a conductive thin film on a substrate such as a semiconductor using the thin film forming apparatus of the present invention, abnormal discharge due to charge accumulation due to incidence of sputtering gas ions such as Ar on the substrate surface can be effectively prevented. It becomes possible to prevent this.
異常放電防止の効果は、従来のバイアススパンタリング
薄膜形成装置による２段階成膜法に比べて、新たに配設
したバイアス電圧印加端子の機能により、著しく確実な
ものとなる。The effect of preventing abnormal discharge is much more reliable than the two-step film forming method using the conventional bias sputtering thin film forming apparatus due to the function of the newly provided bias voltage application terminal.
これにより、異常放電が半導体等の基体や形成される導
電性薄膜に与える損傷を回避することが可能となり、従
来被覆特性に優れるものの、工程の歩留まりの点におい
て、実用化が遅れていたバイアススパッタリング法によ
る薄膜形成装置の信頼性が向上し、本発明の半導体装置
製造工程に及ぼず寄与が大きい。This makes it possible to avoid damage caused by abnormal discharges to substrates such as semiconductors and the conductive thin film formed. Bias sputtering, which conventionally has excellent coating properties but has lagged behind in practical application in terms of process yield, The reliability of the thin film forming apparatus using the method is improved, and the contribution is greater than that of the semiconductor device manufacturing process of the present invention.
第１図は本発明の第１の実施例による薄膜形成装置の模
式的断面図、第２図は本発明の実施例による薄膜形成装
置のバイアス電圧印加端子の平面配置図、第３図は本発
明の第１の実施例による薄膜形成装置のバイアス電圧印
加端子の動作説明図、第４図は本発明の第２の実施例に
よる薄膜形成装置のバイアス電圧印加端子の動作説明図
、第５図は従来の薄膜形成装置の模式的断面図、第６図
は従来の薄膜形成装置の基体支持治具の概略断面図、そ
して第７図は従来の薄膜形成装置の基体支持冶具部分に
おける第１の導電性薄膜を示す断面図である。
一基体
第１の導電性薄膜
一基体取付台座
基体支持治具の爪
一基体支持治具のリング
バイアス電圧印加端子
圧着レバー
スプリング
プッシュロンド
・ＤＣパワー電源
々
☆
（ａ） 、 （ｂ）
従来の薄膜形成装置の
基体支持治具の柵錯直面図
第６図
従来の薄膜形成装置の模式的討面図
第５図
（ａ） （ｂ）
従来の薄膜形成装置の基体支持治具部分におけろ躬１の
導電性薄膜と示Ｔ百面図
第７図FIG. 1 is a schematic cross-sectional view of a thin film forming apparatus according to a first embodiment of the present invention, FIG. 2 is a plan view of a bias voltage application terminal of a thin film forming apparatus according to an embodiment of the present invention, and FIG. 3 is a schematic sectional view of a thin film forming apparatus according to a first embodiment of the present invention. FIG. 4 is an explanatory diagram of the operation of the bias voltage application terminal of the thin film forming apparatus according to the first embodiment of the invention, and FIG. 5 is an explanatory diagram of the operation of the bias voltage application terminal of the thin film forming apparatus according to the second embodiment of the invention. 6 is a schematic sectional view of a conventional thin film forming apparatus, FIG. 6 is a schematic sectional view of a substrate supporting jig of the conventional thin film forming apparatus, and FIG. 7 is a schematic cross sectional view of a substrate supporting jig of the conventional thin film forming apparatus. FIG. 2 is a cross-sectional view showing a conductive thin film. (a), (b) Conventional thin film Figure 6: Schematic cross-sectional view of a conventional thin film forming apparatus Figure 5 (a) (b) Faults in the substrate supporting jig portion of a conventional thin film forming apparatus 1 conductive thin film and T-hundred-view diagram Fig. 7
Claims (1)
形成する薄膜形成装置であって、 基体上に形成される導電性薄膜表面に直接に接触可能な
バイアス電圧印加端子を、基体支持治具とは別体に配設
したことを特徴とする薄膜形成装置。[Claims] A thin film forming apparatus for forming a conductive thin film on a substrate by a bias sputtering method, wherein a bias voltage application terminal that can directly contact the surface of the conductive thin film formed on the substrate is attached to the substrate support. A thin film forming device characterized by being installed separately from a jig.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7216489A JP2926740B2 (en) | 1989-03-24 | 1989-03-24 | Thin film forming equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7216489A JP2926740B2 (en) | 1989-03-24 | 1989-03-24 | Thin film forming equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02251140A true JPH02251140A (en) | 1990-10-08 |
| JP2926740B2 JP2926740B2 (en) | 1999-07-28 |
Family
ID=13481333
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7216489A Expired - Fee Related JP2926740B2 (en) | 1989-03-24 | 1989-03-24 | Thin film forming equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2926740B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007114190A1 (en) * | 2006-03-30 | 2007-10-11 | Hoya Corporation | Film deposition equipment and method for producing magnetic disc |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009081952A1 (en) | 2007-12-26 | 2009-07-02 | Canon Anelva Corporation | Substrate holder, film forming method using substrate holder, method for manufacturing hard disc, film forming apparatus and program |
-
1989
- 1989-03-24 JP JP7216489A patent/JP2926740B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007114190A1 (en) * | 2006-03-30 | 2007-10-11 | Hoya Corporation | Film deposition equipment and method for producing magnetic disc |
| JP2007270189A (en) * | 2006-03-30 | 2007-10-18 | Hoya Corp | Film-forming apparatus and method for manufacturing magnetic disk |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2926740B2 (en) | 1999-07-28 |
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