JPH0225111A - Phase locked oscillator - Google Patents
Phase locked oscillatorInfo
- Publication number
- JPH0225111A JPH0225111A JP63173655A JP17365588A JPH0225111A JP H0225111 A JPH0225111 A JP H0225111A JP 63173655 A JP63173655 A JP 63173655A JP 17365588 A JP17365588 A JP 17365588A JP H0225111 A JPH0225111 A JP H0225111A
- Authority
- JP
- Japan
- Prior art keywords
- bias voltage
- voltage
- phase comparator
- bias
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005070 sampling Methods 0.000 claims abstract description 14
- 230000001360 synchronised effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は通信機の局部発振器などに用いられる位相同期
発振器に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a phase synchronized oscillator used as a local oscillator of a communication device.
（従来の技術）
従来の位相同期発振器は第３図に示すような構成であっ
た。同図において、入力端子２１に加えられる基準信号
と電圧制御発振器２２の出力をサンプリング位相比較器
２３により位相比較し、サンプリング位相比較器２３の
出力をループフィルタ２４に入力し、ループフィルタ２
４の出力を電圧制御発振器２２の入力端子に印加し、電
圧制御発振器２２の出力端子２５から出力信号を得るよ
うに構成し、抵抗器２６と抵抗器２７を直列に接続して
なるバイアス回路２８を備え、抵抗器２６と抵抗器２７
の接続点からループフィルタ２４にバイアス電圧２９を
与えていた。３０は電源電圧である。(Prior Art) A conventional phase synchronized oscillator has a configuration as shown in FIG. In the figure, a reference signal applied to an input terminal 21 and the output of a voltage controlled oscillator 22 are phase-compared by a sampling phase comparator 23, and the output of the sampling phase comparator 23 is inputted to a loop filter 24.
4 is applied to the input terminal of the voltage controlled oscillator 22 and an output signal is obtained from the output terminal 25 of the voltage controlled oscillator 22, and a bias circuit 28 is formed by connecting a resistor 26 and a resistor 27 in series. and a resistor 26 and a resistor 27
A bias voltage 29 was applied to the loop filter 24 from the connection point. 30 is a power supply voltage.
（発明が解決しようとする課題）
上記、従来の構成の位相同期発振器では、電源電圧が一
定であり、温度が一定の場合はバイアス電圧によって、
前記サンプリン・グ位相比較器の出力オフセットの補償
をすることはできるが、Ｗｉ電源電圧温度が変動すれば
、前記バイアス電圧も変動し、前記サンプリング位相比
較器の出力オフセットの補償が不十分になり、同期外れ
が生じる欠点があった。(Problems to be Solved by the Invention) In the above conventional phase-locked oscillator, when the power supply voltage is constant and the temperature is constant, the bias voltage causes
Although it is possible to compensate for the output offset of the sampling phase comparator, if the Wi power supply voltage temperature fluctuates, the bias voltage also fluctuates, and the compensation for the output offset of the sampling phase comparator becomes insufficient. However, there was a drawback that synchronization could occur.
本発明の目的は、従来の欠点を解消し、電源電圧変動や
温度変動がある場合でも確実に同期を保持することであ
る。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art and to reliably maintain synchronization even in the presence of power supply voltage fluctuations and temperature fluctuations.
（課題を解決するための手段）
本発明の位相同期発振器は、入力基準信号と電圧制御発
振器の出力とをサンプリング位相比較器で位相比較し、
そのサンプリング位相比較器の出力をループフィルタに
入力し、このループフィルタの出力を、前記電圧制御発
振器の入力端子に印加し、その電圧制御発振器の出力端
子から出力信号を得るように構成し、バイアス回路より
ループフィルタに第１のバイアス電圧を、前記サンプリ
ング位相比較器に第２のバイアス電圧を与え、この第２
のバイアス電圧が、第１のバイアス電圧の変動に追随し
て変動するものである。(Means for Solving the Problems) The phase synchronized oscillator of the present invention compares the phases of the input reference signal and the output of the voltage controlled oscillator using a sampling phase comparator,
The output of the sampling phase comparator is input to a loop filter, the output of the loop filter is applied to the input terminal of the voltage controlled oscillator, and an output signal is obtained from the output terminal of the voltage controlled oscillator. A circuit applies a first bias voltage to the loop filter, a second bias voltage to the sampling phase comparator, and the second bias voltage is applied to the loop filter.
The bias voltage of the first bias voltage varies in accordance with the variation of the first bias voltage.
（作 用）
上記、技術的手段により、電源電圧変動や温度変動のた
めに、ループフィルタのバイアス電圧が変化しても、こ
の変化に追随して、サンプリング位相比較器のバイアス
電圧も変化するため、サンプリング位相比較器の出力オ
フセットは補償され、安定に同期を保持することができ
る。(Function) With the technical means described above, even if the bias voltage of the loop filter changes due to fluctuations in power supply voltage or temperature, the bias voltage of the sampling phase comparator will also change following this change. , the output offset of the sampling phase comparator is compensated, and synchronization can be stably maintained.
（実施例）
本発明の一実施例を第１図および第２図に基づいて説明
する。(Example) An example of the present invention will be described based on FIGS. 1 and 2.
第１図は本発明の位相同期発振器のブロック図である。FIG. 1 is a block diagram of a phase-locked oscillator according to the present invention.
同図において、１は位相比較器で、入力端子２に加えら
れる入力基準信号と電圧制御発振器３の出力とを位相比
較する。４はループフィルタであり、位相比較器１の出
力より雑音や高調波成分を除いた信号を得る。５はバイ
アス回路であり、第１のバイアス電圧６をループフィル
タ４に与え、また第２のバイアス電圧７を位相比較器１
に与える。８は出力端子である。In the figure, reference numeral 1 denotes a phase comparator, which compares the phases of an input reference signal applied to an input terminal 2 and the output of a voltage controlled oscillator 3. 4 is a loop filter, which obtains a signal from the output of the phase comparator 1 from which noise and harmonic components are removed. 5 is a bias circuit which applies a first bias voltage 6 to the loop filter 4 and a second bias voltage 7 to the phase comparator 1.
give to 8 is an output terminal.
バイアス回路５の構成を第２図に示す。同図において、
９ 、１０．１１．１２．１３．１４はそれぞれ第１゜
第２．第３．第４、第５．第６の抵抗器であり、第１の
抵抗器９や第２の抵抗器１０の抵抗値に比べて第３．第
４．第５．第６の抵抗器１１．１２．１３゜１４の抵抗
値は十分小さい。The configuration of the bias circuit 5 is shown in FIG. In the same figure,
9, 10.11.12.13.14 are the 1st and 2nd, respectively. Third. 4th, 5th. It is the sixth resistor, and is the third resistor compared to the resistance value of the first resistor 9 and the second resistor 10. 4th. Fifth. The resistance value of the sixth resistor 11, 12, 13° 14 is sufficiently small.
つぎに動作を説明する０位相比較器１で生じるオフセッ
ト電圧をｖｏ、第１のバイアス電圧６をｖｌ、第２のバ
イアス電圧７をｖ２とする。まず温度変動や電源電圧変
動がない場合、位相比較器１で生じるオフセット電圧（
Ｖ、）と第２のバイアス電圧７ （Ｖａ）を加算した電
圧（ｖ ｏ ＋ Ｖ ２ ）を補償するように、第１の
バイアス電圧６ （Ｖ工）を調整しておく、つぎに電圧
変動がある場合は抵抗器９，１０に比べて抵抗器１１．
１２．１３．１４の抵抗値が十分大きいので、第２のバ
イアス電圧７ （Ｖ２）は第１のバイアス電圧６ （Ｖ
工）に追従して変動し、Ｖ、 ＋ Ｖ、はｖｌにより補
償されるバイアス位相比較器１のバイアス電圧はループ
フィルタ４のバイアス電圧に追随するため補償されるこ
とになる。Next, let us say that the offset voltage generated in the 0-phase comparator 1 whose operation will be explained is vo, the first bias voltage 6 is vl, and the second bias voltage 7 is v2. First, if there are no temperature fluctuations or power supply voltage fluctuations, the offset voltage (
The first bias voltage 6 (V) is adjusted so as to compensate for the voltage (vo + V 2 ) which is the sum of the voltage (V, ) and the second bias voltage 7 (Va), and then the voltage fluctuation If there is resistor 11. compared to resistors 9 and 10.
Since the resistance value of 12.13.14 is sufficiently large, the second bias voltage 7 (V2) is equal to the first bias voltage 6 (V
The bias voltage of the bias phase comparator 1 follows the bias voltage of the loop filter 4 and is therefore compensated.
（発明の効果）
本発明によれば、きわめて簡単な回路構成で、位相同期
を安定に保持することができ、その実用上の効果はきわ
めて大である。(Effects of the Invention) According to the present invention, phase synchronization can be stably maintained with an extremely simple circuit configuration, and its practical effects are extremely large.
第１図は本発明の一実施例における位相同期発振器のブ
ロック図、第２図は同バイアス回路の回路図、第３図は
従来の位相同期発振器のブロック図である。
１ ・・・位相比較器、 ２・・・入力端子、３・・・
電圧制御発振器、 ４ ・・・ループフィルタ、 ５
・・・バイアス回路、 ６・・・第１のバイアス電圧、
７ ・・・第２のバイアス電圧、 ８ ・・・出力端
子、 ９゜＋０．１１．１２．１３．１４・・・第１．
第２．第３、第４．第５．第６の抵抗器。
特許出願人 松下電器産業株式会社
第
図FIG. 1 is a block diagram of a phase-locked oscillator according to an embodiment of the present invention, FIG. 2 is a circuit diagram of the same bias circuit, and FIG. 3 is a block diagram of a conventional phase-locked oscillator. 1...Phase comparator, 2...Input terminal, 3...
Voltage controlled oscillator, 4...Loop filter, 5
...bias circuit, 6...first bias voltage,
7...Second bias voltage, 8...Output terminal, 9°+0.11.12.13.14...First.
Second. Third, fourth. Fifth. 6th resistor. Patent applicant: Matsushita Electric Industrial Co., Ltd.
Claims (1)
位相比較器で位相比較し、前記サンプリング位相比較器
の出力をループフィルタに入力し、前記ループフィルタ
の出力を、前記電圧制御発振器の入力端子に印加し、前
記電圧制御発振器の出力端子から出力信号を得るように
構成し、バイアス回路より、前記ループフィルタに第１
のバイアス電圧を、前記サンプリング位相比較器に第２
のバイアス電圧を与え、前記第２のバイアス電圧が、前
記第１のバイアス電圧の変動に追随して変動することを
特徴とする位相同期発振器。A sampling phase comparator compares the phases of the input reference signal and the output of the voltage controlled oscillator, inputs the output of the sampling phase comparator to a loop filter, and applies the output of the loop filter to the input terminal of the voltage controlled oscillator. and is configured to obtain an output signal from an output terminal of the voltage controlled oscillator, and a bias circuit supplies a first signal to the loop filter.
A second bias voltage of
A phase synchronized oscillator, characterized in that the second bias voltage varies in accordance with variations in the first bias voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63173655A JPH0225111A (en) | 1988-07-14 | 1988-07-14 | Phase locked oscillator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63173655A JPH0225111A (en) | 1988-07-14 | 1988-07-14 | Phase locked oscillator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0225111A true JPH0225111A (en) | 1990-01-26 |
Family
ID=15964645
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63173655A Pending JPH0225111A (en) | 1988-07-14 | 1988-07-14 | Phase locked oscillator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0225111A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6341935B2 (en) * | 1984-11-16 | 1988-08-19 | Mitsubishi Electric Corp |
-
1988
- 1988-07-14 JP JP63173655A patent/JPH0225111A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6341935B2 (en) * | 1984-11-16 | 1988-08-19 | Mitsubishi Electric Corp |
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