JPH02249049A - Information processor - Google Patents

Abstract

PURPOSE:To easily and smoothly terminate and resume a job and to preserve data at the time of termination even if a battery is not incorporated by using EEPROM as a memory for saving data. CONSTITUTION:A system bus is connected to EEPROM 14 having a capacity sufficient for saving various information in CPU 11 incorporated in a personal computer and all data in RAM 13. When a main switch is turned off at the termination time of the job, the content of CPU 11 and RAM 13 at that time is automatically saved top EEPROM 14. When the job is resumed, data of EEPROM 14 is automatically returned to CPU 11 and RAM 13 by turning on the main switch. Thus, the job after preceding termination can be continued and danger that data disappears owing to the interruption of the job for a long period is eliminated, whereby a high speed access is attained.

Description

Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to an information processing device such as a computer or a word processor.

(Prior Art) When a computer or word processor wants to temporarily end a task, a memory is required to save internal data at that point. Conventionally, magnetic memories such as magnetic disks and floppy disks have been generally used as such save memories. However, magnetic memory requires long access times. In contrast, DRAM, whose capacity has recently been increasing
Personal computers and word processors have been made that have built-in batteries and are used as backup memory. However, the built-in battery has a limited lifespan, and if the main switch is turned off for a long time, there is a risk of data loss due to battery life. Therefore, it is difficult to save data for a long time in DRAM.

(Problems to be Solved by the Invention) As described above, when magnetic memory is used as save memory in computers, word processors, etc., access time is long, and when DRAM is used, a built-in battery is required. However, there was a problem that there was a risk of data loss due to battery life.

It is an object of the present invention to provide an information processing device equipped with a save memory that solves such problems.

[Structure of the Invention] (Means for Solving the Problems) An information processing device according to the present invention includes a CPU and a RAM as the minimum necessary configuration, and further includes a CPU and a RAM at the end of the production process.
Electrically rewritable non-volatile semiconductor memory (EEPROM) is used as a memory to save U and RAM data.
).

(Function) According to the present invention, by turning off the main switch at the end of work, the contents of the CPU and RAM at that point are automatically saved to the EEPROM, and when restarting work, by turning on the main switch. It is possible to automatically return the EEPROM data to the CPU and RAM and continue the work that was completed last time. Moreover, since EEPROM can retain data even without power, DRA
Unlike when M is used for backup, there is no risk of data loss due to long work interruptions, and high-speed access is possible.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a system configuration of an embodiment in which the present invention is applied to a personal computer (or word processor). The basic configuration is CPU
II, RAM 13 and ROM 12. ROM1
A program for controlling the CPU 1 is written in the CPU 2. The CPU 11 executes the RA according to this control program.
It exchanges data with the MI 3, performs necessary arithmetic processing, and exchanges data with various external I10 devices 15. The ROM 12 is normally built-in, but may be an external memory. Connected to the system bus is an EEPROM 14 having a capacity sufficient to save various information (registers, program counters, psw, etc.) in the CPU II built into the personal computer and all data in the RAM 13.

In this embodiment, the EEPROM 14 is a NAND cell type EE.
It is PROM.

Figure 6 shows the NAND cell type EEPR used in this example.
FIG. 2 is a block diagram showing the configuration of OM. Chip enable terminal CE and output terminal are used as external control signal terminals.
Enable terminal OE and write enable terminal WE
and 18 address signal terminals A. -AH, has eight data input/output terminals l10o to I2O3, and has power supply terminals vcc and VSS. In this embodiment, the memory cell array 1 has a capacity of 4 Mbits and is made up of four memory cells collectively configured in a NAND type, as will be described later. Bit lines BLI to BLn+ of memory cell array 1
(m=2048) is connected to the sense amplifier/data latch circuit 5. Selection gate line 5Gln, 5G2n
and word lines WL1n-WL4n (n=512),
Connected to row decoder 3. The address signal is
The signal is input to a row decoder 3 and a column decoder 4 via an address buffer 2, thereby selecting an address.

During reading, the data output to the bit lines BLI to BLm is amplified and latched by the sense amplifier/data latch circuit 5, and then sent to the input/output terminal l10o-1 via the output buffer 6.
It is output to the outside from 10°.

When writing data, input/output terminals I10. The data input from -1107 is taken into the sense amplifier/data latch circuit 5 via the input buffer, and then written into the memory cell at the selected address.

8 is a control logic circuit that generates an internal control signal from an external control signal.

FIG. 7 is an equivalent circuit showing the configuration of the memory cell array 1. The memory cell Mij is a FETMOS type in which a floating gate and a control gate are stacked over the entire channel region with a thin gate insulating film interposed therebetween. For example, in the case of an n-channel, data erasing (or writing) is an operation that moves the threshold in the negative direction by applying a positive high voltage to the control gate and releasing electrons from the floating gate to the substrate by F-N tunneling. By keeping the control gate at "L" level and applying a positive high voltage to the drain, F-
By N tunneling? The operation of injecting electrons into the f free gate and moving the threshold value in the positive direction corresponds to data writing (or erasing).The high voltage used for data writing and erasing is applied to the row decoder 3. It is generated by a voltage divider circuit in the column decoder 4.These memory cells are so-called NAND cells, in which four memory cells are connected in series to form one block, with adjacent cells sharing the source and drain. It consists of

One end of the NAND cell is connected to the bit line BL via a selection gate Qs1, and the other end is connected to the source line VS via a selection gate Qs2. The memory cells are arranged in a matrix as shown, and the control gates of the memory cells in the row direction are commonly connected to the word line WL.

FIG. 8 is a timing chart during reading. Chip enable terminal CE and output enable terminal OE are set to “L” level, and write enable terminal W is set to “L” level.
By setting E to "H" level and changing the address, eight memory cell data are transferred to the human output line 1/Oo = I via the sense amplifier/data latch circuit 5.
Obtained on /07.

FIG. 9 is a timing chart during writing. By setting the chip enable terminal CE to the "L" level and the output enable terminal OE to the "H" level, and toggling the write enable terminal WE in synchronization with the address signal, the input from the input/output lines l10o-I2O3 is The data is latched into the sense amplifier/data latch circuit 5 via the input buffer, and sequentially written to selected addresses.

In such a NAND cell type EEPROM, multiple memory cells are collectively connected to a bit line, so the number of contacts with the bit line is significantly smaller than when each memory cell is connected to the bit line. It has the advantage of being extremely densely integrated.

Next, the operations at the end and restart of the work on the personal computer shown in FIG. 1 will be explained.

FIG. 2 is a flowchart showing the work within the system at the end of the work. When the work is completed, turn off the main switch, the CPU II will detect this and the ROMI
CPUI automatically according to the control program written in 2.
Write the data in I to EEPROM14 (P2)
Furthermore, the data in the RAM 1B is written to the EEPROM 14 (P3). Then, the power is turned off (P4).

FIG. 3 is a flowchart showing the system operations when work is restarted. When the main switch is turned on, the power is turned on and the CPU II detects these.
EEPROM according to the control program written in M12
The data in the CPUI 1 and the data in the RAM 13 that have been saved in the CPU 14 are returned to the CPUI 1 and the RAM 13, respectively (S2 and S3). This returns the system to the state it was in just before it was switched off, and normal operation can then be carried out.

According to this embodiment, the evacuated data can be saved without a power source. Therefore, there is no danger that occurs when data is saved using DRAM. Moreover, faster access is possible than with magnetic memory.

In the above embodiment, the evacuation EEPROM is built into the system, but it may be externally attached in the form of a cartridge (or card).

FIG. 4 shows the appearance of a personal computer of such an embodiment. The main body 21 is a CPU as in the previous embodiment.

Built-in RAM and ROM. In this embodiment, the main body 21 is also integrally formed with a keyboard 22 and a display 23 as an input section.

The evacuation EEPROM cartridge 24 is provided separately from the main body 21 and can be attached to the main body 21 as needed.

For example, as shown in FIG. 5, the EEFROM cartridge 24 includes an EEPROM 26 inside a protective case 25 and is provided with an input/output terminal section 27.

The operation of the system is similar to the previous embodiment. In other words, when the work is finished, the necessary data is transferred to the EEF by switching off.
The data is written to the ROM cartridge 24. When work resumes,
EEFROM cartridge 24 prior to switch on
is set in the main body 21. When the switch is turned on, the main body 21 reads the contents of the EEPROM cartridge 24 and is set up to the state at the time of completion of the work.

This embodiment also provides the same effects as the previous embodiment. Furthermore, if the EEFROM is in a cartridge format, the data saved in the EEFROM can be used in other devices as well.

[Effects of the Invention] As described above, according to the present invention, by using an EEPROM as a memory for saving data, it is possible to finish and restart work easily and smoothly, and there is no need to incorporate a battery. An information processing device is obtained which can save data at the time of termination.

[Brief Description of the Drawings] Fig. 1 is a block diagram showing a personal computer according to an embodiment of the present invention, Fig. 2 is a flowchart showing the operation at the end of the work, and Fig. 3 also shows the operation at the time of restarting the work. Flowchart, FIG. 4 is an external view showing a personal computer of another embodiment, FIG. 5 is a diagram showing its EEFROM cartridge, FIG. 6 is a block diagram showing the configuration of the NAND cell type EEPROM used in the embodiment, and FIG. 8 is an equivalent circuit diagram showing the memory cell array, FIG. 8 is a timing diagram for explaining the data read operation, and FIG. 9 is a timing diagram for explaining the data write operation. 11...CPU, 12...ROM, 13...RA
M. 14...EEPROM, 15...110 equipment, 21
...PC body, 22...Keyboard, 23...
・Display, 24...EE'PROM cartridge.

Claims (4)

[Claims] (1) In an information processing device that has at least a CPU and a RAM, the data in the CPU and the RAM at the end of the work
An information processing device comprising an EEPROM for saving data. (2) The information processing device according to claim 1, wherein the EEPROM is built into the device. (3) The information processing apparatus according to claim 1, wherein the EEPROM is a freely attachable cartridge. (4) EEPROM is a matrix in which a plurality of FETMOS type memory cells in which floating gates and control gates are stacked on a semiconductor substrate are connected in series so that adjacent cells share the source and drain to form a NAND cell. 2. The information processing device according to claim 1, wherein the memory cell array is configured such that the drains of the NAND cells at one end are connected to a bit line, and the control gates of each memory cell are connected to a word line.