KR0180117B1 - Non-volatile semiconductor memory - Google Patents

Abstract

1. The technical field to which the invention described in the claims belongs:

A nonvolatile semiconductor memory in a system.

2. The technical problem the invention is trying to solve:

The present invention provides a nonvolatile semiconductor memory and an input / output control method thereof that can prevent a failure that may occur when a read operation or a write operation is performed with a shared control pin.

3. Summary of the Solution of the Invention:

A nonvolatile semiconductor memory having a read enable signal pin shared with an output enable signal pin of a RAM capable of temporarily storing data, and configured to store data read from the RAM, may be used as the output enable signal pin. The data stored in the RAM output in response to the enable signal is applied by the chip enable signal, the write enable signal, and the internal write enable signal output by the first command flag enabled in the data input mode. And a write buffer for performing a storage operation and a read buffer for disabling the read operation in response to a second command flag enabled only in the data output mode in the data input mode.

4. Important uses of the invention:

It is suitably used for a system using a semiconductor memory.

Description

Nonvolatile Semiconductor Memory

1 is a pin connection diagram of a general nonvolatile semiconductor memory device.

2 is a schematic block diagram of a nonvolatile semiconductor memory and RAM having a common bus on a typical system.

3 is a block diagram schematically illustrating the correlation between each control buffer and data in a nonvolatile semiconductor memory according to the conventional art.

4 is a detailed circuit diagram of the read buffer shown in FIG.

5 is a detailed circuit diagram of the write buffer shown in FIG.

6 is a specific circuit diagram of the data output buffer shown in FIG.

7 is a timing diagram showing an input / output timing relationship according to the prior art.

8 is a timing diagram showing failing that may occur when using a common bus in accordance with the prior art.

9 is a block diagram schematically illustrating the correlation between each control buffer and data in a nonvolatile semiconductor memory constructed in accordance with the present invention.

10 is a circuit diagram of a read buffer constructed in accordance with an embodiment of the present invention.

11 is a circuit diagram of a write buffer constructed in accordance with an embodiment of the present invention.

12 is a timing diagram showing an input / output timing relationship according to the first embodiment of the present invention.

13 is a timing diagram showing an input / output timing relationship according to the second embodiment of the present invention.

The present invention relates to a nonvolatile semiconductor memory, and more particularly to a nonvolatile semiconductor memory having a pin in common with one of the RAM control pins.

In general, various systems controlled by a computer or a microprocessor are required to develop a high density electrically programmable and erasable nonvolatile semiconductor memory. The nonvolatile semiconductor memory may be used as a hard disk replacement for small hand-held devices and PDA devices, or as an embedded application as in a digital still camera. The application as described above is mainly used as a NAND type nonvolatile semiconductor memory, and the cell structure and operation of the NAND type nonvolatile semiconductor memory are disclosed in detail in Korean Application No. 93-390 entitled Nonvolatile Semiconductor Memory Device. have.

On the other hand, the present invention has a mode for temporarily erasing the memory transistors in the nonvolatile semiconductor memory having a NAND cell structure as described above, which is also commonly referred to as a flash memory.

1 is a view schematically showing the pin arrangement of a general flash memory.

Although the names of the pins shown in FIG. 1 are generally known, the names of the pins are as follows: CLE (Command Latch Enable) pin is for temporarily latching a command, and ALE (Address Latch Enable) pin is used for externally applied addresses. To temporarily latch, (Write Enable) pin is an input signal to enable signal for writing operation. The (Write Protect) pin is for write protection to prevent the loss of data stored in memory transistors when the system is powered up or down. (Chip Enable) pin is a pin that inputs a signal to drive the chip. (Read Enable) pin is an input to enable signal to perform read operation. The (Read / Busy) pin is a pin that outputs a signal indicating whether the chip is running or in a standby state. (Spare Field Enable) pin is for supplying ground level ground power, and NC (No Connection) pin indicates unused pin.

FIG. 2 is a block diagram schematically showing a flash memory and a RAM connected to a common bus line in a general system. FIG. 3 is a diagram briefly illustrating a correlation between control buffers and data in a nonvolatile semiconductor memory according to a conventional technique. 4 is a circuit diagram of a read buffer for controlling data output according to the prior art, and FIG. 5 is a circuit diagram of a write buffer for controlling data input according to the prior art. 6 is an exemplary embodiment of a data output buffer for outputting data in response to a control signal of the read buffer shown in FIG. 4 according to the prior art.

Looking at the prior art with reference to Figures 2 to 6, the write enable signal during data input, that is, write operation Toggles the read enable signal The state of is high level. On the other hand, a read enable signal during data output, that is, a read operation. Toggles the write enable signal The state of must be at a high level. In other words, data input and data output should operate exclusively with each other.

Thus, as in the read buffer 303 shown in FIG. 4 and the write buffer 302 shown in FIG. 5, when either one of the read buffer 303 and the write buffer 302 is enabled, the other The buffer of was allowed to be disabled.

The read buffer 303 read read enable signal And chip enable signals In response to the noble gate 401 and the inverter 402 inverting the output signal of the noble gate 401, the output signal and the write output signal of the inverter 402. Output signal in response to WE It consists of a Noah gate 403 which outputs an OE. In addition, the write buffer 302 is a write enable signal. And chip enable signals And an inverter 502 for inverting the output signal of the NOA gate 501, an output signal of the inverter 502, and the output signal. The write output signal in response to OE It consists of a noar gate 503 which outputs WE.

When the flash memory 202 is used as an embedded application as shown in FIG. 2, the output data of the RAM 203 is transferred to the flash memory 202 while sharing the input / output bus line I / O with the RAM 203. Input or output data of the flash memory 202 may be input to the RAM 203 for use.

That is, the data of the flash memory 202 and the RAM 203 can be read and written at the same time without a separate register to improve the performance of the system.

7 is a timing diagram illustrating an embodiment of data input / output between a flash memory and a RAM in a system.

The timing diagram shown in FIG. 7 shows input / output control pins for inputting data input / output control signals of the flash memory 202 and the RAM 203. , , Is an example of using separately. However, in consideration of improving system performance, it is generally more efficient to use input / output bus line I / O for the input / output control signal pins in common. That is, the write enable signal pin of the flash memory 202 (F) and write enable signal pin of RAM 203 Commonly used (R) or read enable signal pin of flash memory 202 Output enable signal pin of (F) and RAM 203 An example is the use of (R) in common.

However, as shown in FIGS. 4 and 5, the read signal buffer 303 and the write buffer 302 used in the flash memory 202 are controlled by the control signal pins of the RAM 203. (R), Input / output bus line I / O cannot be shared in common with (R). The reason for not sharing will be explained with FIG.

The timing diagram of FIG. 8 shows the write enable signal pin. It is an example of assuming that (R, F) is shared between the flash memory 202 and the RAM 203, and that the data of the flash memory 202 is output and used as input data of the RAM 203. . First, in order to output data of the flash memory 202, a read enable signal Must be toggled and the write enable signal of RAM 203 is required to input it to RAM 203. (R) must be toggled. In this case, however, the write enable signal pin of the RAM 203 is used. (R) is the write enable signal pin of the flash memory 202 Read enable signal of flash memory 202 because it is shared with (F) (F) and write enable signal pin (F) is enabled at the same time. At this time, the write output signal of the write buffer 302 of FIG. Output signal of the read buffer 303 in which WE is shown in FIG. This output signal takes precedence over OE and is enabled. The OE is disabled so that the output data of the flash memory 202 is in a high impedance state. In the opposite case, i.e., read enable signal pin of flash memory 202. Output enable signal pin of (F) and RAM 203 The same fail occurs when (F) is used in common, and the data of the RAM 203 is output to use the input data of the flash memory 202.

Accordingly, an object of the present invention is to provide a nonvolatile semiconductor memory and an input / output control method thereof that can prevent a fail that may occur when a read operation or a write operation is performed with a shared control pin.

Another object of the present invention is to provide a nonvolatile semiconductor memory and an input / output control method thereof capable of efficiently utilizing and controlling the system.

According to the technical idea of the present invention for achieving the above object, having a read enable signal pin shared with the output enable signal pin of the RAM capable of temporarily storing data, and storing the data read from the RAM The nonvolatile semiconductor memory for performing the operation may include data stored in the RAM output in response to an enable signal applied to the output enable signal pin and enabled in a chip enable signal, a write enable signal, and a data input mode. The read operation is disabled in response to the write buffer performing the storage operation by the internal write enable signal output by the one instruction flag and the second instruction flag enabled only in the data output mode in the data input mode. At least one read buffer is characterized in that it is provided.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

It should be noted that like elements and parts in the figures represent the same numerals wherever possible.

9 is a block diagram schematically illustrating the correlation between each control buffer and data in a nonvolatile semiconductor memory constructed in accordance with the present invention.

Referring to FIG. 9, the configuration is similar to that illustrated in FIG. 3 except that the signal is applied to the write buffer 908 and the read buffer 904 constructed according to the present invention. The write buffer 908 and the read buffer 904 will be described in detail with reference to FIGS. 10 and 11 described later.

10 is a circuit diagram of a read buffer constructed in accordance with an embodiment of the present invention, and FIG. 10 is a circuit diagram of a write buffer constructed in accordance with an embodiment of the present invention.

The read buffer 903 shown in FIG. 10 has a read enable signal. And chip enable signals And an inverter 402 for inverting the output signal of the NOA gate 401 and an output signal in response to the output signal and the command flag Ssi of the inverter 402. It consists of a Noah gate 403 which outputs an OE.

The write buffer 902 shown in FIG. 11 has a write enable signal. And chip enable signals And the invert 502 for inverting the output signal of the noar gate 501 and the write output signal in response to the output signal and the command flag Srd of the invert 502. It consists of a noar gate 503 which outputs WE.

Basically, all operation implementation methods of the flash memory 202 are instruction driving methods. In other words, in order to program or erase, external commands corresponding to each mode must be input into the chip through I / O pin I / O. Command input and operation in the data input operation are described in detail in the data loading for the partial program of the domestic application No. 94-25243 nonvolatile semiconductor memory device, so it is omitted in the present invention.

12 is a timing diagram showing an input / output timing relationship according to the first embodiment of the present invention. That is, this is a timing chart for the case where the output data of the RAM 203 is input to the flash memory 202.

At this time, the output enable signal pin of the RAM 203 (R) and read enable signal pins of flash memory 202 (F) is common.

As described above, the flash memory 202 operates by a command driving method, and in the data input mode, the command flag Ssi is enabled in the flash memory 202 chip. At this time, in order to output the data of the RAM 203, the output enable signal (R) must be toggled and output enable signal (R) and read enable signal pins of flash memory 202 The read enable signal pin of the flash memory 202 is used because F is commonly used. (F) is also toggled at the same time. In addition, in order to input data output from the RAM 203 into the flash memory 202, a write enable signal pin of the flash memory 202 is used. As a result, the read enable signal pin of the flash memory 202 must be toggled. (F) and write enable signal pins (F) is simultaneously toggled and enabled.

However, as shown in FIG. 9, the data input command Ssi is enabled from low level to high level, thereby controlling the data output buffer. Read enable signal pin in flash memory 202 because OE is disabled to low level (F) and write enable signal pins Even if (F) is enabled at the same time, the data input operation is normally performed.

13 is a timing diagram showing an input / output timing relationship according to the second embodiment of the present invention. That is, this is a timing chart for the case where the output data of the flash memory 202 is input to the RAM 203.

At this time, the write enable signal pin of the RAM 203 (R) and write enable signal pins of flash memory 202 (F) is assumed to be common.

In order to output the data of the flash memory 202, the data output mode must be entered. At this time, the command flag Srd for activating the data output mode internally in the flash memory 202 chip is enabled from low level to high level. Read enable signal pin of flash memory 202 after entering data output mode Toggle (F) to output flash data, and write enable signal pin of RAM 203 to input output data to RAM 203. (R) must be toggled. At this time, the write enable signal pin of the RAM 203 (R) and write enable pins of flash memory 202 (F) is commonly the write enable pin of the flash memory 202 Since (F) is common, the read enable signal pin of the flash memory 202 is eventually used. (F) and write enable signal pin (F) is activated at the same time.

However, as shown in FIG. 10, when the data output command flag Srd is enabled from low level to high level, the write buffer is disabled, thereby enabling the read enable signal pin outside the chip. And write enable signal pins Even when this is activated at the same time, data output of the flash memory 202 is normally performed.

As described above, the present invention has an advantage of preventing a failure from occurring when the control pins of different devices are shared with each other in the system. In addition, the present invention has the advantage of enabling efficient use and control of the system.

Although the present invention described above has been limited to, for example, the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the technical spirit of the present invention.

Claims (10)

A nonvolatile semiconductor memory having a read enable signal pin shared with an output enable signal pin of a RAM capable of temporarily storing data, and configured to store data read from the RAM; An internal write outputted by a chip enable signal, a write enable signal, and a first command flag enabled in a data input mode, the data stored in the RAM output in response to the enable signal applied to the output enable signal pin; A write buffer for performing the storage operation by an enable signal, and at least a read buffer in which the read operation is disabled in response to a second command flag enabled only in the data output mode in the data input mode. Nonvolatile semiconductor memory. The write buffer of claim 1, wherein the write buffer is configured to input a first logic gate to which the chip enable signal and a write enable signal are input, a signal inverting an output signal of the first logic gate, and the first command flag. A nonvolatile semiconductor memory having a second logic gate. The nonvolatile semiconductor memory of claim 2, wherein the first logic gate is a noble gate. 3. The nonvolatile semiconductor memory of claim 2, wherein the second logic gate is a noble gate. A memory array comprising a plurality of memory transistors arranged in a matrix of rows and columns, and at least a write enable signal pin shared with a write enable signal pin of a RAM capable of temporarily storing data, and stored in the memory transistors. A nonvolatile semiconductor memory for performing an operation of reading data and storing the data in the RAM; A read buffer configured to perform the read operation by a first command flag enabled during output of data stored in the memory transistor, an internal output enable signal output by a chip enable signal, and a read enable signal; And at least a write buffer for disabling the write operation in response to the second command flag enabled only in the data input mode when the data is output. 6. The read buffer of claim 5, wherein the read buffer comprises: a first logic gate configured to input the chip enable signal and a read enable signal; a signal obtained by inverting an output signal of the first logic gate; and the first command flag; A nonvolatile semiconductor memory having a second logic gate. The nonvolatile semiconductor memory of claim 6, wherein the first logic gate is a noble gate. 8. The nonvolatile semiconductor memory of claim 7, wherein the second logic gate is a noble gate. An input / output control method of a nonvolatile semiconductor memory for performing an operation of storing data read from the RAM, the read enable signal pin being shared with an output enable signal pin of a RAM capable of temporarily storing data; Outputting data in response to an output enable signal of the RAM; and disabling the output enable signal of the nonvolatile semiconductor memory in response to a command flag enabled in the data input mode of the nonvolatile semiconductor memory. And storing the output data in the nonvolatile semiconductor memory in response to a write enable signal of the nonvolatile semiconductor memory. A memory array comprising a plurality of memory transistors arranged in a matrix of rows and columns, and at least a write enable signal pin shared with a write enable signal pin of a RAM capable of temporarily storing data, and stored in the memory transistors. An input / output control method of a nonvolatile semiconductor memory for reading data and storing the data in the RAM, the method comprising: writing the nonvolatile semiconductor memory in response to a command clock enabled in a data output mode of the nonvolatile semiconductor memory Disabling an enable signal; outputting data in response to a read enable signal of the nonvolatile semiconductor memory; and storing the output data in the RAM in response to a write enable signal of the RAM. Characterized by consisting of a process.