JPH10134559A - Semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate erasure before writing and increasing a writing speed by rewriting the sector information of an address specified externally to information in a surplus storage region based on the address exchange information of an address exchange circuit. SOLUTION: A control circuit 20 controls the operation of an address exchange circuit 19, a low decoder 12, and a column selection circuit 14 by receiving control information from a control buffer 17. Then, an erasure operation is made to the unit sector of an address in write-disable state, when a surplus bit has been set and a writecompletion bit has been set. Then, after the erasure, the write-completion bit of a sector information region corresponding to a memory array 18 for sector information is set. In this manner, the control circuit 20 for rewriting the sector information to address information on the main memory array of the sector of the address instead of the surplus sector is provided, thus eliminating the need for erasure before writing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor memory device which performs writing and reading in page units.

[0002]

2. Description of the Related Art For example, a NAND flash memory,
In a semiconductor memory device such as a DINOR type flash memory, page data is written to all memory transistors connected to a selected word line at a time.

FIGS. 8 (a) and 8 (b) show NAND circuits, respectively.
FIG. 2 is a diagram showing a memory array structure in a flash memory of the DINOR type.

The NAND flash memory shown in FIG. 8A has a structure in which two select transistors ST1 and ST2 and four memory transistors MT1 to M4 are connected in series to one bit line BL for convenience. 1 shows a NAND type memory array. Select transistors ST1, ST
2 are controlled by connection gate lines SL1 and SL2, respectively, and the memory transistors MT1 and MT2 are controlled by word lines WL1 to WL4, respectively.

In the DINOR type flash memory shown in FIG. 8B, for convenience, four memory transistors MT1 to MT are connected to one sub-bit line connected to one main bit line MBL.
4 shows a DINOR memory array when connected. In the DINOR type, the main bit line MB and the sub bit line SBL are connected via a select transistor ST1 controlled by a select gate line SL. The sub-bit line SBL intersects with the four word lines WL1 to WL4, and four memory transistors MT1 and MT4 are arranged at each intersection position.

[0006]

The above-mentioned N
In a semiconductor memory device such as an AND type or DINOR type flash memory which performs page writing in units of word line sectors, data writing is performed as follows. That is, each bit line (or main bit line)
A data latch circuit for temporarily latching page write data is provided for each time, a data transfer process of transferring page write data to the data latch circuit, and a page write for memory transistors connected to the selected word line in accordance with the page write data The data writing is performed by continuously performing the two steps of the data writing process for performing the data writing. If the sector is in the erased state, the write operation is performed as it is. If the data is already written in the sector, it is necessary to erase the sector before performing the write operation.

As described above, in the data write operation of the flash memory, in the case of the written sector,
The write operation is performed after the erase operation is actually performed before the write operation. Generally, the write time of the flash memory is about 1 ms, whereas the erase time is about 10 ms.

Therefore, in the case of the above-mentioned flash memory, the time required for erasure before writing occupies a considerable proportion of the actual data writing time, and the actual data writing speed is sacrificed.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor memory device capable of increasing a data writing speed.

[0010]

In order to achieve the above object, a semiconductor memory device according to the present invention performs writing and erasing on a main memory in which a plurality of memory cells are arranged in sector units in accordance with an externally specified address. Wherein the main memory has a surplus storage area at least as large as a unit sector than the logical storage area to be addressed, and corresponds to each sector of the entire storage area of the main memory. Information indicating whether the sector is a surplus storage area, information indicating whether the sector is in an erased state or a written state, and sector information including address information of the sector on the main memory. The sector information memory to be stored and, at the time of writing, an externally addressed sector are written based on the sector information of the sector information memory. In the state, the external address is replaced with the address of the sector which is a surplus storage area, and an address replacement circuit for outputting the address as a sector address to be written; and based on the address replacement information of the address replacement circuit, In addition to rewriting the sector information at the address specified from outside the information memory to information that is a surplus storage area, the sector information whose address has been replaced and written is not a surplus storage area,
A control circuit which is in a write state and rewrites the address information with the address information on the main memory of the sector of the address designated from the outside.

In the present invention, at the time of standby, the sector information of the sector information memory is a surplus storage area, and a sector indicating a written state is erased based on the address information. Means for rewriting the sector information to be written from the written state to the erased state.

[0012] Further, at the time of reading, the address replacement circuit, based on the sector information of the sector information memory,
When the externally addressed sector is designated as the surplus storage area, there is provided a means for reading data from the sector to which the sector information is rewritten.

According to the semiconductor memory device of the present invention, at the time of writing, when an externally addressed sector is in a write state based on the sector information of the sector information memory in the address replacement circuit, an externally received address is output. The address is replaced with the address of a sector which is a surplus storage area, and is output as a sector address to be written, and page writing is performed based on this address. Then, address replacement information in the address replacement circuit is supplied to the control circuit. In the control circuit, based on the input address replacement information, the sector information of the address designated from outside the sector information memory is rewritten to the information as the surplus storage area, and the address is replaced and the sector in which the writing is performed is performed. The information is not in the surplus storage area, but in the written state, and the address information is rewritten to the address information in the main memory array of the sector at the address specified from the outside.

Further, no write / erase / read command is issued, that is, at the time of standby, a sector which is a surplus storage area in the sector information of the surplus sector / sector information memory and which is shown to be in a written state is erased. . Then, after erasing, the sector information corresponding to the sector is rewritten from the written state to the erased state.

[0015]

FIG. 1 is a circuit diagram showing an embodiment of a nonvolatile semiconductor memory device according to the present invention, for example, a NAND flash memory. The semiconductor storage device 10
As shown in FIG. 1, a main memory array 11, a row decoder 12, a latch circuit group 13, a column selection circuit 14, an input / output buffer 15, an address buffer 16, a control buffer 17, a sector information memory array 18, and an address replacement circuit 19 , And a write system control circuit 20.

In the memory array 11, for example, N + 2 word lines and m bit lines BL1 to BLm are wired in a grid pattern. FIG. 1 shows a case where the word line WLn is selected,
The case where page writing is performed on the memory transistors MTn, 1 to MTn, m is shown. Main memory array 11
As shown in FIG. 2, writing / erasing is performed in units of word line sectors. Then, as shown in FIG. 2A, the N page address logical space P seen by the user
Actually, as shown in FIG. 2B, at least one extra write / erase unit sector (hereinafter referred to as a surplus sector) PN + 1 is provided in addition to S0 to PSN. (There is one in this embodiment). The supply of voltages to the bit lines BL1 to BLm according to the respective operations of writing, erasing, and reading is performed by a column control system (not shown).

The row decoder 12 responds to an instruction of a control signal S20a from the control circuit 20 to control the address replacement circuit 1
9, the word line addressed by the signal S19 is driven to the active state, and the other unselected word lines are kept in the inactive state.

The latch circuit group 13 includes bit lines BL1 to BL
A data latch circuit is provided for each Lm, and the main memory array 1 is operated in word line sector units.
1 is temporarily stored. At the time of page read, page read data from the main memory array 11 performed in word line sector units is temporarily stored.

The column selection circuit 14 responds to an instruction from the control circuit 20 by a control signal S20b to input / output buffer 15
Circuit group 13 for page write data input to
Of the page read data stored in the latch circuit group 13 to the input / output buffer 15.

The input / output buffer 15 inputs page write data from a data line (not shown), and outputs page read data to the data line.

The address buffer 16 receives address signals A0, A1,... From an external device and supplies them to the sector information memory array 18 and the address replacement circuit 19.

The control buffer 17 receives control signals such as a chip enable signal / CE and a write enable signal / WE which are active at a low level.
Output to the sector information memory array 18 and the control circuit 20.

The sector information memory array 18 is a page address physical unit sector space PS of the main memory array 11.
A sector information area composed of N + 2, for example, floating gate type non-volatile memory transistors physically corresponding to 0 to PSN + 1 is formed. As shown in FIG. 3, each sector information area is composed of a remainder bit field 181, a written bit field 182, and an upper address field 183. In FIG. 3, for simplification of description, four unit sectors are used. Shows a case where the number of surplus sectors is one.

The surplus bit field 181 is composed of 1 bit, and is set to logical "1" when the corresponding unit sector is a surplus sector under the control of the control circuit 20. In this case, it is set to logic “0”. Written bit field 18
2 is 1 bit and is set to logic "1" when the corresponding unit sector is in a write state under the control of the control circuit 20, and is set to logic "0" in an erase state.
Is set to The address upper field 183 is made up of, for example, 2 bits and is set with the upper logical address of the corresponding unit sector. In the case of the example of FIG. 3, the sector information area is set to “00”, “01”, “10”, “11” in order from the first row, and “1” is set to the surplus bit 181. Address upper field 183
Is set to “00”.

FIG. 3A shows an initialized state, that is, all the unit sectors are in the erased state, and the last unit sector is assigned as a surplus sector. (B) shows that the written bits are set to “1” in the unit sectors in the second and third rows, and that data is written in those unit sectors.

Such a sector information memory array 18
Of the data of the sector information area corresponding to the addressed unit sector and the data of the sector information area in which the surplus bit is set to "1" as a signal S18. Output to the address replacement circuit 19.

The address replacement circuit 19 receives the address signal S16a from the address buffer 16 and the signal S18 from the sector information memory array 18, and receives the written bit of the sector information corresponding to the unit sector of the address indicated by the address signal S16a. Is set to “1” and the surplus bit is set to “0”, the address is written to the unit sector of the address indicated by the sector information whose surplus bit is set to “1”. And the replaced address is sent to the row decoder 12 as a signal S1.
9a, and the information on the replacement of the address is given as a signal S19b in the memory array 1 for sector information.
8 and the control circuit 20. On the other hand, when “0” is set in the written bit of the sector information corresponding to the unit sector of the address indicated by the address signal S16a, the address indicated by the address signal S16a is set to the signal S1.
9 as well as notifying to the memory array 18 for sector information and the control circuit 20 that the address has not been replaced, as a signal S19b. Further, even when the surplus bit of the sector information corresponding to the unit sector of the address indicated by the address signal S16a is set to “1” and the written bit is set to “0”, the address indicated by the address signal S16a is also set. A signal S19 is provided, and the fact that the address has been designated for writing to the surplus sector is notified to the sector information memory array 18 and the control circuit 20 as a signal S19b.

The control circuit 20 receives the signal S19a and the information of the sector information memory array 18, and controls rewriting of the surplus bits, the written bits, and the upper bits of the address of the corresponding sector information area of the sector information memory array 18. I do.

Further, the control circuit 20 operates when the write / read operation is not performed based on the control information.
By controlling the decoder 12 and a column control system (not shown), the erasing operation is performed on the unit sector of the address where the surplus bit is set to “1” and the written bit is also set to “1”. Then, the written bit of the corresponding sector information area of the sector information memory array 18 is set to “0”.

An example of the rewriting operation of the surplus bits, the written bits, and the upper address bits of the corresponding sector information area of the sector information memory array 18 of the control circuit 20 will be described with reference to FIG. For example, when a write command is issued to the unit sector corresponding to the sector information area (indicated by * in the figure) in the second row from the state shown in FIG. As described above, the surplus bits of the sector information area in the second row are set to “1”. As a result, both the surplus bit and the written bit of the sector information area of the second row are set to “1”, and the unit sector indicated by the upper bit of the address is in a write-protected state. Next, FIG.
As shown in (1), the remainder bit of the last row in which the remainder bit is set to "1" is set to "0", and the written bit is set to "1". Further, the upper bits of the address are set to “01”. And, as mentioned above,
When the write / read operation is not performed from the control information, the decoder 12 and a column control system (not shown) are controlled to set the surplus bit to “1” and the written bit to be set to “1”. An erase operation is performed on a unit sector of an address in a write-inhibited state, and after erasure, the written bit of the corresponding sector information area of the sector information memory array 18 is set to “0” as shown in FIG. ”And the upper bits of the address are set to“ 00 ”.

Next, the operation of the above configuration will be described with reference to FIG. 2 and FIGS. FIG. 5 is an explanatory diagram of a case where a write command is issued to a written unit sector, and FIG. 6 is an explanatory diagram of a case where erasing is automatically performed internally when not in a write / erase / read state. FIG. 7 is an explanatory diagram when a read command is issued.

First, when a write command is issued from an external device (not shown), the fact is notified to the memory array for sector information and the control circuit 20 via the control buffer 17. A logical sector address to be written is input to the address buffer 16 in parallel with the input of the write command, and the address is supplied to the address replacement circuit 19 as a signal S16a and supplied to the sector information memory array 18 as a signal S16b. Is done.

In the information of the sector information memory array 18, the address and the remainder bit of the sector information area corresponding to the unit sector specified by the address are set to "1" in response to the address specification by the address buffer 16. The data in the sector information area is output to the address replacement circuit 19 as a signal S18.

The address replacement circuit 19 receives the address signal S16a from the address buffer 16 and the signal S18 from the sector information memory array 18, and has already written sector information corresponding to the unit sector of the address indicated by the address signal S16a. Bit is set to "1",
FIG. 5 in which the remainder bit is set to "0"
In such a case, the address is switched so that writing is performed to the unit sector of the address indicated by the sector information in which the remainder bit is set to “1”, and the replaced address is output to the row decoder 12 as a signal S19a. At the same time, the information of the address replacement
19b is reported to the sector information memory array 18 and the control circuit 20. On the other hand, the address signal S1
If "0" is set in the written bit of the sector information corresponding to the unit sector of the address indicated by 6a, the address indicated by the address signal S16a is changed to the signal S19.
And the fact that the addresses have not been replaced is reported to the sector information memory array 18 and the control circuit 20 as a signal S19b.

The control circuit 20 receives the control information from the control buffer 17 and controls the operations of the address replacement circuit 19, the row decoder 12, and the column selection circuit 14. Thus, after the data to be written to the page is once stored in the latch circuit group via the column selection circuit 14, the page data is written into the sector in which the word line is driven by the row decoder 12.

The control circuit 20 receives the signal S19a from the address replacement circuit 19 and the information of the sector information memory array 18 and responds to the sector information memory array 18 according to the procedure shown in FIG. Rewriting control of the surplus bits, the written bits, and the upper bits of the address of the sector information area to be performed is performed. When the write / erase / read operation is not performed based on the control information, the decoder 12
And a column control system (not shown) is controlled so that the surplus bit is set to “1” and the written bit is also “1”.
As shown in FIG. 6, an erasing operation is performed on the unit sector of the address in the write-inhibited state set to "1". After erasing, the sector information memory array 18
The written bit of the corresponding sector information area is “0”
Is set to

As shown in FIG. 5, the address of the last sector unit, which is a surplus sector, is switched to "0002h", and the sector of "0002h" is physically set as a surplus sector, and the sector information memory array is used. Since “1” is set in the surplus bits of the corresponding sector information of No. 18, when a read command is issued, as shown in FIG. 7, the data is read from the last sector in page units.

As described above, according to the present embodiment, the main memory array 11 has a surplus sector area at least as large as the unit sector than the logical recording area to be addressed. Corresponding to each sector of the storage area, information indicating whether the sector is a surplus sector, information indicating whether the sector is in an erased state or a written state, and a main memory array of the sector. When a sector that is externally addressed is in a write state based on the sector information of the sector information memory array 18 at the time of writing and the sector information memory array 18 that stores the sector information composed of the above address information, Address that replaces the external address with the address of the surplus sector and outputs it as the write target sector address. A replacement circuit 19, based on the address replacement information address replacement circuit 19, the sector information of the specified address from the outside of the sector information for the memory array 18 with rewritten information is the remainder sectors,
A control circuit 20 for rewriting the sector information in which the address has been replaced and for which writing has been performed is not a surplus sector, but is in a writing state and the address information is replaced with address information on the main memory array of the sector of the address specified from the outside.
Is provided, there is no need to erase before writing, and there is an advantage that the writing speed can be increased.

Further, in the present embodiment, the case where there is one surplus sector has been described as an example, but a plurality of surplus sectors can be provided.
Assuming that the number of surplus sectors is Z, the writing time is TW, and the erasing time is TE, the erasing time is completely invisible from the outside by satisfying the following relationship.

[0040]

## EQU1 ## TW × (Z + 1) ≧ TE

According to this condition, when the erasing time TE is 10 milliseconds and the writing time TW is 1 millisecond, the erasing time is completely invisible from the outside if there are 11 or more surplus sectors.

[0042]

As described above, according to the present invention,
There is no need to perform erasing before writing, and the writing speed can be increased.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a diagram showing an N-page address logical space visible to a user and an actual logical address including a surplus sector.

FIG. 3 is a diagram showing a configuration example of a sector information area according to the present invention.

FIG. 4 is a diagram for explaining a sector information rewriting operation of the control circuit according to the present invention.

FIG. 5 is an explanatory diagram when a write command is issued to a written unit sector.

FIG. 6 is an explanatory diagram of a case where erasing is automatically performed internally when not in a write / erase / read state.

FIG. 7 is an explanatory diagram when a read command is issued.

FIG. 8 is a diagram showing a memory array structure in NAND type and DINOR type flash memories.

[Explanation of symbols]

10 semiconductor memory device, 11 main memory array, 12
Row decoder, 13 latch circuit group, 14 column selection circuit, 15 input / output buffer, 16 address buffer, 17 control buffer, 18 memory array for sector information, 19 address replacement circuit, 20 write system control circuit.

Claims (3)

[Claims] 1. A semiconductor memory device for performing writing and erasing on a main memory in which a plurality of memory cells are arranged in sector units in accordance with an externally designated address, wherein the main memory is a logical memory to be addressed. Information indicating whether or not the sector is a surplus storage area, corresponding to each sector of the entire storage area of the main memory, having a surplus storage area at least as large as the unit sector than the area; And a sector information memory for storing information indicating whether the sector is in an erased state or a written state, and sector information including the address information of the sector in the main memory. When writing, the sector information in the sector information memory If the externally addressed sector is in a write state based on the An address replacement circuit that replaces the address of the data and outputs it as a sector address to be written, based on address replacement information of the address replacement circuit,
In addition to rewriting the sector information at the address specified from the outside of the sector information memory to information that is a surplus storage area, the sector information whose address has been replaced and written is not in the surplus storage area, but in a write state, And a control circuit for rewriting the address information with the address information on the main memory of the sector of the address specified from the outside. 2. In a standby mode, sector information of the sector information memory is a surplus storage area, and a sector indicating a written state is erased based on the address information, and after erasing, sector information corresponding to the sector is erased. 2. The semiconductor memory device according to claim 1, further comprising means for rewriting from a written state to an erased state. 3. The address replacement circuit according to claim 1, wherein at the time of reading, based on the sector information of said sector information memory, if a sector addressed externally is designated as a surplus storage area, said address replacement circuit writes said sector information. 2. A means for reading data from a replacement sector.
13. The semiconductor memory device according to claim 1.