JPH02248172A - Solid-state memory device for storing picture - Google Patents

Abstract

PURPOSE:To store lots of pictures with less capacity by writing a data while selecting either a data path via a compression means or a data path not via the means and reading the data while selecting either a data path via a compression means or a data path not via the means. CONSTITUTION:A solid-state memory device 12 can select two ways of storage methods as compressed form and non-compressed form. Selector switches 24, 30 are switched manually. When the switch 24 is thrown to the position of a contact (a), an A/D converter 18 digitizes a picture output and the result is compressed by a compression circuit 26 and stored in a memory 28. with the switch 24 thrown to the position of a contact (b), the picture data is stored in the memory 28 as it is. When the switch 30 is thrown to the position of the contact (a), the data in the memory 28 is outputted as it is from the solid- state memory device 12 and when the switch 30 is thrown to the position of the contact (b), the data in the memory 28 is expanded by an expansion circuit 32 and the resulting data is outputted from the solid-state memory device 12 and converted into an analog signal at a D/A converter 20 and converted into a video signal by a video encoder 22.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid state memory device for storing images, for example as a recording medium for an electronic still camera.

[Prior Art] Electronic methyl video cameras that use magnetic floppy disks as image recording media are well known, but as semiconductor memories have become more highly integrated and lower in price in recent years, it has become increasingly common to use semiconductor memory devices as image recording media. The still video camera used is seen as promising.

[Problem to be solved by the invention] The number of pixels in the image sensor of a still video camera, such as a CCD type image sensor, is currently around 500,000 pixels, and in the near future, it is likely that devices with more than 1 million pixels will be realized. It is. In order to store the data of a large number of pixels in a memory without deterioration, an image of 500,000 pixels requires 4 megabits, assuming 8 bits per pixel. If you try to store an image of 25 frames on a magnetic floppy, part 2
100 megabits will be required five times, and no matter how much the integration of semiconductor memory progresses, it is disadvantageous in terms of cost, size, and power consumption.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a solid-state memory device for storing images that can store more images with a smaller memory capacity.

[Means for Solving the Problems] A solid-state memory device for image storage according to the present invention includes a solid-state memory means, and a data path for transmitting write data to the solid-state memory means through either a data path that passes through a compression means or a data path that does not pass through a compression means. It is characterized by comprising a write selection means for selecting and supplying one of them, and a read selection means for selecting either one of a data path passing through the decompression means and a data path not passing through the decompression means for the output data of the solid state memory means. do.

[Operation] By using the above means, the memory capacity can be substantially increased by appropriately and selectively performing compression processing by utilizing the redundancy of images.

Furthermore, by providing the compression/expansion means, input/output compatibility with solid-state memory devices not equipped with such compression/expansion means can be maintained. Furthermore, you can choose between outputting the recorded data as is or decompressing it before outputting it. In the former case, high-speed output is possible, making it easier to copy, file, and transmit image data. This enables high-speed processing.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a configuration block diagram of an embodiment of the present invention in which two compression processes can be selected. 10 is a camera body, and 12 is a solid-state memory device for recording (storing) captured images. Light from an object to be photographed enters the image sensor 16 via the photographic lens 14, and is photoelectrically converted by the image sensor 16. The output of the image sensor 16 is digitized by an A/D converter 18.

If you want to record a photographed image in the solid-state memory device 12,
The output data of the A/D converter 18 is stored in the solid state memory device 12.
If only the display is desired, the D/A converter 2
0, the signal is returned to an analog signal, and the video encoder 22 converts it into a video signal and outputs it.

In the solid-state memory device 12, two storage methods can be selected: a compressed format and an uncompressed format. 24 is a selection switch thereof, which can be manually switched.

When the switch 24 is connected to the a contact side, the data is compressed by the compression circuit 26 and stored in the memory 28 .

When the switch 24 is connected to the b contact side, the image data is stored in the memory 28 as is.

When reading data from the solid-state memory device 12, two operations can be selected: an operation of reading out the data stored in the memory 28 as is, and an operation of reading out the data after decompression processing in the case of compressed data. 30 is a selection switch thereof, and 32 is a decompression circuit that performs decompression processing corresponding to the compression processing of the compression circuit 26.

When the switch 30 is connected to the a contact side, the memory 2
8 is output as is from the solid-state memory device 12, and when the switch 30 is connected to the b contact side, data obtained by expanding the data in the memory 28 by the expansion circuit 32 is output from the solid-state memory device 12.

When compressed and recorded in the solid-state memory device 12, there is an advantage that the number of stored images increases by the amount of compression, but there is also a disadvantage that the processing time for compression/expansion increases.

On the other hand, when recording data as is in the solid-state memory device 12, it has the advantage that writing and reading can be performed at high speed, and since the storage capacity per image is constant, random access is possible in units of fields or frames. There is.

In any case, the selection switches 24, 30, the compression circuit 2
6 and decompression circuit 32 in the solid state memory device 12, the camera body 10 can be written to and read from like a normal standard solid state memory device without such selection functionality. At first glance, it is no different from connecting a large-capacity solid-state memory device.

In addition to the camera body 10, a recording and reproducing device with an editing function,
Considering the case of connecting to an electronic album, a transmitter, etc., it is preferable that the data stored in the memory 28 of the solid-state memory device 12 can be retrieved as is. In this case, the switch 30 may be connected to the a contact side. This is because the compression method by the compression circuit 24 is self-evident, so that the image can be restored using another circuit or device, and it also has advantages such as increasing the read speed from the solid-state memory device 12.

Note that since Figure 1 mainly depicts the flow of image signals, switches and display devices for various operation instructions, as well as control circuits and power supply circuits that control the entire system are omitted. .

Next, the compression process in the compression circuit 26 will be specifically explained. Natural images have a very strong correlation with adjacent pixels, and when the difference between adjacent pixels is taken, the value is small in the case of extremes. In other words, compared to storing (recording) the absolute value of the image (for example, 8 bits), by storing the difference, the amount of data can be significantly reduced. This compression method
It is called DPCM. In addition, as another compression method, ADP is an improved version of DPCM in which the nonlinearity of the nonlinear quantization circuit is adaptively changed according to the image.
There are CM and methods (for example, discrete cosine transformation) in which an image is compressed by converting the image into the frequency domain and increasing the weight of coefficients of low frequency components and decreasing the weight of coefficients of high frequency components.

FIG. 2 shows a block diagram of the configuration of a compression circuit using DPCM, and FIG. 3 shows a block diagram of the configuration of a decompression circuit for decompressing the compressed data of FIG. For more information, see Nikkan Kogyo Shimbun series, 1 of ``Digital signal processing of images'' by Takahiko Fukinuki.
It is explained on pages 46-159. In FIG. 3, 40 is a subtracter, 42 is a nonlinear quantization circuit, 44 is a representative value setting circuit, 46 is an adder, 48 is a delay circuit, and 50 is a coefficient multiplier. The subtracter 40 subtracts from the input 8-bit image data,
The output of coefficient multiplier 50 is subtracted. Nonlinear quantization circuit 4
2 nonlinearly quantizes the output of the subtracter 40, thereby compressing the input image data from 8 bits to, for example, 3 bits. The 3-bit output of the nonlinear quantization circuit 42 is the target compressed data.

The representative value setting circuit 44 returns the 3-bit output of the nonlinear quantization circuit 42 to an 8-bit representative value, and the adder circuit 46 converts the output of the representative value setting circuit 44 into a representative value (8 bits) using the coefficient multiplication circuit 50. Add the outputs of . The output of the adder 46 is delayed by one pixel by a delay circuit 48, specifically a data latch circuit, and applied to a coefficient multiplication circuit 50. The coefficient multiplication circuit 50 multiplies by a constant coefficient, for example 0.95,
The multiplication result is applied to the subtraction circuit 40 and the adder 46 when the next data is input.

By repeating the above, 8 bit data is compressed to 3 bits.

The nonlinear quantization circuit 42, the representative value calculation circuit 44, and the coefficient multiplication circuit 50 can be realized in the form of ROM table conversion,
High-speed processing is possible.

Next, the decompression circuit shown in FIG. 3 will be explained. 52 is a representative value setting circuit, 54 is an adder, 56 is a delay circuit for one pixel, and 58 is a coefficient multiplication circuit. The representative value setting circuit 52 is a circuit similar to the representative value setting circuit 44 in FIG.
bit) to an 8-bit representative value. The adder 54 adds the output of the coefficient multiplication circuit 58 to the output of the representative value setting circuit 52. The output of the adder 54 becomes the desired restored data. The delay circuit 56 is a data latch similar to the delay circuit 48, and delays the output of the adder 54 by one pixel and supplies the delayed output to the coefficient multiplication circuit 58. The coefficient multiplication circuit 58 multiplies the result by a constant coefficient, for example 0.95, and outputs the result to the adder 54. Through the above loop processing, the input compressed data (3 bits)
is decompressed to 8 bits and restored.

For more information on the discrete cosine transform method, see 179-179 of "Digital Signal Processing of Images" by Takahiko Fukinuki, published by Nikkan Kogyo Shimbunsha.
Since it is explained on page 195, its outline will be briefly explained. First, image data is orthogonally transformed by discrete cosine transform to extract frequency components. The frequency components are multiplied by a coefficient that leaves the low frequency components and cuts the high frequency components. This allows image information to be compressed. If the frequency components of the image are closer to the lower side, good compression with little deterioration can be performed.

In the above embodiment, the image data can be processed in the same way whether it is black and white or color.

[Effects of the Invention] As can be easily understood from the above explanation, according to the present invention, by appropriately compressing and recording while maintaining compatibility with ordinary solid-state memory devices that do not have compression/expansion functions. , the apparent upper memory capacity can be increased. Furthermore, since recorded data can be directly read, high-speed access is possible, and recompression/decompression processing is not required during editing, filing, transmission, etc., so multiple compression/decompression processes can be performed.
Image quality deterioration due to decompression processing can be prevented.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a compression circuit, and FIG. 3 is a block diagram of a decompression circuit. 10: Camera body 12: Solid-state memory device 14: Photographic lens 16: Image sensor 18: A/D converter 2
0: D/A converter 22: Video encoder 2
4.30: Selection switch 26: Compression circuit 28: Memory 32: Expansion circuit

Claims (1)

[Claims] a solid-state memory means; a write selection means for selectively supplying write data to the solid-state memory means through either a data path passing through the compression means or a data path not passing through the compression means;
A solid-state memory device for image storage, characterized in that it comprises a readout selection means for selecting either a data path passing through the decompression means or a data path not passing through the decompression means for the output data of the solid-state memory means.