JPH02246519A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To enable a phase locked loop to withdraw from a wrong phase locked state speedily and surely carried out phase locked loop operation by detecting the phase locked loop having entered the wrong phase locked state, applying a disturbance signal to the phase locked loop, and making the phase- locked loop withdraw from the wrong phase locked state. CONSTITUTION:When the phase locked loop 1 enters the wrong phase locked state and the state wherein a specific phase locked pattern is not present in the output signal of a latch circuit 8 continues for a constant time, a timer 11 outputs a warning signal. Disturbance adding means 13-15 apply the disturbance signal to the phase-locked loop 1 according the warning signal and a detection signal which is outputted by a detecting circuit 12 as long as the input signal is present so that the phase-locked loop 1 withdraws from the wrong phase locked state. Consequently, even if the wrong phase locked state is entered, the phase-locked loop withdraws from the wrong phase locked state speedily to surely enter the phase locked loop operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase-locked circuit that extracts a clock signal from self-clocking digital data.

[Conventional technology]

FIG. 2 is a block diagram showing an example of a conventional phase locked circuit of this type. In the figure, a phase-locked loop 1 is a circuit for extracting a clock signal CK from self-synchronized digital data D input from an input terminal 2 and taking it out from an output terminal 3, and a phase comparator 4. DC amplifier5.
It is composed of a reduction filter 6 and a voltage controlled oscillator 7.

Of these, the phase comparator 4 is a circuit that compares the phase of the digital data D input from the input terminal 2 and the phase of the clock signal CK output from the voltage controlled oscillator 7, and outputs a signal corresponding to the difference. , the DC amplifier 5 is a circuit for amplifying the output of the phase comparator 4. The reduction filter 6 is a circuit for removing high frequency components from the output of the DC amplifier 5, and the output of the reduction filter 6 is given as a control voltage to the voltage controlled oscillator 7. The voltage controlled oscillator 7 has a function of outputting a clock signal CK of phase 1 frequency according to the control voltage given from the reduction filter 6.

The latch circuit 8 is a circuit for latching (sampling) digital data D, which is an input signal, in synchronization with the clock signal CK output from the voltage controlled oscillator 7 of the phase-locked loop 1, and shaping the waveform of the input signal. The waveform-shaped data is taken out from the output terminal 9.

In the operation of the above-mentioned phase-locked circuit, in the phase-locked loop 1, a clock signal CK synchronized with digital data D, which is an input signal, is outputted to the voltage-controlled oscillator 4 by its negative feedback effect.
The digital data D is output from the latch circuit 8 at a timing synchronized with the clock signal CK, and is taken out from the output terminals 3 and 9, respectively.

Figure 3 shows the digital data D (
(1)) and the extracted clock signal CK (3rd
(2)). Since this digital data D is not a continuous periodic signal but contains clock information at its changing points, the phase comparator 4 described above is generally provided with a changing point detection function. In addition, when the frequency change range of the input digital data D is wide, a frequency comparison function is also provided to compare the frequency of the digital data D and the frequency of the clock signal CK output from the voltage controlled oscillator 7. It is customary to provide the signal to the phase comparator 4.

[Problem to be solved by the invention]

However, in the conventional phase-locked circuit described above, under conditions where the frequency change range of the digital data D and the oscillation frequency range of the voltage controlled oscillator 7 are wide, the input digital data D has a continuous fixed pattern. Then, there is a problem in that the phase-locked loop 1 falls into a state of erroneous synchronization in which it outputs a clock signal CK having a frequency different from the frequency to which it should be originally synchronized, and it becomes impossible to escape from this state.

FIG. 4 is a waveform diagram showing an example of the most extreme case of such a phenomenon. FIG.
) shows the waveform diagram of the clock signal CKI (that is, the clock signal with the frequency that should be synchronized) in a normal synchronization state, and Fig. 4 (3) shows the waveform diagram of the clock signal CKI in a state of incorrect synchronization.
A waveform diagram of K2 is shown.

That is, the phase-locked loop 1 should be synchronized with the state in which the voltage controlled oscillator 7 outputs the clock signal CKI of the above-mentioned frequency with respect to the digital data D containing the clock information of the above-mentioned frequency. It is easy to fall into a state of erroneous synchronization in which the frequency clock signal CK2 is output.

Therefore, in order to prevent such erroneous synchronization from occurring, countermeasures are generally taken such as scrambling the input digital data D or providing the phase comparator 4 with a frequency comparison function as described above. It is being taught.

However, even when the phase comparator 4 is provided with a frequency comparison function, the frequency of the input digital data D and the frequency of the clock signal CK output from the voltage controlled oscillator 7 have an integer-to-integer relationship of 1. If the frequency ratio becomes close to , for example 11:12 or 13:14, the phase-locked loop 1 will fall into erroneous synchronization. This is because the gain of the frequency comparison function is generally small where the frequency ratio is close to 1.

The present invention has been made to solve these problems, and provides a phase synchronization circuit that can quickly escape from the false synchronization state and perform reliable synchronization even if it falls into a false synchronization state. The purpose is to obtain.

[Means to solve the problem]

The phase-locked circuit according to the present invention includes a phase-locked loop that extracts a clock signal from self-synchronized digital data that is an input signal, and a phase-locked loop that latches the input signal in synchronization with the extracted clock signal and converts the input signal into a waveform. A latch circuit for shaping, a detection means for detecting the presence or absence of an input signal, an alarm means for outputting an alarm signal when a state in which a predetermined synchronization pattern does not exist in the output signal of the latch circuit continues for a certain period of time, and a detection means for Disturbance adding means is provided for outputting a detection signal and adding a disturbance signal to the phase-locked loop to cause the phase-locked loop to escape from an incorrectly synchronized state when the alarm means outputs the alarm signal.

[Effect]

In this invention, when the phase-locked loop falls into an erroneously synchronized state and the state in which the predetermined synchronization pattern does not exist in the output signal of the latch circuit continues for a certain period of time, the alarm means outputs an alarm signal. Based on the alarm signal and the detection signal outputted from the detection means (outputted as long as there is an input signal), a disturbance signal is added to the phase-locked loop from the disturbance adding means, thereby preventing the phase-locked loop from being erroneously synchronized. Escape immediately.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of a phase locked circuit according to the present invention. In the figure, the phase-locked loop 1 is
Clock signal CK is generated from self-synchronous (self-clocking) type digital data D input manually from input terminal 2.
A circuit for extracting and taking out from output terminal 3,
Phase/frequency comparator 4a, DC amplifier 5. Reduction filter 6
and a voltage controlled oscillator 7. Of these, the phase/frequency comparator 4a compares the phase and frequency of the digital data D input from the input terminal 2 with the phase and frequency of the clock signal CK output from the voltage controlled oscillator 7, and generates a signal corresponding to the difference. The DC amplifier 5 is a circuit for amplifying the output of the phase comparator 4. The reduction filter 6 is a circuit for removing high frequency components from the output of the DC amplifier 5, and the output of the reduction filter 6 is given as a control voltage to the voltage controlled oscillator 7. The voltage controlled oscillator 7 has a function of outputting a clock signal CK having a phase and frequency corresponding to the control voltage applied from the reduction filter 6.

The latch circuit 8 latches (samples) digital data D, which is an input signal, in synchronization with the clock signal CK output from the voltage controlled oscillator 7 of the phase-locked loop 1, and performs waveform shaping on the input signal. The waveform-shaped data is taken out from the output terminal 9. When this data is, for example, data on a CD (compact disc), as is well known, a synchronization pattern in a predetermined format is inserted at every predetermined period of data. As long as the phase-locked loop 1 is properly synchronized, this synchronization pattern should appear in the output of the latch circuit 8 at a predetermined period.

At the next stage of the latch circuit 8, an alarm means is provided which outputs an alarm signal when the above synchronization pattern does not exist in the data output from the latch circuit 8 for a predetermined period of time. This alarm means is composed of a synchronization pattern detection circuit 10 and a timer 11, the synchronization pattern detection circuit 10 detects a synchronization pattern present in the data output from the latch circuit 8, and the timer 11 If a state in which no detection signal is output continues for a certain period of time, an alarm signal is output.

Further, the detection circuit 12 is a detection means for detecting the presence or absence of an input signal, that is, whether or not the digital data D is input to the input terminal 2. is given as a two-man power of the AND gate 13 in the next stage. This AND gate 13
The next stage receives the output of the AND gate 13 and generates, for example, a sine wave.

A signal generating circuit 14 is provided which generates a signal such as a triangular wave or random noise that causes disturbance to the phase-locked loop 1, and the disturbance signal from the signal generating circuit 14 is added to the phase-locked loop 1.

That is, an adder circuit 15 is inserted between the reduction filter 6 and the voltage-controlled oscillator 7 of the phase-locked loop 1, and the disturbance signal from the signal generation circuit 14 is passed through the adder circuit 15 to the phase-locked loop. Added within 1. In other words, AND
Gate 13. The signal generating circuit 14 and the adding circuit 15 detect the detection signal of the detection circuit 12 and the timer 11.
Disturbance adding means is configured to add a disturbance signal to the phase-locked loop 1 when there is a disturbance alarm signal.

Next, the operation of the phase locked circuit will be explained.

The phase/frequency comparator 4a of the phase-locked loop 1 compares the phase and frequency of the digital data D input from the input terminal 2 with the phase and frequency of the clock signal CK output from the voltage controlled oscillator 7. A signal corresponding to the difference between them is output from the phase comparator 4 and amplified by the DC amplifier 5. The amplified signal is sent to the next stage reduction filter 6, where its high frequency components are removed.

The output of the reduction filter 6 is input as a control voltage to a voltage controlled oscillator 7, and the voltage controlled oscillator 7 outputs a clock signal CK having a phase and frequency corresponding to the control voltage.

By such a negative feedback control operation, the voltage controlled oscillator 7 normally outputs a clock signal CK that is correctly synchronized with the digital data D, and the clock signal CK is taken out from the output terminal 3. On the other hand, the latch circuit 8 latches and waveform-shapes the input signal digital data D in synchronization with the clock signal CK, and generates the waveform-shaped data (which includes the synchronization pattern of the digital data D). ) is taken out from the output terminal 9.

On the other hand, for example, due to a series of fixed patterns in the input digital data D, the phase-locked loop 1 is in a state of incorrect synchronization, that is, the clock signal C from the voltage controlled oscillator 7 has a frequency different from that when properly synchronized.
If K is output, the data latched and waveform-shaped by the latch circuit 8 in synchronization with the clock signal CK at this time does not have the synchronization pattern seen during normal synchronization, and therefore the next No detection signal is output from the synchronization pattern detection circuit 10 of the stage.

If the state in which no detection signal is output continues for a certain period of time, an alarm signal is output from the timer 11, and this signal is
It is given as one input to gate 13. On the other hand, the detection circuit 12 receives digital data D from the input terminal 2 at this time.
is detected, and the detection signal is given as the other input of the AND gate 13. In response to these two inputs, the AND gate 13 outputs a signal that activates the next-stage signal generation circuit 14 , whereby the signal generation circuit 14 outputs a disturbance signal, and this disturbance signal is sent via the addition circuit 15 . is added to the phase-locked loop 1. Erroneous synchronization due to a fixed pattern of digital data D is unstable compared to normal synchronization, so phase synchronization can be achieved by adjusting the addition amount of adder circuit 15 and adding an appropriate disturbance to phase-locked loop 1. Loop 1 can be easily extracted from a false synchronization. In this way, the phase-locked loop 1 escapes from the incorrectly synchronized state and settles into the correct synchronized state.

When the phase-locked loop 1 is in a normal synchronized state, a synchronization pattern exists in the data waveform-shaped by the latch circuit 8, and this is detected by the synchronization pattern detection circuit 10, so that an alarm signal is output from the timer 11. Therefore, no unnecessary disturbance signal is added to the phase-locked loop 1.

Further, when the digital data D is not input to the input terminal 2, the detection circuit 12 does not detect it, so that no disturbance signal is added to the phase-locked loop 1 at this time as well.

〔Effect of the invention〕

As explained above, according to the phase-locked circuit of the present invention, when the phase-locked loop falls into an incorrectly synchronized state, this is detected and a disturbance signal is applied to the phase-locked loop to bring the phase-locked loop out of the incorrectly synchronized state. Since it is configured to allow escape, there is an effect that it is possible to quickly escape from the erroneous synchronization state and perform a reliable synchronization operation.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the phase-locked circuit according to the present invention, Fig. 2 is a block diagram showing a conventional phase-locked circuit, and Fig. 3 shows each signal of the phase-locked circuit in a normal synchronized state. FIG. 4 is a waveform diagram showing each signal in an erroneous synchronization state of the phase synchronization circuit. In the figure, 1 is a phase locked loop, 13 is an AND gate, 14 is a signal generation circuit, and 15 is an adder circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts. Diagram

Claims (1)

[Claims] (1) A phase-locked loop that extracts a clock signal from self-synchronous digital data that is an input signal, and latches the input signal in synchronization with the clock signal extracted by this phase-locked loop and shapes the input into a waveform. A phase locked circuit including a latch circuit, a detection means for detecting the presence or absence of the input signal, and an alarm that outputs an alarm signal when a state in which a predetermined synchronization pattern does not exist in the output signal of the latch circuit continues for a certain period of time. and a disturbance adding means for adding a disturbance signal to the phase-locked loop to cause the phase-locked loop to escape from a state of false synchronization when the detection means outputs a detection signal and the alarm means outputs an alarm signal. A phase-locked circuit characterized in that it is provided with a phase-locked circuit.