JPH02246368A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To inhibit crystal defects, and to lower the impurity concentration of the surface by laminating first main surfaces of a first semiconductor wafer and a second semiconductor wafer to form a substrate, performing etching and removal of the first semiconductor wafer until its impurity layer is exposed and forming an impurity region having a conductivity type different from that of the impurity layer. CONSTITUTION:A conductivity type impurity 4 is added to a surface opposite to the first main surface of a first semiconductor wafer 1 to form an impurity layer 41, and the surface oppositely faced to the first main surface of the first semiconductor wafer 1 and the first main surface of a second semiconductor wafer 2 are laminated, thus manufacturing a substrate 10. The first semiconductor wafer 1 of the substrate 10 is etched and removed until the impurity layer 41 is exposed, and an impurity region 42 having a conductivity type different from the impurity layer 41 is formed into the exposed impurity layer 41. Consequently, heating for a prolonged time can be eliminated from a manufacturing process after the laminating of the wafers for reducing crystal defects in a silicon crystal. Accordingly, the crystal defects are inhibited, and the impurity concentration of the surface of the substrate can be lowered easily.

Description

[Detailed Description of the Invention] [Summary] A method for manufacturing a semiconductor device in which a CMOS device or the like is formed on an SOI substrate. An insulating layer is formed on at least one of a first main surface of a first semiconductor wafer and a first main surface of a second semiconductor wafer, with the aim of providing a method for manufacturing a semiconductor device that can easily reduce surface impurity concentration. a step of adding a conductivity type impurity to a surface opposite to the first main surface of the first semiconductor wafer to form an impurity layer; and a step of forming an impurity layer on the first main surface of the first semiconductor wafer. forming a substrate by bonding opposing surfaces and a first main surface of the second semiconductor wafer; etching away the first semiconductor wafer of the substrate until the impurity layer is exposed; forming an impurity region of a conductivity type different from that of the impurity layer in the exposed impurity layer.

3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device in which a CMOS device or the like is formed on a SOR substrate.

In recent years, as electronic devices have become more multifunctional and smaller, semiconductor devices have been required to have higher speeds and higher densities. But even faster.

In order to promote higher density, there are issues that must be overcome.For example, in order to increase the speed of CMOS devices, p-channel MOSFET and n-channel MOSFET
II! However, if the two are brought close together, a small amount of noise entering the semiconductor substrate will cause the two PET
A so-called rough stub phenomenon occurs in which current continues to flow between the two.

As an effective manufacturing method to solve the above problem, S0! (S
There is a technology using an ilicon (on inverter) substrate. This S-separated substrate has SiO in the silicon layer.
It has a structure in which the second insulating film is sandwiched, and when used in a CMOS device, for example, a --like SiO□ layer is already formed under the silicon layer that becomes the element region, so the p-channel MOSFET and n-channel MOSI
'By simply isolating the elements between the ETs with a trench, etc., you can reliably separate the p-channel MOSFET and n-channel MOSFET.
Can be insulated and separated. Since the P-channel MOSFET and the n-channel MOSFET are completely insulated and separated, no latch-up phenomenon occurs even if they are brought close to each other. Therefore, we actively use p-channel MOSFET and n-channel MOSFET.
! T can be brought closer to CMOS devices, and higher speed and higher density CMOS devices can be achieved. As above, SO
■The board is an effective means to solve problems such as latch-up. However, since SOI is made of two materials, SiO□ and silicon, which have different coefficients of thermal expansion, it is desirable to eliminate long-term high-temperature heating that causes thermal stress from the process after SOI formation.

[Conventional technology]

Next, this SOI will be explained using an example in which the bonded SOI technology, which has been frequently used recently, is applied to a CMOS device. This bonding SQI technology is a technology that creates an SO structure by forming an oxide film by thermally oxidizing the surface of at least one of two silicon wafers, and then stacking and bonding the surface-oxidized wafers together. It is.

FIG. 3 is a manufacturing process diagram of a conventional bonded Sot substrate. In FIG. 0, 1 is a first semiconductor wafer, 2 is a second semiconductor wafer, and 3 is an oxide layer. Further, 10 is a substrate, which is formed by bonding the first semiconductor wafer 1 and the second semiconductor wafer 2 together and then polishing them. Impurity 4 is added to this substrate IO, and a high concentration region 45 is formed in a shallow portion of impurity layer 41.

In step (a), two silicon wafers (first semiconductor wafer 1, second semiconductor wafer 2) with a thickness of 400 to 600 t1m are prepared.
The oxidized surfaces of the two silicon wafers are oxidized to form an oxide layer 3 with a thickness of about lum on each surface.Next, in step (b), after the oxidized surfaces of the two silicon wafers are superimposed on each other, an oxidized layer 3 is formed on each surface. An electric field is applied to temporarily bond the two pieces together. Thereafter, the wafers are completely bonded at 1100° C. for 230 minutes, for example, to form a substrate 10 having a structure in which an oxide layer is sandwiched in the silicon layer. Process (C)
Then, one side of the substrate is removed by polishing, leaving only a thickness of about 3 μm as an element region. In step (d), a p-type impurity layer 41. which becomes an element region is formed. An n-type impurity layer 42 is formed. Of the surface-polished surface of the substrate 10, B" (boron) ions are implanted into the part that will become a p-Wall. Also, P" (boron) ions are implanted into the part that will become an n-Well adjacent to the part that will become a p-Well. (phosphorus) ions are implanted. After this,
The impurity layer 41 is diffused by heating at 1200° C. for 3 to 6 hours. By this impurity diffusion, the p-type impurity layer 41
．． The impurity concentration is varied in the n-type impurity layer 42, and the high concentration 813tj, 45 shown in the figure is formed. Through the above steps, a well is formed in the bonded SO1 substrate having the structure shown in FIG. Complete.

Generally, in order to increase the depth of an impurity layer formed by ion implantation to about 3 μm, it is necessary to diffuse impurities by heating at a high temperature for a long time as described above. conventionally,
This impurity diffusion is performed after a so-called Sol structure in which an oxide layer is sandwiched between silicon layers is formed. However, if a long-time high-temperature heating process is included after the SOI structure is completed, the difference in thermal expansion coefficient between silicon and oxide layer will cause a similar effect on the substrate to occur on a bimetallic layer, causing stress to accumulate in the silicon crystal and causing crystal defects. For example, in the case of a CMOS (complementary MO9) integrated circuit, which is characterized by its ability to operate with low power, the occurrence of such crystal defects increases junction leakage current, leading to device deterioration.

On the other hand, the conventional technology also has problems in terms of impurity diffusion. In the conventional SOI technology, impurities are diffused from the surface side of the SOI substrate after the Sol structure is completed, so that the impurity concentration becomes particularly high near the surface of the SOI substrate. - As an example, FIG. 2 shows the concentration profile of a silicon layer into which impurities have been diffused, and the horizontal axis represents the depth from the substrate surface.

The impurity concentration at each depth is plotted on the vertical axis.

According to FIG. 2, it is clear that the impurity concentration near the diffusion surface of the substrate is particularly high. Not limited to SOI, but in general, when the surface concentration of an element forming substrate is high, autodoping increases during epitaxial growth, which causes a slowdown in device operation. Other methods are known for increasing the impurity concentration deep from the impurity diffusion surface, but they require large-scale equipment and are complicated processes.

There has been a long-awaited method for manufacturing a semiconductor device that can suppress crystal defects that occur during the manufacturing process of the semiconductor device having the ■Sol structure as described above, and can easily reduce the surface impurity concentration of the ■Sol substrate.

[Problem to be solved by the invention]

The problem with conventional Sol technology is that after the wafers are bonded together, high-temperature, long-term heat treatment is required to diffuse impurities, and this heat generates crystal defects in the silicon crystal, which can lead to device deterioration. The two problems are that autodoping occurs during shrimp growth due to the high impurity concentration near the surface of the soy substrate, which slows down the operation of the device.

The present invention is an attempt to solve these two problems faced by the conventional technology at once, and it aims to: 1) suppress crystal defects that occur during the manufacturing process of devices using SOI substrates, and 2) reduce the surface impurity concentration of SOI substrates. The purpose of the present invention is to provide a method for manufacturing a semiconductor device that can be easily manufactured in low cost.

[Means to solve the problem]

In order to achieve this object, the present invention includes the steps of forming an insulating layer on at least one of the first main surface of the first semiconductor wafer and the first main surface of the second semiconductor wafer;
a step of adding a conductivity type impurity to a surface opposite to the first main surface of the semiconductor wafer to form an impurity layer; a step of bonding together the first main surfaces of two semiconductor wafers to form a substrate; a step of etching away the first semiconductor wafer of the substrate until the impurity layer is exposed;
The method includes a step of forming an impurity region having a conductivity type different from that of the impurity layer.

[Effect]

The occurrence of crystal defects associated with SOR manufacturing technology is caused by stress in silicon crystals due to heating during the manufacturing process. Therefore, in order to reduce crystal defects in silicon crystals, long-term heating can be eliminated from the manufacturing process after wafers are bonded together.

Furthermore, when impurities are diffused into a silicon substrate, the impurity concentration becomes highest at a shallow position from the diffusion surface, as shown in FIG. Therefore, if you face the opposite side of the diffusion surface, so
The impurity concentration near the y-substrate surface can be lowered.

In the present invention, the impurity diffusion process by high-temperature heat treatment is performed on SOI.
Since the process is completed before the structure is completed, no thermal stress is applied and no crystal defects occur.

Furthermore, since the wafer is ground from the back side, the surface impurity concentration can be lowered, and autodoping during shrimp growth can be avoided.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a process diagram for manufacturing a CMOS device using bonded SOI technology according to an embodiment of the present invention. In the figure, 1 is the first semiconductor wafer.

2 is a second semiconductor wafer, 3 is an oxide layer, and 4 is an impurity.

41 is an n-type impurity layer, 42 is an n-type impurity layer, 45 is a high concentration region, and 10 is a substrate.

See Figure 1(a): 625 μm thick surface orientation (100
) are prepared, and B (boron) ions are implanted at a concentration of about 10"cs+-" from the surface of the first semiconductor wafer 1 into a region that will become a p-well. In addition, P (phosphorus) ions are implanted at a concentration of about 10110l2'' into the region that will become the n-well.To explain in detail, the surfaces of the prepared first and second semiconductor wafers are oxidized or vapor-phase grown to form a wafer. Oxide layer 3 on the surface with a thickness of approximately 0
．． 02 to 10 μm. After that, ions are implanted into the surface of the first semiconductor wafer, and then the temperature is increased to 1200°C to 1250°C.
, N, (nitrogen) atmosphere for 3 hours to diffuse impurities and form an n-Wel I + p-Wel 1 layer. In this way, the p-type impurity layer 41. n-type impurity layer 42
is approximately 3 μm to 5 μm deep. After diffusing impurities,
A high concentration region 45 with a high impurity concentration is formed near the impurity implantation surface of the wafer. In this embodiment, ions are implanted through an oxide layer formed on the wafer surface to prevent channeling. However, although it is preferable to implant ions through the oxide film, it is not necessary.

Refer to FIG. 1(b): The oxide film 31 on the surface of the first semiconductor wafer 1 on which impurities have been diffused is removed by using, for example, HF (hydrofluoric acid). Note that this oxide film 31 removal process is
Not necessarily necessary.

Refer to FIGS. 1(C) and (d): The diffused surface of the first semiconductor wafer 1 and the surface of the second semiconductor wafer 2 are overlapped, and a pulse of ±100ν to ±500v is directly applied.
Temporarily bond by reducing the pressure to about 'Pa. Next, both wafers are completely bonded together by heating with a carbon heater or the like at 1100° C. for 930 minutes in a nitrogen atmosphere.

See FIGS. 1(e) and 1(f): Next, the p-type impurity layer 41 is polished to a thickness of approximately 0.5 to 5 μm from the surface opposite to the surface on which the impurity is diffused. The n-type impurity layer 42 is exposed. The exposed impurity layers 41 and 42 can be formed with a lower impurity concentration than the conventional ones.

The substrate 10 with the impurity layers 41 and 42 exposed is shown in FIG. 1(f). Thereafter, a CMOS device is manufactured through a normal element forming process.

Refer to FIG. 1(g): An oxide film 1 is formed on the surface of this substrate 10.
5 is formed by CVD. This oxide film 15 is used for the subsequent trench isolation, and has an opening corresponding to the position where the trench groove is to be opened.

Refer to FIG. 1(h): Both impurity layers (n-Well 41
1 and p-Well 412) using an oxide film as a mask, RIE is performed using the formed oxide film 15 as a mask.
Drill holes using (reactive ion etching) until the oxide layer 3 is exposed.

See Figure 1(i): On the side of this hole, n-Wel1
411 and p-Well 412, C
Form an oxide film using VD.

Refer to FIG. 1 (j) 2 CV on the impurity layer forming surface of the substrate 10
D-5i layer 9 is grown in vapor phase. The grooves formed above are also filled.

See FIG. 1(k): CVD-3ii 9 formed above.
is left only inside the groove of the substrate IO, and CVD is performed on other surface parts.
The Si layer is removed by applying a mixed solution of HF (hydrofluoric acid) and HNO3 (nitric acid).

Refer to FIG. 1(1): Next, the oxide film 15 on the impurity layer forming surface is removed using hydrofluoric acid.

Refer to FIG. 1(m) 2. Next, after growing an oxide film and a nitride film over the entire surface, an opening is formed in the element isolation region (center of the drawing), and thermal oxidation is performed using the nitride film 16 as a mask. Wel
A thick oxide film is formed to insulate and isolate the p-well 411 and the p-well 412.

See FIG. 1(n): Nitride film 16. After removing the oxide film 15, an oxide film is formed by CVD over the entire impurity layer formation surface of the substrate, and polycrystalline silicon, which will become the gate electrode 7, is formed on the surface of this oxide film. Next, the oxide film below the gate electrode 7 is left as the gate oxide film 6, and the rest is removed with HF (hydrofluoric acid).

Refer to FIG. 1 (0) 2 Next, using this gate electrode 7 as a mask, p-type impurity 502 is added to the n-Well 411.
(B" ions) and n-type impurity 501 (As"" ions) were implanted into the p-well 412, and the source was formed.

Form a drain layer. Of course, these source and drain ions may be implanted through the oxide film.

As explained above using the embodiments, according to the manufacturing method of the present invention, there is no step of impurity diffusion by long-term high-temperature heating after wafer bonding, so thermal stress is not accumulated on the SO2 substrate ( Crystal defects are less likely to occur in the substrate 10. Furthermore, in the configuration of the present invention, since the surface of the first semiconductor wafer 1 into which the impurities have been implanted is turned over and bonded to the surface of the second semiconductor wafer 2, the Sol The impurity concentration on the substrate surface can be lowered, and the device can operate at high speed.

Note that the present invention is not limited to the above-mentioned embodiments, and can be modified in many ways. In this embodiment, the manufacturing process of an OS (complementary MOS) device has been described, but It can also be applied to devices. Also,
For example, there may be an insulating film on only one of the surfaces to be bonded, or it is also possible to remove the insulating film after forming the diffusion layer, form a new insulating film, and then bond.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to realize a method for manufacturing a semiconductor device that can suppress crystal defects generated during the SO1 manufacturing process and easily reduce the surface impurity concentration of the SOI substrate.

[Brief explanation of drawings]

FIG. 1 shows a laminated SO according to an embodiment of the present invention.
Figure 2 is a diagram of the manufacturing process of CMOS devices using technology.
Diagram of the concentration profile of the substrate surface doped with impurities, Part 3
The figure is a manufacturing process diagram of a conventional bonded SO1 substrate. In the figure, 1...first semiconductor wafer, 2...second semiconductor wafer. 3... Oxide layer (insulating layer), 31... Oxide layer, 4...
- Impurity 241...p-type impurity layer, 42...n-type impurity layer, 411...n-Well, 412...
p-Well, 45-high concentration region, 51/n-type layer, 5
2... P-type layer, 6... Gate oxide film, 7... Gate electrode, 9... CVD-5i layer, 10... Substrate, 1
5... Oxide film, 16... Nitride film, 501... N-type impurity (arsenic ion), 502... P-type impurity (boron ion). '# f 圀で／Il whisper fJ zono 2 A (loincloth wa ka sea kaban et al. Ij 1 = regular C what θS ten \ isri 稟 ￥zanio L (mistake Q4 49 threshold 1M #iSahaJltl] CMθS ten\°Isu no crack y 艷工 1tl こ'gf Q3 not thing LIEJIrJt da knillfiy' lower r4 rvty15 2 Kugugu Jun 6 yen contribution 1; regular CMθ3 8゛Isu manufacturing engineering, punishment 'l & I) 5 Sub-A (more fortune-telling ρNtsu C5θz) k-piece fabrication engineering [薯] 3rd t] 7!

Claims (1)

[Scope of Claims] A step of forming an insulating layer (3) on at least one of the first main surface of the first semiconductor wafer (1) and the first main surface of the second semiconductor wafer (2); a step of adding a conductivity type impurity (4) to a surface opposite to the first main surface of the first semiconductor wafer (1) to form an impurity layer (41); forming a substrate (10) by bonding a surface opposite to the first main surface of the second semiconductor wafer (2) to the first main surface of the second semiconductor wafer (2); etching away the wafer (1) until the impurity layer (41) is exposed; and forming an impurity region of a conductivity type different from that of the impurity layer (41) in the exposed impurity layer (41). A method for manufacturing a semiconductor device, comprising the steps of: