JPH02244927A - Measuring instrument for processing capability - Google Patents

Measuring instrument for processing capability

Info

Publication number
JPH02244927A
JPH02244927A JP1065325A JP6532589A JPH02244927A JP H02244927 A JPH02244927 A JP H02244927A JP 1065325 A JP1065325 A JP 1065325A JP 6532589 A JP6532589 A JP 6532589A JP H02244927 A JPH02244927 A JP H02244927A
Authority
JP
Japan
Prior art keywords
measured
packet
information
processing capability
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1065325A
Other languages
Japanese (ja)
Inventor
Shigeru Nara
奈良 茂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1065325A priority Critical patent/JPH02244927A/en
Publication of JPH02244927A publication Critical patent/JPH02244927A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To inspect the internal operation state of a device measured to be by analyzing receiving dat inputted to counter circuits for counting up the changes of signals inputted from external terminals and packet receiving equipment for monitoring and inputted packet data transmitted/received to/from various devices in the device to be measured and calculating the processing capability of an information communication equipment. CONSTITUTION:The processing capability measuring instrument 1 is provided with the counter circuits 2, 3 for counting up the changes of signals obtained from the external terminals of a device to be measuring, the packet receiving equipments 4, 5 for monitoring and inputting packet data transmitted/received to/from various devices in the device to be measured packet storage devices 6, 7 for comparing the inputted packet data with plural previously stored patterns, and an information processor 9 for analyzing receiving data and calculating the processing capability of the device to be measured. A change in the internal state and transfer data between modules and between system are collected from information lines connected to the external terminals of the device to be measured without adding any change to the device to be measured. Consequently, the internal operation state of the device to be measured can be cleared.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は処理能力測定装置に関し、特に情報通信機器の
処理能力を測定する処理能力測定装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a processing capacity measuring device, and more particularly to a processing capacity measuring device for measuring the processing capacity of information communication equipment.

〔従来の技術〕[Conventional technology]

従来の情報通信機器の処理能力を測定する方法としては
、外部に設けた疑似負荷装置から被測定装置に負荷を掛
け、被測定装置内の中央制御装置の占有時間を、中央制
御装置臼らが測定することにより、負荷と占有時間との
関係から占有率等を算出し処理能力を測定していた。
The conventional method for measuring the processing capacity of information and communication equipment is to apply a load to the device under test from a pseudo load device installed externally, and measure the occupied time of the central controller in the device under test. By measuring, the occupancy rate etc. were calculated from the relationship between the load and the occupancy time, and the processing capacity was measured.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の情報通信機器の処理能力を測定する方法
は、被測定装置内らが占有時間を測定し占有率等を算出
するため、被測定装置自身にこの種のソフトウェアを組
込む必要があり、特にきめの細かい測定を行うには、多
大のソフトを組込み処理を行うため、処理能力を測定す
ることが、被測定装置自身の処理能力を落すことになる
という問題点がある。又、被測定装置の占有率が高くな
り、100%に近づいた状態では、この被測定装置から
出力された占有率そのものが必ずしも信用できるもので
あるとはいえず、この100%に近いオーバロード状態
での被測定装置の動作状態の把握ができないという問題
点もある。
In the conventional method of measuring the processing capacity of information communication equipment described above, the device under test measures the occupancy time and calculates the occupancy rate, etc., so it is necessary to incorporate this type of software into the device under test itself. In particular, in order to perform detailed measurements, a large amount of software is incorporated and processing is required, so there is a problem in that measuring the processing capacity will reduce the processing capacity of the device to be measured itself. Furthermore, when the occupancy rate of the device under test becomes high and approaches 100%, the occupancy rate itself output from the device under test cannot necessarily be trusted; Another problem is that it is not possible to grasp the operating state of the device under test.

本発明の目的は、被測定装置には何等の変更も加えず、
被測定装置の外部端子に接続した情報線から、内部状態
の変化およびモジュール間およびシステム間の転送デー
タを収集し、被測定装置の内部動作状態を明らかにする
ことの可能な処理能力測定装置を提供することにある。
The purpose of the present invention is to avoid making any changes to the device under test.
A processing capacity measurement device that collects internal state changes and transfer data between modules and systems from the information line connected to the external terminal of the device under test, and can clarify the internal operating state of the device under test. It is about providing.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の処理能力測定装置は、被測定装置の外部端子に
接続しこの外部端子上の信号の変化を計数する少なくと
も一つのカウンタ回路と、前記被測定装置内の各種装置
の送受するパケットデータを監視し取入れるパケット受
信装置と、前記カウンタ回路と前記パケット受信装置と
が取入れた受信データを分析し情報通信機器の処理能力
を算出する機能を持つ情報処理装置とを有する構成であ
る。
The processing capacity measuring device of the present invention includes at least one counter circuit that is connected to an external terminal of the device under test and counts changes in a signal on the external terminal, and a counter circuit that is connected to an external terminal of the device under test and counts changes in a signal on the external terminal, and a counter circuit that measures packet data transmitted and received by various devices in the device under test. The configuration includes a packet receiving device that monitors and receives data, and an information processing device that has a function of analyzing the received data received by the counter circuit and the packet receiving device and calculating the processing capacity of the information communication device.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.

処理能力測定装置1は、情報線a、bで図示されていな
い被測定装置の外部端子に接続し、この外部端子上の信
号の変化を計数するカウンタ回路2.3と、情報線e、
dで被測定装置内の各種装置の送受するパケットデータ
を監視し取入れるパケット受信装置4.5と、パケット
受信装置4゜5の取入れたパケットデータと予め記憶し
である複数のパターンと入力パケットデータとを比較す
るパケット記憶装置6.7と、カウンタ回路2゜3とパ
ケット受信装置4.5とが取入れた受信データを共通バ
ス8を介して受け、分析して被測定装置の処理能力を算
出する機能を持つ情報処理装置9とを含んでいる。情報
処理装置9は、受信したデータを時刻を付加して記憶す
るための記憶装置10と接続している。又、処理能力測
定の条件の入力および測定結果の出力を行うための、外
部入出力装置30が接続されている。
The processing capacity measuring device 1 includes a counter circuit 2.3 that is connected to an external terminal (not shown) of the device under test via information lines a and b, and counts changes in a signal on the external terminal, and an information line e,
A packet receiving device 4.5 monitors and takes in the packet data sent and received by various devices in the device under test, and the packet receiving device 4.5 receives the packet data taken in by the packet receiving device 4.5 and a plurality of pre-stored patterns and input packets. The packet storage device 6.7 for comparing data, the counter circuit 2.3, and the packet receiving device 4.5 receive the received data via the common bus 8 and analyze it to determine the processing capacity of the device under test. It includes an information processing device 9 having a calculation function. The information processing device 9 is connected to a storage device 10 for storing received data with time added thereto. Also connected is an external input/output device 30 for inputting conditions for processing capacity measurement and outputting measurement results.

第2図は本発明を適用した情報通信機器の処理能力測定
例のブロック図である。
FIG. 2 is a block diagram of an example of measuring the processing capacity of an information communication device to which the present invention is applied.

被測定装置である情報通信機器11は、加入者線と接続
し多重化する加入者線多重化装置12と、加入者線多重
化装置12と接続し加入者線の信号を処理する加入者線
信号処理装置13と、回線を交換する時分割通話路14
と、時分割通話路14を制御する通話路制御装置15と
、パケット通信に使用するパケット通信装置16と、回
線交換の呼の接続に使用する回線交換用トランク17と
、加入者線信号処理装置13および通話路制御装置15
と、CCITT  No、7信号方式に基づきパケット
化したブロックの転送を行う共通バス18を介して接続
し、これらの制御処理装置を制御し交換動作を行う中央
制御装置19とを含んでいる。
Information communication equipment 11, which is a device to be measured, includes a subscriber line multiplexing device 12 that connects to and multiplexes subscriber lines, and a subscriber line multiplexing device 12 that connects to subscriber line multiplexing device 12 and processes subscriber line signals. Signal processing device 13 and time division communication path 14 for exchanging lines
, a communication path control device 15 that controls the time division communication path 14, a packet communication device 16 used for packet communication, a circuit switching trunk 17 used for connection of circuit switching calls, and a subscriber line signal processing device. 13 and communication path control device 15
and a central control unit 19 that is connected via a common bus 18 that transfers packetized blocks based on the CCITT No. 7 signaling system, and that controls these control processing units and performs exchange operations.

又、加入者線多重化装置12の加入者線側には、疑似負
荷を発生する疑似負荷発生装置20が接続されている。
Further, a pseudo load generator 20 that generates a pseudo load is connected to the subscriber line side of the subscriber line multiplexing device 12.

パケット通信装置16にはデータ回線21が接続されて
いる。そして、第1図に示した処理能力測定装置1との
間に、各装置に設けられている外部端子に情報線a、b
、c、dが接続されている。
A data line 21 is connected to the packet communication device 16 . Information lines a and b are connected to external terminals provided in each device between the processing capacity measuring device 1 shown in FIG.
, c, and d are connected.

次に動作について説明する。Next, the operation will be explained.

測定開始に先立ち、試験者は、外部入出力装置30から
測定モードと測定時間とを設定する。同時に疑似負荷発
生装置20を動作開始させる。情報処理装置9は、前述
の設定に基づき、カウンタ回路2,3とパケット受信装
置4,5に対し、収集モード設定後収集開始を指令する
。情報処理装置9はそれ自身時限回路を備えている。中
央制御装置19は、接続する情報線aに対し、呼処理中
は一定の間隔でパルスを発生し、休止中はパルスを発生
しない、カウンタ回路2は、発生したパルスを受信する
と、このパルス受信を情報処理装置9に通知する。パケ
ット通信装置16も又同様に、接続する情報線すに対し
、呼処理中は一定の間隔でパルスを発生し、休止中はパ
ルスを発生しない。
Prior to starting the measurement, the tester sets the measurement mode and measurement time using the external input/output device 30. At the same time, the pseudo load generator 20 is started to operate. Based on the above settings, the information processing device 9 instructs the counter circuits 2 and 3 and the packet receiving devices 4 and 5 to start collection after setting the collection mode. The information processing device 9 itself is equipped with a timer circuit. The central control unit 19 generates pulses at regular intervals during call processing to the connected information line a, and does not generate pulses during rest. When the counter circuit 2 receives the generated pulses, the counter circuit 2 receives the generated pulses. is notified to the information processing device 9. Similarly, the packet communication device 16 generates pulses at regular intervals to the connected information line during call processing, and does not generate pulses during rest.

同様に、カウンタ回路3は、発生したパルスを受信する
と、このパルス受信を情報処理装置9に通知する。情報
線Cは、共通バス8に接続し、情報線dは、パケット通
信装置16に接続して、各装置間および各システム間で
送受するパケットデー夕を監視し取入れる。パケット受
信装置4,5の取入れたパケットデータと予めパケット
記憶装置6.7に記憶しである複数のパターンとを比較
し、一致した場合には、パケット受信装置4,5は、一
致したパケットデータを情報処理装置9に転送する。パ
ルス受信の通知あるいはデータの転送を受けた情報処理
装置9は、それらのデータに受信した時刻を付加して記
憶装置10に記憶する。試験者からの終了コマンド又は
、予めスタートコマンドで指定した時刻がきたとき、前
述の動作を終了する。収拾されたデータは、情報処理装
置1が持つデータ出力装置に出力される0例えば、フロ
ッピーディスクに転送する。フロッピーディスクに格納
されたデータは、別のコンピュータで処理される。
Similarly, upon receiving the generated pulse, the counter circuit 3 notifies the information processing device 9 of the reception of the pulse. The information line C is connected to the common bus 8, and the information line d is connected to the packet communication device 16 to monitor and take in packet data sent and received between each device and between each system. The packet data taken in by the packet receiving devices 4 and 5 are compared with a plurality of patterns stored in advance in the packet storage device 6.7, and if they match, the packet receiving devices 4 and 5 store the matched packet data. is transferred to the information processing device 9. The information processing device 9 that receives the pulse reception notification or the data transfer adds the reception time to the data and stores it in the storage device 10. When the end command from the tester or the time specified in advance by the start command arrives, the above-mentioned operation ends. The collected data is output to a data output device of the information processing device 1, for example, transferred to a floppy disk. The data stored on the floppy disk is processed by another computer.

第3図は本発明の一実施例のパケットデータ収集動作の
流れ図である。
FIG. 3 is a flowchart of a packet data collection operation according to an embodiment of the present invention.

測定を開始すると、ステップ31でパケットデータを読
込み、ステップ32でパケット記憶装置内に記憶されて
いる比較パターンと比較し、ステップ33で一致するか
否かを検出し、一致していればステップ34で時刻情報
を付加して記憶装置に記憶する。この動作を時刻又は終
了コマンドを受信するまで繰返す。
When measurement starts, the packet data is read in step 31, compared with the comparison pattern stored in the packet storage device in step 32, and it is detected in step 33 whether or not they match, and if they match, step 34 is performed. time information is added and stored in the storage device. This operation is repeated until the time or end command is received.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、被測定装置には何等の
変更も加えず、被測定装置の外部端子に接続した情報線
から、内部状態の変化およびモジュール間およびシステ
ム間の転送データを収集し、被測定装置の内部動作状態
を明らかにすることが可能となる効果が有る。
As explained above, the present invention collects internal state changes and data transferred between modules and systems from the information line connected to the external terminal of the device under test without making any changes to the device under test. However, it has the effect of making it possible to clarify the internal operating state of the device under test.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例のブロック図、第2図は本発
明を適用した情報通信機器の処理能力測定例のブロック
図、第3図は本発明の一実施例のパケットデータ収集動
作の流れ図である。 l・・・・・・処理能力測定装置、2,3・・・・・・
カウンタ回路、4.5・・・・・・パケット受信装置、
6,7・・・・・パパケット記憶装置、8,18・・・
・・・共通バス、9・・・・・・情報処理装置、10・
・・・・・記憶装置、11・・・・・・情報通信機器、
12・・・・・・加入者線多重化装置、13・・・・・
・加入者線信号処理装置、14・・・・・・時分割通話
路、15・・・・・・通話路制御装置、16・・・・・
・パケット通信装置、17・・・・・・回線交換用トラ
ンク、19・・・・・・中央制御装置、20・・・・・
・疑似負荷発生装置、21・・・・・・データ回線、3
0・・・・・・外部入出力装置、a。 b、c、d・・・・・・情報線。 代理人 弁理士  内 原  晋 塙 凹
FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of an example of processing capacity measurement of an information communication device to which the present invention is applied, and FIG. 3 is a packet data collection operation of an embodiment of the present invention. This is a flowchart. l... Processing capacity measuring device, 2, 3...
Counter circuit, 4.5...Packet receiving device,
6, 7... Packet storage device, 8, 18...
...Common bus, 9...Information processing device, 10.
... Storage device, 11 ... Information communication equipment,
12... Subscriber line multiplexing device, 13...
・Subscriber line signal processing device, 14... Time division communication path, 15... Communication path control device, 16...
・Packet communication device, 17...Line switching trunk, 19...Central control unit, 20...
・Pseudo load generator, 21...Data line, 3
0...External input/output device, a. b, c, d... Information line. Agent Patent Attorney Shinhan Uchihara

Claims (1)

【特許請求の範囲】[Claims] 被測定装置の外部端子に接続しこの外部端子上の信号の
変化を計数する少なくとも一つのカウンタ回路と、前記
被測定装置内の各種装置の送受するパケットデータを監
視し取入れるパケット受信装置と、前記カウンタ回路と
前記パケット受信装置とが取入れた受信データを分析し
情報通信機器の処理能力を算出する機能を持つ情報処理
装置とを有することを特徴とする処理能力測定装置。
at least one counter circuit that is connected to an external terminal of the device under test and counts changes in a signal on the external terminal; a packet receiving device that monitors and takes in packet data transmitted and received by various devices in the device under test; A processing capacity measuring device comprising: an information processing device having a function of analyzing received data taken in by the counter circuit and the packet receiving device and calculating the processing capacity of an information communication device.
JP1065325A 1989-03-17 1989-03-17 Measuring instrument for processing capability Pending JPH02244927A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1065325A JPH02244927A (en) 1989-03-17 1989-03-17 Measuring instrument for processing capability

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1065325A JPH02244927A (en) 1989-03-17 1989-03-17 Measuring instrument for processing capability

Publications (1)

Publication Number Publication Date
JPH02244927A true JPH02244927A (en) 1990-09-28

Family

ID=13283650

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1065325A Pending JPH02244927A (en) 1989-03-17 1989-03-17 Measuring instrument for processing capability

Country Status (1)

Country Link
JP (1) JPH02244927A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6493655B1 (en) 1999-06-25 2002-12-10 Nec Corporation Apparatus for measuring throughput and method of measuring throughput

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6493655B1 (en) 1999-06-25 2002-12-10 Nec Corporation Apparatus for measuring throughput and method of measuring throughput

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