JPH02244823A - A/d converter - Google Patents

A/d converter

Info

Publication number
JPH02244823A
JPH02244823A JP6434189A JP6434189A JPH02244823A JP H02244823 A JPH02244823 A JP H02244823A JP 6434189 A JP6434189 A JP 6434189A JP 6434189 A JP6434189 A JP 6434189A JP H02244823 A JPH02244823 A JP H02244823A
Authority
JP
Japan
Prior art keywords
voltage
circuit
output
conversion
output voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6434189A
Other languages
Japanese (ja)
Inventor
Takehisa Matsuura
松浦 武久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6434189A priority Critical patent/JPH02244823A/en
Publication of JPH02244823A publication Critical patent/JPH02244823A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To obtain an A/D converter which can extend a measuring range without changing a D/A conversion circuit by performing the voltage comparison of an input signal with second and third comparators. CONSTITUTION:The input signal Sa is compared with the output voltage of a reference voltage generation circuit 4 by a second voltage comparator 2b, and also, the output voltage of the reference voltage generation circuit 4 is compared with a result amplified by an amplifier 8 by a third voltage comparator 2c. The above results are used in the judgement of two most significant bits as the A/D converter, and the output voltage of the reference voltage generation circuit 4 is supplied as an offset voltage to an adder circuit 10. Therefore, the output of the adder circuit in which the output voltage of the D/A conversion circuit 5 is added on the output voltage of the reference voltage generation circuit 4, or that of the adder circuit in which the former is added on the output voltage of the amplifier is supplied to a first voltage comparator 2a, then, A/D conversion is performed. In such a manner, the measuring range can be extended.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、被計測信号としてアナログ信号を取り扱う
計測分野に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the field of measurement that handles analog signals as signals to be measured.

〔従来の技術〕[Conventional technology]

第2図は、従来の逐次比較型A/D変m装考であり1図
においてS!1ij被計測信号、(1)は被計測信号を
インピーダンス変換するバッファ回路、(2)は上記被
計測信号とD/A変換回路(4(の信号を電圧比較する
電圧比較型コンパレータ、(3)は電圧比較型コンバレ
ー4(2)の信号を蓄積する逐次比較レジス4,74)
は基準電圧発生回路、15)は上記苓鵡電圧発生回路(
4)の電圧を入力し逐次比較レジスタ(3)のデータに
対応したアナログ電圧を発生させるD/A変搗回路、(
6)は上紀装竜の動作のタイミングを1伸するタイミン
グ回路、DaはA/D変換値である。
Figure 2 shows a conventional successive approximation type A/D transformation system, and in Figure 1, S! 1ij signal to be measured, (1) is a buffer circuit that converts the impedance of the signal to be measured, (2) is a voltage comparison type comparator that compares the voltage of the signal to be measured and the D/A conversion circuit (4), (3) is a successive approximation register 4, 74) that accumulates the signal of voltage comparison type converter 4 (2).
15) is the reference voltage generation circuit, and 15) is the above-mentioned parrot voltage generation circuit (
A D/A converter circuit which inputs the voltage of 4) and generates an analog voltage corresponding to the data of the successive approximation register (3);
6) is a timing circuit that increases the timing of the movement of the Joki Souryu by 1, and Da is an A/D conversion value.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記構成によるとA/D変換装置の計測範囲はD/A変
換回路そのものの分解能によっての入装竜の分野能が快
定されるため計測範囲を拡大させるためにはより良い分
解能を有したD/A変換回路が必要となり価格の増加を
招くという課題があった。
According to the above configuration, the measurement range of the A/D conversion device is determined by the resolution of the D/A conversion circuit itself, so in order to expand the measurement range, it is necessary to use a D with better resolution. There was a problem in that a /A conversion circuit was required, leading to an increase in price.

この発明はかかる課題を解消するためになされたもので
、D/A変櫓回路をf更することなく計測Q弗を拡大で
きるA/D変換装・賃を得ることを目的とする。
This invention was made to solve this problem, and aims to provide an A/D converter that can expand the measurement Q without changing the D/A converter circuit.

〔胃襲題を解決するための手段〕[Means to solve stomach problems]

この発明に備わるA/D変換装賃は、入力信号S5を第
二のコンパレータ及び第三のコンパレータによって電子
比較することによつ゛(h/n変換回路としての最上位
2ビツトの判定を行い、加算回路へのオフセット電圧を
供給するか否か割判している。
The A/D conversion equipment provided in this invention electronically compares the input signal S5 with a second comparator and a third comparator, thereby determining the most significant two bits as an h/n conversion circuit. It is determined whether or not to supply the offset voltage to the adder circuit.

このため1本俸(は従来の計測範囲に比べ3倍の計測範
囲を有することができる。
Therefore, 1 piece of paper can have a measurement range three times larger than the conventional measurement range.

〔作用〕[Effect]

この発明に係わるA / D変換製電は、入力信号BS
を第二の電圧比較コンパレータによって基準電圧発生回
路の出力1圧と比較すると共に、第三の電圧比較コンパ
レータによって苓P1電圧発生回路の出力電圧を増1幅
器にて増幅した結果と比較する。その結果がA/D変換
装竜としての4上位2ビットの判定となり、その結果を
タイミング回路へ入力する。その結果、仮に第二の電圧
比較コンパレータ及び第三の゛電圧比較コンパレータの
比較結果が上記基準電子発生回路の出力電圧を超ないと
判定した場合、上記第一のスイッチ回路を絶縁状態とし
上記基準電圧発生回路の出力1itlEを加算回路への
オフセット電圧として供給し々いよう上記第一のスイッ
チ回路を制倒し、従来のA/D変換を実施する。また、
第二の′電圧比較コンバレー〃比較結果のみが−F記基
準電圧発生回路の剛力電圧を超えたと判定した場合、上
記タイミング回路は上記第一のスイッチ回路を上記基準
電圧発生回路の出力電圧に選択し、上記基準電圧発生回
路の出力電圧を上記?70篭回路へのオフセット電圧き
して供給する。したがって第一〇電圧比較コンパレータ
へはD/A変準変格回路力電圧プラス上記基@電子発生
回路の出力電圧をη0箆した上記加算回路出力が供給さ
れA/D変襖を実侑する。さらに第三の1圧比較コンパ
レータも超えたと判定した場合お上記タイミング回路は
−F記第−のスイッチ回路をゲイン2倍の増幅器出力電
圧に選択し、第一の電圧比較コンパレータへはD/A変
換回路の出力礪王プラス上記増幅器用力電圧を加すした
上記加算回路出力が供給されA/Df換を実施する。
The A/D conversion electric manufacturing device according to the present invention converts the input signal BS
is compared with the output voltage of the reference voltage generation circuit by the second voltage comparison comparator, and compared with the result of amplifying the output voltage of the P1 voltage generation circuit by the amplifier by the third voltage comparison comparator. The result is the judgment of the 4 upper 2 bits as an A/D converter, and the result is input to the timing circuit. As a result, if it is determined that the comparison results of the second voltage comparison comparator and the third voltage comparison comparator do not exceed the output voltage of the reference electron generation circuit, the first switch circuit is insulated and the reference The first switch circuit is suppressed so that the output 1itlE of the voltage generation circuit is completely supplied as an offset voltage to the adder circuit, and conventional A/D conversion is performed. Also,
Second Voltage Comparison Combare If it is determined that only the comparison result exceeds the stiffness voltage of the reference voltage generation circuit described in -F, the timing circuit selects the first switch circuit as the output voltage of the reference voltage generation circuit. Is the output voltage of the reference voltage generation circuit above? The offset voltage is applied to the 70-meter circuit. Therefore, the voltage comparison comparator No. 10 is supplied with the output of the adder circuit which is the D/A conversion circuit output voltage plus the output voltage of the base@electron generation circuit η0, thereby implementing the A/D conversion. Furthermore, when it is determined that the voltage has exceeded the third voltage comparison comparator, the above-mentioned timing circuit selects the -F-th switch circuit as the amplifier output voltage with double the gain, and outputs the D/A voltage to the first voltage comparison comparator. The output of the adder circuit obtained by adding the output voltage of the converter circuit plus the power voltage for the amplifier is supplied to perform A/Df conversion.

このことにより従来のA/D変換変換装出べ3倍の計測
範囲を有することができる。
This makes it possible to have a measurement range three times that of conventional A/D conversion devices.

〔実施例〕〔Example〕

第1図は、この発明の一実施例を示す構成図である。 FIG. 1 is a configuration diagram showing an embodiment of the present invention.

図において、(l)から16)は−F記従来回路と全く
同一のものである。
In the figure, (l) to 16) are exactly the same as the conventional circuit indicated by -F.

上記第一図において、外部から入力される波計側信号S
11をバッファ回路(1)にてインビーターンス変換し
、第二の′電圧比較型コンパレータ(2b)にて上記基
準電圧発生回路(4)の出力1圧を比較し結果をレジス
タ回路(7)へ出力するとともにタイミング回路+61
へ入力するつまた第三〇゛心圧比較型コンパレータ(2
C)にて上記基準1圧発生回路14)の甲力をゲイン2
倍の増@ iM t81にて増幅した電圧を比較した結
果もレジスタ回路(7)及びタイミング回路l路f61
へ入力するつこの@果が本titの最上位2ビットの判
定結果きなゆ、上記タイミング回路(6)でjは第二の
1!王比較型コンパレータ(2b)及び第三の電子、比
較型コンパL−・−タ(2C)の結果をもきてスイッチ
回路・9)へ制@信号を出力する。例えば):記第二の
電圧比較型コンパレータ(2b)の比較時果。
In Figure 1 above, the wave meter side signal S input from the outside
11 is subjected to in-bitance conversion in the buffer circuit (1), and the output 1 voltage of the reference voltage generation circuit (4) is compared in the second voltage comparison type comparator (2b), and the result is sent to the register circuit (7). output to the timing circuit +61
Tsumata 30゛ Heart pressure comparison type comparator (2
In C), the instep force of the reference 1 pressure generation circuit 14) is set to gain 2.
The result of comparing the voltage amplified by doubling @ iM t81 is also the result of register circuit (7) and timing circuit f61.
The result of the input is the judgment result of the most significant two bits of this tit, and in the timing circuit (6) above, j is the second 1! The results of the comparison type comparator (2b) and the third electronic comparison type comparator (2C) are obtained and a control @ signal is output to the switch circuit 9). For example): Comparison result of the second voltage comparison type comparator (2b).

上記バッファ回路111の出力が上記基準イ圧発生回路
(4)の出力電圧よや小さいと判定した場合、上記タイ
ミング回路16+では上記スイッチ回路(9)をグラン
ド状態とするよう制葡し、上記$準電圧発生回路(4)
の出力電圧を加算回路1田へ供給しない。
When it is determined that the output of the buffer circuit 111 is slightly smaller than the output voltage of the reference voltage generating circuit (4), the timing circuit 16+ controls the switch circuit (9) to be in the ground state, and Quasi-voltage generation circuit (4)
The output voltage of is not supplied to the adder circuit 1.

これにより上記加算回路IIの出力電圧は、上記D/A
変換回路(5)の出力電圧きなろうこのため、第一の電
圧比較型コンパレータ(25)で上記加算回路(9)出
カイ圧と電圧比較することにより逐次比較型A/D変換
を行い、その結果は逐次比較レジスタ(3)に得ること
ができる。
As a result, the output voltage of the adder circuit II is the same as that of the D/A
For this reason, the output voltage of the conversion circuit (5) is small, so a first voltage comparison type comparator (25) performs successive approximation type A/D conversion by comparing the voltage with the output voltage of the adding circuit (9). The result can be obtained in the successive approximation register (3).

上記逐次比較レジスタ(3)の結果は、上記レジスタ回
路(71へ先の上記第二の電圧比較型コンパレータ(2
b)及び第三の(圧比較型コンバレー4 (2c)の結
果とともに蓄積・出力しA / D変換データDBとす
る。
The result of the successive approximation register (3) is sent to the second voltage comparison type comparator (2) which is forwarded to the register circuit (71).
b) and the results of the third (pressure comparison type combiner 4 (2c)) are accumulated and output as an A/D conversion data DB.

以上の動作により従来のA/D変4fI結果を得る事が
できる。
By the above operation, the conventional A/D variable 4fI result can be obtained.

また、上記第二の電圧比較型コンパレータ(2b)の比
較枯果、上記バッファ回路fl)の出力が上記基準電圧
発生回路(4(の出力電圧よ妙大きいと判定した場合、
上記タイミング回路(6)では上記スイッチ回路(9)
を上記苓帛(圧発生回路(4)の出力1fFEが導通状
態とするよう開−し、上記基準電圧発生「引ド(4)の
出力填圧を上記111[回路iIGへ@給する、1?:
れにより上記加算回路な1の出力電圧は、上記基準電圧
発生回路14)の出力電圧と上記D/A変換回路(5)
の出力電圧の1701[された電圧となる。さらに第一
・の電圧比II9型コンパレータ(2g)で上紀和″I
EfJIBilQ出力電圧さ1圧比較することにより逐
次比較型A/D変換を行い、その結果は逐次比較レジス
タ(3)に得るこきができる。
In addition, when it is determined that the output of the second voltage comparison type comparator (2b) and the buffer circuit fl) is unusually larger than the output voltage of the reference voltage generation circuit (4),
In the above timing circuit (6), the above switch circuit (9)
is opened so that the output 1fFE of the pressure generating circuit (4) becomes conductive, and the output filling pressure of the reference voltage generating circuit (4) is supplied to the circuit iIG. ?:
As a result, the output voltage of the adder circuit 1 is the output voltage of the reference voltage generating circuit 14) and the D/A converter circuit 5).
The output voltage is 1701[]. Furthermore, the voltage ratio of the first voltage ratio II9 type comparator (2g)
Successive approximation type A/D conversion is performed by comparing the EfJIBilQ output voltage by one voltage, and the result can be obtained in the successive approximation register (3).

上記逐次比較レジスタ(3)の結果は、上記レジスタ回
路(7)へ先の上記第二の直圧比較型コンパレータ(2
b)及び第三の電圧比較型コンパレータ(2C)の結果
とともに#潰・出力しA/D変神データDちとする。
The result of the successive approximation register (3) is sent to the second direct voltage comparator (2) to the register circuit (7).
b) and the results of the third voltage comparison type comparator (2C) are crushed and outputted as A/D transformation data D.

以上の動作により、従来のA/D変換結果に比べ2倍の
計測範囲を得る事ができる。
By the above operation, a measurement range twice as large as that of the conventional A/D conversion result can be obtained.

ま九、上記第三の電圧比較型コンパレータ(1C)の比
較結果1上記バッファ回路(1)の出力が上記増幅器(
8)の出力電圧より大きいと判定した場合、上記タイミ
ング回路16)では上記スイッチ回路(9)を上記f:
li!幅器;8)の出力電圧が導通状態とするよう制倒
し1.上記増ll@器(8)の出力11!圧を上記?+
111[回路Illへ供給する。これによシ上記加簀回
路aαの出力填圧は、11111幅器(8)の出力電圧
と上記D/A変換1可路(5)の出力電圧のη0算され
た電圧となる。さらに第一の電圧比較型コンパレータ(
2a)  でi N:1貴。
9. Comparison result 1 of the third voltage comparison type comparator (1C) The output of the buffer circuit (1) is the output of the amplifier (1C).
8), the timing circuit 16) switches the switch circuit (9) to the output voltage f:
li! Control so that the output voltage of width switch; 8) becomes conductive 1. Output 11 of the above multiplier (8)! Pressure above? +
111 [supply to circuit Ill. Accordingly, the output filling pressure of the summing circuit aα becomes a voltage obtained by multiplying the output voltage of the 11111 amplifier (8) by η0 of the output voltage of the D/A converter 1-channel (5). Furthermore, the first voltage comparison type comparator (
2a) Dei N:1 Takashi.

回路1111出力電圧と!圧比較することにより逐次比
較型A/Df換を行い、その結果は逐次比較レジスタ(
3)に得ることができる。
Circuit 1111 output voltage and! Successive approximation type A/Df conversion is performed by comparing the voltages, and the result is stored in the successive approximation register (
3) can be obtained.

上記逐次比較レジスタ(3)の結果は、上記レジスタ回
路(7)へ先の上記第二の電圧比較型コンパシ・・−タ
(2b)及び第三の電圧比較型コンパレータ(2C)の
結果ときもに蓄積・出力しA/D変換変換データ上9る
The result of the successive approximation register (3) is also the result of the second voltage comparison type comparator (2b) and the third voltage comparison type comparator (2C) which are sent to the register circuit (7). The A/D conversion data is stored and output.

以上の・動作によハ、従来のA/Df換結果に比べ3倍
の計測範囲を得る事ができる。
Through the above operations, it is possible to obtain a measurement range three times larger than the conventional A/Df conversion result.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば第二の電圧比較型コン
パレータ及び第三の1圧比較型コンパレータにより基m
i圧発生回路の電圧およびその2倍の電圧を比較するこ
とにより1本俸電の号1位2ビットを判定し加算回路へ
のオフセットM″+:としている。
As described above, according to the present invention, the second voltage comparison type comparator and the third one-voltage comparison type comparator are used to
By comparing the voltage of the i-voltage generating circuit and the voltage twice that voltage, the first and second bits of one voltage are determined and set as an offset M″+: to the adder circuit.

この操作によゆ従来のA /’ D変換装・竜に比べ3
倍の計測範囲を有することができるっ
Compared to the conventional A/'D conversion device/Dragon due to this operation, 3
Can have twice the measurement range

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例を示す装置の構成1図、第
21っは従来の装置【を示す構成1gである。v4にお
いて(+)はバッフアロ路、  (2!l) は第一〇
′′圧比較型コンパレータ、  (2b)  は第二〇
′笥正圧比較型コンハレー*、  (2c) h第Hの
電圧比較型コンパレータ、(3)は逐次比較レジスタ、
14)は基ff1i!圧発生回路、(5)はD/Af換
回路、 i6)はタイミング回路、(7)はレジスタ回
路、(8)は増幅器、19)はスイッチ回路、!11は
mxra路である。 なお1図中同一符号は同一または相当部分を丞すつ
FIG. 1 is a diagram showing the configuration of an apparatus according to an embodiment of the present invention, and FIG. 21 is a configuration 1g showing a conventional apparatus. In v4, (+) is a buffer arrow path, (2!l) is the 10'' pressure comparison type comparator, (2b) is the 20' positive pressure comparison type Conhaleley*, (2c) hth H voltage comparison Type comparator, (3) is successive approximation register,
14) is the base ff1i! pressure generation circuit, (5) is a D/Af conversion circuit, i6) is a timing circuit, (7) is a register circuit, (8) is an amplifier, 19) is a switch circuit,! 11 is the mxra path. In addition, the same symbols in one figure refer to the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 外部より与えられる被計測信号をインピーダンス変換す
るバッファ回路と、上記バッファ回路出力電圧とD/A
変換回路出力電圧とを電圧比較する第一の電圧比較型コ
ンパレータと、上記第一の電圧比較型コンパレータの比
較結果を入力するとともにタイミング回路によつて動作
速度を制御される逐次比較レジスタと、上記逐次比較レ
ジスタの出力をアナログ電圧に変換するD/A変換回路
と、上記D/A変換回路に基準電圧を供給する基準電圧
発生回路とから構成されるA/D変換装置において、上
記基準電圧発生回路出力電圧と項記バッファ回路出力と
を電圧比較する第二の電圧比較型コンパレータと、上記
基準電圧発生回路の出力電圧を増幅器により増幅した後
上記バッファ回路出力とを電圧比較する第三の電圧比較
型コンパレータと、上記D/A変換回路出力電圧と増幅
器出力電圧を上記タイミング回路により選択する第一の
スイッチ回路と、上記第一のスイッチ回路により選択さ
れた出力と上記D/A変換回路出力電圧とを電圧加算す
る加算回路とを備えたことを特徴とするA/D変換装置
A buffer circuit that converts the impedance of a measured signal given from the outside, and a D/A that converts the output voltage of the buffer circuit.
a first voltage comparison type comparator that compares the voltage with the conversion circuit output voltage; a successive approximation register into which the comparison result of the first voltage comparison type comparator is input and whose operating speed is controlled by a timing circuit; In an A/D conversion device that includes a D/A conversion circuit that converts the output of a successive approximation register into an analog voltage, and a reference voltage generation circuit that supplies a reference voltage to the D/A conversion circuit, a second voltage comparison type comparator that compares the voltage between the circuit output voltage and the buffer circuit output; and a third voltage that compares the output voltage of the reference voltage generation circuit with the buffer circuit output after amplifying the output voltage of the reference voltage generation circuit with an amplifier. a comparison type comparator, a first switch circuit for selecting the output voltage of the D/A conversion circuit and the output voltage of the amplifier by the timing circuit, an output selected by the first switch circuit and an output of the D/A conversion circuit; 1. An A/D conversion device comprising: an addition circuit that adds a voltage to a voltage.
JP6434189A 1989-03-16 1989-03-16 A/d converter Pending JPH02244823A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6434189A JPH02244823A (en) 1989-03-16 1989-03-16 A/d converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6434189A JPH02244823A (en) 1989-03-16 1989-03-16 A/d converter

Publications (1)

Publication Number Publication Date
JPH02244823A true JPH02244823A (en) 1990-09-28

Family

ID=13255446

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6434189A Pending JPH02244823A (en) 1989-03-16 1989-03-16 A/d converter

Country Status (1)

Country Link
JP (1) JPH02244823A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8957804B2 (en) 2012-10-30 2015-02-17 Asahi Kasei Microdevices Corporation Successive approximation A/D converter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8957804B2 (en) 2012-10-30 2015-02-17 Asahi Kasei Microdevices Corporation Successive approximation A/D converter

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