JPH02243020A - Test equipment for multi-stage synchronous counter - Google Patents

Abstract

PURPOSE:To attain quick test of a multi-stage synchronous counter by providing a test data generating circuit outputting a test data and a selection circuit receiving the test data and applying an output to the generating circuit selectively. CONSTITUTION:A test data generating circuit 1 outputs a test data TDATA whose effective binary data bit number is increasing in response to the application of a clock CLK. A multi-stage synchronous counter 3 in 10-bit outputs 10 sets of data TDATA only in response to the clock CLK. A selection circuit SEL 2 outputs the data TDATA to a counter 3 from the circuit 1 in the case of an enable test signal TEST. The counter 3 inputs the data TDATA to a data input terminal of each stage of circuits to apply the operation in response to the data TDATA. As a result, in the case of the counter 3, for example, number of times of the test is decreased to 10 thereby reducing the test time.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a multi-stage synchronous counter testing device for testing a state transition type multi-stage synchronous counter. For the purpose of conducting tests effectively, there is a test data generation circuit that outputs test data in which the number of bits of valid binary data increases sequentially in response to the application of a clock. and a selection circuit that selectively applies test data from the test data generation circuit as data input to the multistage synchronous counter for testing.

[Industrial application field]

The present invention particularly relates to a multistage synchronous counter testing device that can effectively perform rapid and comprehensive testing of state transition type multistage synchronous counters having a large number of bits with a simple circuit configuration.

State transition type multi-stage synchronous counters are used in various applications, such as frame synchronization circuits in multiple synchronizers of communication systems, and address counters for interfacing with RAM and ROM of computer systems. Such a multi-stage synchronous counter is an LSI
It is often used housed in a chip, and its operation is tested before it is actually used.

[Conventional technology]

FIG. 11 shows a circuit configuration of a conventional state transition type multi-stage synchronous counter. The state transition type multi-stage synchronous counter shown in FIG. 11 has a four-digit circuit configuration to simplify the drawing, but in reality, the number of bits is even larger, for example, 10 bits, that is, 2''=1024. Often configured to count.

The multi-stage synchronous counter in Fig. 11 has LSB-
It is configured to be the MSB. To briefly describe the circuit configuration and circuit operation of this multi-stage synchronous counter, for example, the circuit 130 for the next digit after the LSB is
It consists of a D gate 121, an exclusive OR gate (BXOR gate) 122, and a D-type flip-flop 124, whose output is the output state of the previous D-type flip-flop 111 and the output state of its own D-type flip-flop 124. configured as specified. Therefore, regarding the circuit 140 of the MSB digit, all the D-type flip-flops 111 to 131 are connected to the AND gate 141.
The output of the AND gate 141 applied to the EXOR gate 142 and the output of its own D-type flip-flop 144 are exclusive logically ORed to define its own output state. In this manner, each circuit state of the state transition type multi-stage synchronous counter is determined by the transition state of the previous stage circuit. This state transition type multi-stage synchronous counter is used as a synchronization counter.

[Problem to be solved by the invention]

When testing the multi-stage synchronous counter described above, data of "1" is sequentially input to the data input terminal of the LSB D-type flip-flop 111 in FIG.
The Q output of the type flip-flop is monitored to check the operation of each stage of the circuit as well as the overall operation.

However, if such a test method is used, if 1
In the case of a 0-bit multi-stage synchronous counter, data must be applied 1024 times and results must be checked 1024 times, which is a problem. In other words, we have encountered the problem that the testing effort is extremely heavy and the testing time is extremely long.

One way to solve this problem is to separate a 10-bit multi-stage synchronous counter into 4-bit, 4-bit, and 2-bit counters and test each counter independently and in parallel. It is being However, with such a method, it is not possible to test the overall operation of a multi-stage synchronous counter, that is, the operation that takes into account the connections between the separate units, and it is not possible to comprehensively test a multi-stage synchronous counter. There are still problems from the perspective of doing so.

It is an object of the present invention to solve the above-mentioned problems of requiring too much labor for testing, taking too much time for testing, and not being able to perform a comprehensive test by using a simple circuit configuration.

[Means to solve the problem]

FIG. 1 shows a block diagram of the principle of a multi-stage synchronous counter testing device according to the present invention.

In the figure, a selection circuit 2 and a test data generation circuit 1 are connected via the selection circuit 2 to a multistage synchronous counter 3 to be tested.

The multi-stage synchronous counter 3 itself has the same structure as the multi-stage synchronous counter 3 shown in FIG.

Note that, preferably, a reset circuit 4 is further provided.

[For production]

The test data generation circuit 1 outputs test data in which the number of valid binary data bits increases sequentially in response to the application of the clock CLKO.

That is, this test data is not simply 1-bit data, but the AND gate of each stage of the multi-stage synchronous counter 3, for example, the 111th! The test data TDATA according to the timing of each clock CLK is used as a signal of all bit states applied to the AND gate 141 of I.
Outputs 10 times. This test data TDATA is 10
In the case of BIT's multi-stage synchronous counter 3, the conventional
Instead of 0.024 pieces of data, only 10 pieces of data are output in response to the clock CLK. The test data T
An example of DATA is shown in the following table.

Table Kuraguchi-1 below: When the test signal TEST is enabled, the selection circuit 2 outputs the test data TDATA from the test data generation circuit 1 to the multistage synchronous counter 3.

The multi-stage synchronous counter 3 inputs the test data TDATA to the data input terminals of the circuits at each stage, and operates according to the test data TDATA.

As a result, for example, in the case of a 10-bit multi-stage synchronous counter 3, the number of tests that conventionally required 1024 is reduced to only 10, resulting in a significant reduction in test time. Furthermore, since the above test is automated, the testing effort is significantly reduced. Furthermore, the test data TDAT^ is basically input data to the circuits at each stage, but since it is data that takes continuity between circuits into consideration, a test that meets the purpose of a comprehensive test is performed.

Furthermore, as is clear from the circuit configuration shown in FIG. 1, the multistage synchronous counter testing apparatus of the present invention has a simple overall circuit configuration.

Note that when the test signal TBST is disabled, the selection circuit 2 applies the original count output 5COUNT from the multistage synchronous counter 3 to the multistage synchronous counter 3 itself, so that normal operation is performed.

That is, whether to enable the test signal TBST or
Multi-stage synchronous counter 3
It can be tested or operated normally. Therefore, the test equipment for the multi-stage synchronous counter is
Even if it is incorporated into an I chip or the like, there is an advantage that it can be easily tested not only in the factory but also in the field when the LSI chip is shipped.

Furthermore, by providing the reset circuit 4, when the multi-stage synchronous counter 100 counts up and the carry-out signal SC○ is output from the multi-stage synchronous counter 100, the reset signal RBSEIT is sent from the reset circuit 4 to the test data generation circuit 1. and test data generation circuit 1.
It becomes possible to return to the initial state again and repeat the above test.

〔Example〕

FIG. 2 shows a circuit diagram of an embodiment of the multi-stage synchronous counter testing device of the present invention.

In the figure, the test data generation circuit 1 shown in FIG. has been done. Further, the reset circuit 4 is realized by an initial value setting circuit 41.

FIG. 3 shows the circuit configuration of the test multi-stage synchronous counter 100 shown in FIG. 2. The test multi-stage synchronous counter 100 includes selectors 151-154 in addition to circuits 110-140 of each stage having the same configuration as the multi-stage synchronous counter 3 shown in FIG.
The selector circuit 150 corresponds to the selection circuit 2 consisting of the following. In the drawings, a four-stage counter configuration is illustrated for simplicity. In reality, there are more than 10 stages.

As is clear from FIG. 2, each selector 151 to 154
are the corresponding D-type flip-flops 111 to 111, respectively.
144 (DD input terminal and BX[]]R'7'-to 122
142, and is connected between the clock load signal generating circuit 11 and the load signal 5LOAD from the clock load signal generation circuit 11.
Test data signal TDO~ from shift register circuit 12
Apply TD3 to the D input terminals of each type flip-flop 111 to 141, or apply it to the original each type flip-flop 1.
The outputs from the Q output terminals 11 to 141 are applied to the D input terminal of the D-type flip-flop 111 at the next stage. In this example, the test data TDATA is composed of the above-mentioned 4 bits TOO to TD3.

Clock load signal generation circuit 11 and shift register circuit 12 cooperate to output test data TDATA in the form shown in Table 1 in response to clock CLK.

The operation of the multi-stage synchronous counter testing apparatus shown in FIGS. 2 and 3 will be described with reference to FIGS. 4(a)-(f) and FIGS. 5(a)-(e). Figures 4(a) to (f) are
The operation timing diagram in the initial state of the test is shown in Figure 5 (a).
) to (e) are operation timing charts showing the reset operation of the shift register circuit 12 when the multi-stage synchronous counter 3 counts up and the carry-out signal SCO is output.

First, the initial test state will be described with reference to FIGS. 4(a) to 4(f).

At time to, when the test signal TIEST becomes "high" enabled, the clock load signal generation circuit 11
is the shift clock 5 which is the frequency of the clock CLK divided by 1/2.
CLK and outputs the load signal 5LOAD (
, not shown).

As shown in FIG. 4(e), the shift register circuit 12 basically performs a load operation (LOAD) for loading data "1" applied to its data input signal terminal SI, a shift operation (SHIFT), and an increment operation (INC). therefore,
In the initial state at time t1, the output of the shift register circuit 12, that is, the test data TDO to TD3
is “0000”, and this test data TOO~TD3
Output 5C of multi-stage synchronous counter 100 for testing manually
OUNT becomes "0000".

Then, at time t4 when 1 is incremented, the output of the shift register circuit 12, that is, the test data TOO to TD3 becomes "0001", and the test data TOO to TD3 is manually input to the test multistage synchronous counter 100. The output 5COUNT becomes "0001". Furthermore, at the next stage, that is, the stage of time t7, the output of the shift register circuit 12, that is, the test data TOO to TD3 becomes "0011", and the test data TDO to TD3 are manually input to the test multistage synchronous counter. The output 5COUNT of 100 becomes "0011".

Note that the test data TDO to TD3 bypass "0010" and proceed to "0011". By outputting such test data, the generation of test data can be significantly reduced. On the other hand, even if the data is thinned out from the original test data in this way, the continuity test of the entire circuit cannot be performed, considering the circuit configuration of the multi-stage synchronous counter 3 shown in Fig. 3. Therefore, there are no problems with the comprehensive exam.

The same applies to the following test data.

FIGS. 5(a) to 5(e) show that when the multistage synchronous counter 3 performs a carry-out and outputs the carry-out signal SCO (FIG. 5(d)), the initial value setting circuit 41 responds to the carry-out signal SCO. A case is shown in which the reset signal RBSBT is output to the shift register circuit 12. When this reset signal RESET is input manually, the shift register circuit 12
Again, set the test data TOO to TD3 to the initial value “00”.
00'' and in response to the shift clock 5CLK,
Generates test data. Therefore, the above test can be repeated.

In the above embodiment, the multi-stage synchronous counter 3 of only 4 bits was described as an example to simplify the explanation, but the present invention
It is clear that the greater the number of bits in the multi-stage synchronous counter 3, the greater the effect.

FIG. 6 shows a more detailed circuit diagram of FIG. 2.

In FIG. 6, the clock load signal generation circuit 11 of FIG. 2 is replaced by a T-type flip-flop 110 with an enable terminal.
The initial value setting circuit 41 is realized by an AND gate 410, and the shift register circuit 1
2 is realized by four shift registers connected in series as shown in FIG.

The truth table of the flip-flop shown at J- in FIG. 7 is shown in FIG. This truth table itself is well known. The test multi-stage synchronous counter 100 is shown in FIG. Further, FIG. 9 shows the operation timing of the shift register shown in FIG. 7.

FIG. 10 shows an operation timing diagram of the multi-stage synchronous counter testing apparatus shown in FIG. 6.

Since the T-type flip-flop 110 is used, the load signal 5LOA[l and the shift clock 5CLK are output with a phase difference of 180°. Test data TDO
~TD3 is output in the form shown in Table 1, and its tanning is as shown in the figure. The test data TOO~TD
Each counter output SCO~S of the multi-stage synchronous counter 3 in the test multi-stage synchronous counter 100 according to 3.
C3 (overall Te5COuNT) is shown in Figure C3. When the carryout signal SCO is output, the reset signal RBSII! is output from AND game) 1410. T is output to the shift register 120, and the test is performed again from the initial value.

The circuits shown in FIGS. 6 and 7 are also existing simple circuits, and it is clear that the multi-stage synchronous counter testing apparatus of the present invention can be realized with a simple circuit configuration.

In the above embodiments, the reset circuit 4 or the AND
Obviously, gate 410 is not needed for a one-time test.

In the above embodiment, the test data generation circuit 1 of FIG. 1 generates a clock signal 5CL which is half of the clock CLK.
Although we have described the case where the multistage synchronous counter 3 also operates with a clock divided by 1/2 of the normal clock CLK, the test data generation circuit 1 operates with the clock CLK.
Since the test data in Table 1 can be output at the same timing as LK, the operation of the multi-stage synchronous counter 3 can also be tested using the actual clock CLK before frequency division.

〔Effect of the invention〕

As described above, the multi-stage synchronous counter testing device of the present invention has a test data generation circuit that outputs test data in which the number of valid binary data bits increases sequentially in response to the application of a clock. and a selection circuit that selectively applies test data from the test data generation circuit as data input to the multistage synchronous counter for testing when in the test mode. This has the effect of enabling rapid and comprehensive testing to be conducted effectively.

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of a test device for a multi-stage synchronous counter of the present invention, Fig. 2 is a block diagram of a test device for a multi-stage synchronous counter according to an embodiment of the present invention, and Fig. 3 is a multi-stage synchronous test equipment for testing of Fig. 2. 4(a) to (f) and 5(a) to (e) are operational timing diagrams of the circuits in FIG. 2 and 3. FIG. 6 is the circuit diagram of the circuit in FIG. More detailed circuit diagrams, Figure 7 is a circuit diagram of the shift register in Figure 6, Figure 8 is a truth diagram showing the operation of the flip-flop at J- in Figure 7, Figure 9 is the shift register in Figure 7. FIG. 10 is an operation timing diagram of the multi-stage synchronous counter testing device shown in FIG. 6; FIG. 11 is a circuit diagram of a conventional multi-stage synchronous counter. (Explanation of symbols) 1... Test data generation circuit, 2... Selection circuit, 3... Multi-stage synchronous counter, 4... Reset circuit, 11... Clock load signal generation circuit, 12...・・・
Shift register circuit, 41... Initial value setting circuit, 100... Multi-stage synchronous counter for testing.

Claims (1)

[Claims] 1. In a multi-stage synchronous counter testing device for testing a state transition type multi-stage synchronous counter, a clock (CL
A test data generation circuit (1) that outputs test data in which the number of valid binary data bits increases sequentially in response to the application of K); A testing device for a multi-stage synchronous counter, comprising a selection circuit (2) for selectively applying test data as data input to the multi-stage synchronous counter for testing (100). 2. The carrier-out signal (SC) of the multi-stage synchronous counter
2. The multi-stage synchronous counter testing device according to claim 1, further comprising a reset circuit (4) for detecting the test data generation circuit and resetting the test data generation by the test data generation circuit.