JPH02242353A - Address arithmetic circuit - Google Patents

Abstract

PURPOSE:To arbitrarily set the number of words of a cyclically addressing memory by providing a first to a third registers 35, a comparator, and an adder 33. CONSTITUTION:For example, the value of a VP register 32a is updated by +1 each with a +1 adder 33a, and the incremented value is compared with the set value of a VPM register 35a by a pointer value comparator 36a. When they coincide with each other, the VP register 32a is reset, the operation of starting the newly updating by +1 each is repeated. The output updated by +1 each of the VP register 32a is added to the output of a Y register 31a by an address adder 34a, and the addition result is outputted as the effective address, and a memory 37a is accessed by this address. The memory 37a is addressed in such a manner to enable the memory 37a to hold data independently of the number of words of data. Thus, the number of words of the cyclically addressed memory 37a is arbitrarily set.

Description

[Detailed Description of the Invention] [Summary] An address calculation circuit that has an addressing method that can arbitrarily set the number of words of the memory to be addressed in a circular manner, regarding a circuit that calculates the effective address of a memory built in a digital signal processor. The output side is fed back to the input side via a first register that holds the index of the storage part of the memory and a first adder, and the first adder returns the memory by +1. a second register that updates the address pointer value of the register; a second adder that adds the output of the first register and the output of the second register and outputs the result as an effective address of the memory; The third register is configured to set an arbitrary number of words for address shifting, and a comparator is configured to compare the set value of the third register with the output of the second register.

[Industrial application field]

The present invention relates to a circuit for calculating an effective address of a memory included in a digital signal processing processor.

For example, when updating 19 taps for calculating filters used in transmission equipment using a digital signal processing processor, instead of sequentially shifting the data, use an index register and increase the address by +1 by I/1. However, in this case, an address arithmetic circuit with an addressing method to effectively use the limited memory capacity is required.

[Conventional technology]

FIG. 3 is a diagram illustrating the configuration of a digital signal processing processor, and FIG. 4 is a diagram illustrating a conventional example of an address calculation section.

The digital signal processor 6 shown in FIG. 3 includes a sequence control section 1, a decoder section 2, an address calculation section 3, a calculation section 4, and an input/output interface section 5.

The above-mentioned sequence control unit 1 is a program counter that controls the program sequence.

Program memory 6 is comprised of an instruction register, etc.

The decoder unit 2 is equipped with a decoder and a preview decoder that decodes the next code of the code currently being decoded, and controls the address calculation of a writable memory (RAM) prior to executing an instruction, and decodes the number of cycles of an instruction. The address calculation section 3 also controls data transfer and calculation.
, a writable memory (RAM) for storing data, etc., and calculates the address of the data storage memory (RAM) and the address when used as table data of a part of the program memory, and the calculation unit 4 is equipped with 16-bit registers A and B, a multiplier, a temporary register, an arithmetic unit ALU, a 26-bit length accumulator, etc., and performs arithmetic processing. It is equipped with an output control section, and a digital signal processing processor forms a part that receives and receives data in parallel with the outside.

FIG. 4 shows a conventional example of a part of the effective address calculation section of the address calculation section 3 described above, including a Y register 31a which is an index register, a P register 32a which is a 4-bit virtual shift pointer register, and a +1 Adder 33a, address adder 34a, memory (RA
M) 37a.

Note that the Y register 31a stores an index indicating the storage location of data, the VP register 32a increases the virtual data location by +1 and cycles through 16 words, and the +1 adder 33a The combination of the Y register 31a and the Y register 31a is updated by +1, and the address adder 34a outputs the output of the Y register 31a and the VP.
The output of the register 32a is added to output the effective address (2), and the memory (RAM) 37a writes/reads data based on the effective address (2) from the address adder 34a.

For example, when updating taps when calculating filters used in transmission equipment, etc., the Y register 31a, which is an index register, does not shift data sequentially.
Calculations may be performed by incrementing the address by 1 using .

At this time, the address is sequentially increased and the row (and the capacity of the memory (RAM) 37a having a limited capacity is insufficient) is used, so the VP register 32a which is a 4-bit virtual shift pointer register is used. The output is added to the output of the Y register 31a by an address adder 34a to calculate an effective address (2).

As a result, 16 words (
4 bits), the address returns to the first address of the Y register 31a, and addressing can be performed using v&circle.

(Problem to be Solved by the Invention) As described above, 16 words (4 bits) are calculated from the value of the Y register 31a using the 4-bit VP register 32a.
When performing circular addressing at 1
There was a problem that it could not hold more than 6 words of data, and even if the memory (RAM) had the capacity to hold more than 16 words of data, it could not be used effectively. .

SUMMARY OF THE INVENTION An object of the present invention is to provide an address arithmetic circuit having an addressing method that can arbitrarily set the number of words of a memory to be addressed in i-rings.

[Means to solve the problem]

FIG. 1 shows a diagram illustrating the principle of the address calculation section of the present invention.

The address calculation section 30 in the present invention shown in FIG.
an 8-bit second register 32,
8-bit third register 35, comparator 36, and first
The first register 31, the first adder 33, and the second adder 34 are provided.
The adder 34 performs the same operation as explained in FIG. 4, and the second register 32 mentioned above is an 8-bit register that updates and circulates the memory pointer by +1. The third register 35 is an 8-bit register that arbitrarily sets and holds the circulation range of memory addresses, and the comparison Li 36 compares the output value of the second register 32 with the output value of the third register. 35 settings, and if they match, the second
The device outputs a signal for resetting the register 32 of the device, and is a means for solving this problem by having such means and calculating the effective address of the memory.

[For production]

An arbitrary number of words for circular addressing is set in the third register 35, and the virtual shift pointer from the second register 32 is compared with the set value by the comparator 36, and when they match, the second register 35 is set. By resetting 32 and performing addressing by circulating an arbitrary number of words set in the third register 35, it is no longer limited to the number of words of data.

〔Example〕

The gist of the present invention will be specifically explained below with reference to an embodiment shown in FIG.

FIG. 2 is a diagram illustrating an embodiment of the address calculation section of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

The address arithmetic unit 30a of the present invention shown in FIG. 2 serves as the first register 31 shown in FIG.
VP register 32a1 as the register 32, VPM register 35a as the third register 35, first adder 3
3, a +1 adder 33a, a second adder 34, an address adder 34a, a comparator 36, a pointer value comparator 36a, and a memory (RAM) 37a.
This is an example configured with the following.

The basic function of the address calculation section 30a of this embodiment is the same as that explained in FIG. 4, and it is a component of the digital signal processing processor 6 explained in FIG. ing.

The VP register 32a of this embodiment is an 8-bit (256 word) virtual shift pointer register, and
Similarly, the PM register 35a is 8 bits (256 words).
The addressing range can be arbitrarily set using the virtual shift pointer MAX, which forms the register.

In this embodiment, the value of the VP register 32a is increased by +1 to the adder 33.
Update by +1 at ■P register 32a at that time.
The value is compared with the set value of the VPM register 35a by a pointer value comparator 36a.

If the output ■ of the pointer value comparator 36a indicates a mismatch, the VP register 32a continues updating ■ by +1, and when the output ■ of the pointer value comparator 36a indicates a match, the VP register 32a is reset. and newly +
The operation of starting update ω one by one is repeated.

On the other hand, the updated output of the P register 32a by +1 is the output of the Y register 31a and the address adder 34a.
is added and output as an effective address (2), and the memory (RAM) 37a is accessed using this effective address (2).

By addressing the memory (RAM) 37a as described above, the memory (RAM) 37a can hold data regardless of the number of words of the data.

〔Effect of the invention〕

According to the present invention as described above, it is possible to provide an address arithmetic circuit having an addressing method in which the number of words of a memory to be addressed in a circular manner can be arbitrarily set.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the address calculation section of the present invention, FIG. 2 is a diagram explaining an embodiment of the address calculation section of the invention, and FIG. 3 is a diagram explaining the configuration of a digital signal processing processor. FIG. 4 is a diagram illustrating a conventional example of an address calculation section. In the figure, 1 is a sequence control section, 2 is a decoder section, 3.30
．． 30a is an address calculation unit, 4 is a calculation unit, 5 is a human output interface unit, 6 is a digital signal processing processor, 31 is a first register, 31a is a Y register, 32
is the second register, 32a is the VP register, 33 is the first adder, 33a is the +1 adder, 34 is the second adder, 34a is the address adder, 35 is the third register, 35
a is a VPM register, 36 is a comparator, 36a is a pointer value comparator, and 37a is a memory (RAM). FIG. 1 is a diagram illustrating the principle of the address calculation section of the present invention.

Claims (1)

[Claims] The output side is fed back to the input side via a first register (31) that holds an index of a storage part of a memory built into the digital signal processor and a first adder (33). , a second register (32) that updates the address pointer value of the memory by +1 in the first adder (33);
), a second adder (34) that adds the output of the first register (31) and the output of the second register (32) and outputs the result as an effective address of the memory; A third register (35) sets the arbitrary number of words to be rotated and shifted in the register (32).
), and a comparator (36) that compares the set value of the third register (35) and the output of the second register (32), and the output of the comparator (36) is a match signal. In the case of
An address arithmetic circuit characterized in that addressing is performed by resetting a register (32) of the third register (32) and circulating an arbitrary number of words set in the third register (35).