JPH02242230A - Liquid crystal display device - Google Patents
Liquid crystal display deviceInfo
- Publication number
- JPH02242230A JPH02242230A JP1062048A JP6204889A JPH02242230A JP H02242230 A JPH02242230 A JP H02242230A JP 1062048 A JP1062048 A JP 1062048A JP 6204889 A JP6204889 A JP 6204889A JP H02242230 A JPH02242230 A JP H02242230A
- Authority
- JP
- Japan
- Prior art keywords
- scanning circuit
- liquid crystal
- horizontal scanning
- pseudo
- display device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 239000010409 thin film Substances 0.000 claims abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 16
- 239000010408 film Substances 0.000 abstract description 15
- 239000010453 quartz Substances 0.000 abstract description 15
- 239000011521 glass Substances 0.000 abstract description 12
- 239000000853 adhesive Substances 0.000 description 9
- 230000001070 adhesive effect Effects 0.000 description 9
- 238000000034 method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、ラップトツブパソコン等の表示装置として用
いる液晶表示装置に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a liquid crystal display device used as a display device for a laptop computer or the like.
（従来の技術）
近年、液晶を用いた表示装置（液晶表示装置という）は
軽量、薄形、低消費電力あるいは低価格等の特徴を有し
て、従来のＣＲＴ表示装置に代わって、小型、軽量が要
求されるラップトツブパソコンあるいは可搬型測定器等
の表示装置等に用いられる傾向にある。(Prior Art) In recent years, display devices using liquid crystals (referred to as liquid crystal display devices) have characteristics such as being lightweight, thin, low power consumption, and low cost, and have been used as small-sized and They tend to be used for display devices such as laptop computers or portable measuring instruments that require light weight.
第３図はそのような従来の液晶表示装置の平面構成を示
す図、第４図は第３図のＡ−Ｂ線断面図。FIG. 3 is a diagram showing the planar configuration of such a conventional liquid crystal display device, and FIG. 4 is a sectional view taken along the line AB in FIG. 3.
第５図は第３図の画素部の一部を示す断面図である。FIG. 5 is a sectional view showing a part of the pixel section of FIG. 3. FIG.
これらの図において、４０は石英基板、４１はゲート酸
化膜、４２はゲート電極、４３はゲート信号線、４４は
ソース領域、４５はドレイン領域、４６は層間絶縁層、
４７はソース・コンタクト、４８はドレイン・コンタク
ト、４９はソース信号線、５０はポンディングパッド、
５１はコンタクト膜、５２は画素電極、５３は保護膜、
５４は液晶配向膜、５５は共通電極、５６は上面ガラス
板、５７は液晶、５８は接着剤、５９は画素部、６０は
垂直走査回路、６１は水平走査回路である。In these figures, 40 is a quartz substrate, 41 is a gate oxide film, 42 is a gate electrode, 43 is a gate signal line, 44 is a source region, 45 is a drain region, 46 is an interlayer insulating layer,
47 is a source contact, 48 is a drain contact, 49 is a source signal line, 50 is a bonding pad,
51 is a contact film, 52 is a pixel electrode, 53 is a protective film,
54 is a liquid crystal alignment film, 55 is a common electrode, 56 is a top glass plate, 57 is a liquid crystal, 58 is an adhesive, 59 is a pixel portion, 60 is a vertical scanning circuit, and 61 is a horizontal scanning circuit.
まず、第５図を参照して、石英基板４ｏ上に厚さ約０．
２μｍ程度のポリシリコン層を形成し、フォトレジスト
をマスクにしてドライエツチングによりトランジスタ領
域を形成した後、チャネル領域を形成するために熱酸化
により厚さ０．１μｍ程度の酸化シリコン層を形成後、
その上に厚さ０．３μｍ程度のポリシリコン層を形成し
、フォトレジストをマスクにドライエツチングして、上
記ポリシリコンによるゲート電極４２と第３図に示すゲ
ート信号線４３とを形成する。その後、フォトレジスト
をマスクにしてウェットエツチングにより、チャネル領
域上にゲート酸化膜４１を形成させる。First, referring to FIG. 5, a quartz substrate 4o is coated with a thickness of approximately 0.
After forming a polysilicon layer of about 2 μm, forming a transistor region by dry etching using a photoresist as a mask, and forming a silicon oxide layer of about 0.1 μm thick by thermal oxidation to form a channel region,
A polysilicon layer having a thickness of about 0.3 μm is formed thereon, and dry etching is performed using a photoresist as a mask to form a gate electrode 42 made of the polysilicon and a gate signal line 43 shown in FIG. 3. Thereafter, a gate oxide film 41 is formed on the channel region by wet etching using a photoresist as a mask.
次に、フォトレジストをマスクにしてトランジスタ領域
上にＰｌまたはＡｓ”をイオン注入し、ｎ領域であるソ
ース領域４４とドレイン領域４５とを形成する。その後
、ソースコンタクト用の窓とドレインコンタクト用の窓
を有する層間絶縁層４６を厚さ０．８７７１１１程度の
Ｎ Ｓ Ｇ （Ｎｏｎ−ｄｏｐｅｄ ５ｉｌｉｃａｔｓ
Ｇｌａｓｓ）により形成し、厚さ１μ−程度のＡＱ−
３Ｌ合金膜によるソース・コンタクト４７とドレイン・
コンタクト４８とを形成すると同時に、第３図のソース
信号線４９とポンディングパッド５０とを形成する。さ
らに、厚さ０．３μｍ程度のＣｒ等によるコンタクト膜
５１を形成した後、厚さ０．２μｍ程度の酸化インジウ
ム錫膜等の画素電極５２を形成した後、厚さ０．３μ慣
程度の窒化シリコン膜による保護膜５３を形成する。Next, using a photoresist as a mask, Pl or As'' is ion-implanted onto the transistor region to form a source region 44 and a drain region 45, which are n-type regions.After that, a window for a source contact and a window for a drain contact are formed. The interlayer insulating layer 46 having a window is made of NSG (Non-doped 5 illicats) with a thickness of about 0.877111.
Glass) and has a thickness of about 1μ.
Source contact 47 and drain contact made of 3L alloy film
At the same time as the contact 48 is formed, the source signal line 49 and the bonding pad 50 shown in FIG. 3 are formed. Furthermore, after forming a contact film 51 made of Cr or the like with a thickness of about 0.3 μm, a pixel electrode 52 made of indium tin oxide or the like with a thickness of about 0.2 μm is formed, and then a nitride film with a thickness of about 0.3 μm is formed. A protective film 53 made of a silicon film is formed.
このようにして、第３図に示したような画素部５９が形
成されると同時に、上記のＣＭＯＳプロセスにより垂直
走査回路６０と水平走査回路６１が形成される。In this way, the pixel section 59 as shown in FIG. 3 is formed, and at the same time, the vertical scanning circuit 60 and the horizontal scanning circuit 61 are formed by the above-described CMOS process.
その後、第４図のように液晶工程において、画素部５９
上に液晶配向膜５４を形成させ、ラビングして液晶５７
を注入し、石英基板４０と対向するように共通電極５５
を形成した上面ガラス板５６を接着剤５８を用いて接着
することにより、液晶５７を封止して液晶表示装置が形
成される。Thereafter, as shown in FIG. 4, in the liquid crystal process, the pixel portion 59
A liquid crystal alignment film 54 is formed on the liquid crystal 57 by rubbing.
A common electrode 55 is implanted to face the quartz substrate 40.
The liquid crystal 57 is sealed by bonding the upper glass plate 56 formed with an adhesive 58 using an adhesive 58 to form a liquid crystal display device.
この時、画素部５９と垂直走査回路６０と水平走査回路
６１とは厚さが２μｍ程度に、また、上面ガラス板５６
と石英基板４０との間隔は４μｍ程度となっている。ま
た、接着剤５８の少なくとも一部は垂直走査回路６０お
よび水平走査回路６１の上に第４図のように形成される
。At this time, the pixel portion 59, the vertical scanning circuit 60, and the horizontal scanning circuit 61 have a thickness of about 2 μm, and the top glass plate 56
The distance between the quartz substrate 40 and the quartz substrate 40 is about 4 μm. Further, at least a portion of the adhesive 58 is formed on the vertical scanning circuit 60 and the horizontal scanning circuit 61 as shown in FIG.
（発明が解決しようとする課題）
しかしながら、上記の構成では１石英基板４０上に、接
着剤５８と垂直走査回路６０および水平走査回路６１上
に設けられた接着剤５８とが形成されているため、上面
ガラス板５６と石英基板４０との間隔が位置によって違
い、最高２μ田程度の差がある。(Problem to be Solved by the Invention) However, in the above configuration, the adhesive 58 and the adhesive 58 provided on the vertical scanning circuit 60 and the horizontal scanning circuit 61 are formed on the quartz substrate 40. The distance between the top glass plate 56 and the quartz substrate 40 varies depending on the position, and there is a maximum difference of about 2 μm.
そのため、封止した液晶の厚さが不均一で、したがって
、液晶の電界制御特性が位置によって均一ではなく、そ
のため、不均一な画素表示あるいは低コントラスト表示
等の表示品質を劣化させている。Therefore, the thickness of the sealed liquid crystal is non-uniform, and the electric field control characteristics of the liquid crystal are therefore non-uniform depending on the position, resulting in deterioration of display quality such as non-uniform pixel display or low contrast display.
本発明は上述に鑑み、封止した液晶の厚さの不均一性を
排除して、高品質で信頼性の高い液晶表示装置の提供を
目的とする。In view of the above, it is an object of the present invention to provide a high quality and highly reliable liquid crystal display device by eliminating non-uniformity in the thickness of sealed liquid crystal.
（課題を解決するための手段）
本発明は上記の目的を、基板上に薄膜トランジスタを有
する画素複数により形成した画素部およびその側辺に直
角的に配設され、上記画素を走査し駆動する垂直走査回
路および水平走査回路を有する液晶表示装置において、
上記画素部を介在させて上記垂直走査回路および水平走
査回路にそれぞれ対向させて形成した。それら垂直走査
回路および水平走査回路に近似の疑似垂直走査回路およ
び疑似水平走査回路を設けて達成する。(Means for Solving the Problems) The present invention has achieved the above object by providing a pixel section formed by a plurality of pixels having thin film transistors on a substrate, and a vertical In a liquid crystal display device having a scanning circuit and a horizontal scanning circuit,
They were formed to face the vertical scanning circuit and the horizontal scanning circuit, respectively, with the pixel section interposed therebetween. This is achieved by providing approximate pseudo vertical scanning circuits and pseudo horizontal scanning circuits to these vertical scanning circuits and horizontal scanning circuits.
（作 用）
上記の手段により、基板上に垂直走査回路および水平走
査回路の有無によって不均一であった上面ガラス板と石
英基板との間隔が、疑似垂直走査回路と疑似水平走査回
路を形成したので均一化され、したがって、封止された
液晶は均一で、電界制御が同じになって表示品質が画素
部全域にわたって良好になる。(Function) By the above means, the gap between the top glass plate and the quartz substrate, which was uneven due to the presence or absence of vertical scanning circuits and horizontal scanning circuits on the substrate, was changed to form a pseudo vertical scanning circuit and a pseudo horizontal scanning circuit. Therefore, the sealed liquid crystal is uniform and the electric field control is the same, resulting in good display quality over the entire pixel area.
（実施例）
以下、本発明の一実施例の液晶表示装置を図面により説
明する。(Example) Hereinafter, a liquid crystal display device according to an example of the present invention will be described with reference to the drawings.
第１図は液晶表示装置の構成図、第２図はそのＥ−Ｆ線
断面図であり、これら両図において、１は石英基板、２
はゲート信号線、３はソース信号線、４はポンディング
パッド、５は液晶配向膜、６は共通電極、７は上面ガラ
ス板、８は液晶、９は接着剤、 １０は画素部、１１は
垂直走査回路、■２は水平走査回路、１３は疑似垂直走
査回路、１４は疑似水平走査回路である。Fig. 1 is a configuration diagram of a liquid crystal display device, and Fig. 2 is a cross-sectional view taken along the line E-F. In both figures, 1 is a quartz substrate, 2
1 is a gate signal line, 3 is a source signal line, 4 is a bonding pad, 5 is a liquid crystal alignment film, 6 is a common electrode, 7 is a top glass plate, 8 is a liquid crystal, 9 is an adhesive, 10 is a pixel part, 11 is a 2 is a vertical scanning circuit; 2 is a horizontal scanning circuit; 13 is a pseudo-vertical scanning circuit; and 14 is a pseudo-horizontal scanning circuit.
まず、第１図を参照して１石英基板１上にＣＭＯＳプロ
セスによってゲート信号線２とソース信号線３およびポ
ンディングパッド４を形成し、薄膜トランジスタを有す
る画素部１０と垂直走査回路１１および水平走査回路１
２を形成する。First, referring to FIG. 1, a gate signal line 2, a source signal line 3, and a bonding pad 4 are formed on a quartz substrate 1 by a CMOS process, and a pixel section 10 having a thin film transistor, a vertical scanning circuit 11, and a horizontal scanning circuit are formed. circuit 1
form 2.
この際、同時に画素部１０を介在させて垂直走査回路１
１および水平走査回路１２にそれぞれ対向する、それら
垂直走査回路１１および水平走査回路１２に近似の疑似
垂直走査回路１３および疑似水平走査回路１４を形成す
る。At this time, at the same time, the vertical scanning circuit 1 is
A pseudo vertical scanning circuit 13 and a pseudo horizontal scanning circuit 14, which are similar to the vertical scanning circuit 11 and the horizontal scanning circuit 12, are formed opposite to the vertical scanning circuit 11 and the horizontal scanning circuit 12, respectively.
その後、液晶工程によって第２図に示す画素部１０上に
ポリイミド系樹脂による液晶配向膜５を形成し、ラビン
グを行なった後液晶８を注入し１石英基板１と対向させ
て共通電極６が形成された液晶封止用の上面ガラス板７
を接着剤９によって接着し、液晶を封止することによっ
て本発明の一実施例の液晶表示装置が形成される。Thereafter, a liquid crystal alignment film 5 made of polyimide resin is formed on the pixel portion 10 shown in FIG. 2 by a liquid crystal process, and after rubbing, a liquid crystal 8 is injected and a common electrode 6 is formed facing the quartz substrate 1. Top glass plate 7 for sealing liquid crystal
A liquid crystal display device according to an embodiment of the present invention is formed by bonding them with an adhesive 9 and sealing the liquid crystal.
以上のように形成する液晶表示装置は、従来のプロセス
の変更を要せず、ただマスクの変更だけで形成すること
が可能である。なお、上記の実施例では封止液晶の均一
化のプロセスを簡易にするため、マスクの変更により付
加した疑似垂直走査回路あるいは疑似水平走査回路を設
けたが、それに代えて新たなプロセスにより封止液晶を
均一化する垂直走査回路、水平走査回路に近似の島状体
を設けてもよいことは当然である。The liquid crystal display device formed as described above does not require any change in conventional processes, and can be formed simply by changing the mask. In the above embodiment, in order to simplify the process of uniformizing the sealed liquid crystal, a pseudo vertical scanning circuit or a pseudo horizontal scanning circuit was added by changing the mask. It goes without saying that approximate island-shaped bodies may be provided in the vertical scanning circuit and horizontal scanning circuit for making the liquid crystal uniform.
（発明の効果）
以上、説明して明らかなように１本発明は、液晶表示装
置において、垂直走査回路および水平走査回路による上
面ガラス板と石英基板との間隔の位置による不均一さを
、疑似の垂直走査回路および水平走査回路を設けて解決
したものであり、したがって、封止されている液晶は均
一で、そのため、画素部の電界制御性に不均一性がない
から、全表示画面上で表示精度が高い品質良好な表示が
得られる効果があり、液晶の平面性、軽量性、経済性等
とあいまって、可搬型装置の表示装置等の利用に貢献す
る。(Effects of the Invention) As is clear from the above description, one aspect of the present invention is to simulate non-uniformity due to the position of the gap between the top glass plate and the quartz substrate caused by the vertical scanning circuit and the horizontal scanning circuit in a liquid crystal display device. This problem was solved by providing a vertical scanning circuit and a horizontal scanning circuit. Therefore, the sealed liquid crystal is uniform, and therefore there is no non-uniformity in the electric field controllability of the pixel area, so that it can be displayed on the entire display screen. It has the effect of providing a high-quality display with high display accuracy, and together with the flatness, light weight, and economic efficiency of liquid crystals, it contributes to the use of display devices in portable devices.
第１図は液晶表示装置の構成図、第２図は第１図のＥ−
Ｆ線断面図、第３図は従来の液晶表示装置の平面構成を
示す図、第４図は第３図のＡ−Ｂ線断面図、第５図は第
３図の画素部の一部を示す断面図である。
１・・・石英基板、 ２・・・ゲート信号線、 ３°゛
°ソ一ス信号線、 ４・・・ポンディングパッド、 ５
・・・液晶配向膜、 ６・・・共通電極、７・・・上面
ガラス板、 ８・・・液晶、 ９・・・接着剤、 １０
・・・画素部、 １１・・・垂直走査回路、１２・・・
水平走査回路、 １３・・・疑似垂直走査回路、 １４
・・・疑似水平走査回路。
特許出願人 松下電子工業株式会社
区
ば）
琺Figure 1 is a configuration diagram of a liquid crystal display device, and Figure 2 is an E- diagram of Figure 1.
3 is a diagram showing the planar configuration of a conventional liquid crystal display device, FIG. 4 is a sectional view taken along line A-B in FIG. 3, and FIG. 5 shows a part of the pixel section in FIG. 3. FIG. DESCRIPTION OF SYMBOLS 1...Quartz substrate, 2...Gate signal line, 3°゛°source signal line, 4...Ponding pad, 5
...Liquid crystal alignment film, 6...Common electrode, 7...Top glass plate, 8...Liquid crystal, 9...Adhesive, 10
... Pixel section, 11... Vertical scanning circuit, 12...
Horizontal scanning circuit, 13...Pseudo vertical scanning circuit, 14
...pseudo horizontal scanning circuit. Patent applicant Matsushita Electronics Co., Ltd.)
Claims (1)
した画素部およびその側辺に直角的に配設され、上記画
素を走査し駆動する垂直走査回路および水平走査回路を
有する液晶表示装置において、上記画素部を介在させて
上記垂直走査回路および水平走査回路にそれぞれ対向さ
せて形成した、それら垂直走査回路および水平走査回路
に近似の疑似垂直走査回路および疑似水平走査回路を有
することを特徴とする液晶表示装置。In a liquid crystal display device having a pixel portion formed by a plurality of pixels having thin film transistors on a substrate, and a vertical scanning circuit and a horizontal scanning circuit disposed perpendicularly to the sides thereof and scanning and driving the pixels, the pixel portion is A liquid crystal display device comprising a pseudo-vertical scanning circuit and a pseudo-horizontal scanning circuit which are interposed and formed to face the vertical scanning circuit and the horizontal scanning circuit, respectively, and which are similar to the vertical scanning circuit and the horizontal scanning circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6204889A JP2816982B2 (en) | 1989-03-16 | 1989-03-16 | Liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6204889A JP2816982B2 (en) | 1989-03-16 | 1989-03-16 | Liquid crystal display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02242230A true JPH02242230A (en) | 1990-09-26 |
| JP2816982B2 JP2816982B2 (en) | 1998-10-27 |
Family
ID=13188885
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6204889A Expired - Lifetime JP2816982B2 (en) | 1989-03-16 | 1989-03-16 | Liquid crystal display |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2816982B2 (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0682811A (en) * | 1992-07-15 | 1994-03-25 | Toshiba Corp | Liquid crystal display device |
| JPH06138488A (en) * | 1992-10-29 | 1994-05-20 | Seiko Epson Corp | Liquid crystal display device |
| EP0603420A1 (en) * | 1992-07-15 | 1994-06-29 | Kabushiki Kaisha Toshiba | Liquid crystal display |
| JPH08220560A (en) * | 1995-02-15 | 1996-08-30 | Semiconductor Energy Lab Co Ltd | Active matrix display device |
| US6115097A (en) * | 1996-05-16 | 2000-09-05 | Semiconductor Energy Laboratory Co., Ltd | Liquid crystal device with light blocking sealing member and light blocking electrode over two interlayer insulating films |
| US6163357A (en) * | 1996-09-26 | 2000-12-19 | Kabushiki Kaisha Toshiba | Liquid crystal display device having the driving circuit disposed in the seal area, with different spacer density in driving circuit area than display area |
| JP2002023196A (en) * | 2001-04-23 | 2002-01-23 | Seiko Epson Corp | Liquid crystal display device |
| US6703643B2 (en) | 1995-02-15 | 2004-03-09 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device with an integrated circuit covered with a sealing material |
| JP2004334214A (en) * | 2003-05-06 | 2004-11-25 | Lg Phillips Lcd Co Ltd | Thin film transistor array substrate and its manufacture method |
| US7053973B1 (en) * | 1996-05-16 | 2006-05-30 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
| KR100550810B1 (en) * | 1996-06-25 | 2006-06-29 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Electronic device having liquid crystal display device |
| US7142273B1 (en) | 1996-06-25 | 2006-11-28 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display panel with a laminating structure containing a semiconductor layer located under the seal |
| US7298447B1 (en) | 1996-06-25 | 2007-11-20 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display panel |
| US7956978B2 (en) | 1995-12-21 | 2011-06-07 | Semiconductor Energy Laboratory Co., Ltd. | Liquid-crystal display device having a particular conductive layer |
| JP2013200573A (en) * | 2013-06-05 | 2013-10-03 | Semiconductor Energy Lab Co Ltd | Liquid crystal display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60166927A (en) * | 1984-02-09 | 1985-08-30 | Seiko Epson Corp | Input method of signal to signal line |
| JPS61177481A (en) * | 1985-02-01 | 1986-08-09 | セイコーインスツルメンツ株式会社 | Sealing construction of liquid crystal display unit |
| JPS62251723A (en) * | 1986-04-25 | 1987-11-02 | Seiko Epson Corp | Liquid crystal panel incorporating driver |
| JPS62252964A (en) * | 1986-04-25 | 1987-11-04 | Seiko Epson Corp | Active matrix substrate housed in driver |
| JPS63218927A (en) * | 1987-03-06 | 1988-09-12 | Matsushita Electronics Corp | Picture display device |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60166927A (en) * | 1984-02-09 | 1985-08-30 | Seiko Epson Corp | Input method of signal to signal line |
| JPS61177481A (en) * | 1985-02-01 | 1986-08-09 | セイコーインスツルメンツ株式会社 | Sealing construction of liquid crystal display unit |
| JPS62251723A (en) * | 1986-04-25 | 1987-11-02 | Seiko Epson Corp | Liquid crystal panel incorporating driver |
| JPS62252964A (en) * | 1986-04-25 | 1987-11-04 | Seiko Epson Corp | Active matrix substrate housed in driver |
| JPS63218927A (en) * | 1987-03-06 | 1988-09-12 | Matsushita Electronics Corp | Picture display device |
Cited By (26)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0603420A1 (en) * | 1992-07-15 | 1994-06-29 | Kabushiki Kaisha Toshiba | Liquid crystal display |
| EP0603420A4 (en) * | 1992-07-15 | 1994-12-21 | Tokyo Shibaura Electric Co | Liquid crystal display. |
| JPH0682811A (en) * | 1992-07-15 | 1994-03-25 | Toshiba Corp | Liquid crystal display device |
| JPH06138488A (en) * | 1992-10-29 | 1994-05-20 | Seiko Epson Corp | Liquid crystal display device |
| US6703643B2 (en) | 1995-02-15 | 2004-03-09 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display device with an integrated circuit covered with a sealing material |
| JPH08220560A (en) * | 1995-02-15 | 1996-08-30 | Semiconductor Energy Lab Co Ltd | Active matrix display device |
| US7924392B2 (en) | 1995-02-15 | 2011-04-12 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display and forming method thereof |
| US7538849B2 (en) | 1995-02-15 | 2009-05-26 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix display and forming method thereof |
| US9316880B2 (en) | 1995-12-21 | 2016-04-19 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device |
| US8194224B2 (en) | 1995-12-21 | 2012-06-05 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device having particular conductive layers |
| US7956978B2 (en) | 1995-12-21 | 2011-06-07 | Semiconductor Energy Laboratory Co., Ltd. | Liquid-crystal display device having a particular conductive layer |
| US8665411B2 (en) | 1995-12-21 | 2014-03-04 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device having particular conductive layer |
| US7053973B1 (en) * | 1996-05-16 | 2006-05-30 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
| US6115097A (en) * | 1996-05-16 | 2000-09-05 | Semiconductor Energy Laboratory Co., Ltd | Liquid crystal device with light blocking sealing member and light blocking electrode over two interlayer insulating films |
| US7417702B2 (en) | 1996-05-16 | 2008-08-26 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
| US7142273B1 (en) | 1996-06-25 | 2006-11-28 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display panel with a laminating structure containing a semiconductor layer located under the seal |
| US7667817B2 (en) | 1996-06-25 | 2010-02-23 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display panel |
| US7298447B1 (en) | 1996-06-25 | 2007-11-20 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display panel |
| KR100550810B1 (en) * | 1996-06-25 | 2006-06-29 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Electronic device having liquid crystal display device |
| US7990514B2 (en) | 1996-06-25 | 2011-08-02 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display panel |
| US8334964B2 (en) | 1996-06-25 | 2012-12-18 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display panel |
| US6163357A (en) * | 1996-09-26 | 2000-12-19 | Kabushiki Kaisha Toshiba | Liquid crystal display device having the driving circuit disposed in the seal area, with different spacer density in driving circuit area than display area |
| JP2002023196A (en) * | 2001-04-23 | 2002-01-23 | Seiko Epson Corp | Liquid crystal display device |
| JP4658514B2 (en) * | 2003-05-06 | 2011-03-23 | エルジー ディスプレイ カンパニー リミテッド | Thin film transistor array substrate and manufacturing method thereof |
| JP2004334214A (en) * | 2003-05-06 | 2004-11-25 | Lg Phillips Lcd Co Ltd | Thin film transistor array substrate and its manufacture method |
| JP2013200573A (en) * | 2013-06-05 | 2013-10-03 | Semiconductor Energy Lab Co Ltd | Liquid crystal display device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2816982B2 (en) | 1998-10-27 |
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