JPH02240963A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02240963A JPH02240963A JP6080489A JP6080489A JPH02240963A JP H02240963 A JPH02240963 A JP H02240963A JP 6080489 A JP6080489 A JP 6080489A JP 6080489 A JP6080489 A JP 6080489A JP H02240963 A JPH02240963 A JP H02240963A
- Authority
- JP
- Japan
- Prior art keywords
- island
- silicon semiconductor
- tapered shape
- oxide film
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 230000005855 radiation Effects 0.000 abstract description 8
- 230000003647 oxidation Effects 0.000 abstract description 6
- 238000007254 oxidation reaction Methods 0.000 abstract description 6
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 230000006866 deterioration Effects 0.000 abstract description 4
- 239000012212 insulator Substances 0.000 abstract 2
- 238000000034 method Methods 0.000 description 11
- 238000007796 conventional method Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 229910005091 Si3N Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
Landscapes
- Recrystallisation Techniques (AREA)
- Local Oxidation Of Silicon (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔(既 要〕
SO■におけるSi島の形成方法に関し、Si島の側壁
が鋭角であると、電極の段差切れや絶縁膜の耐圧低下の
原因となる問題を解決することを目的とし、
5olO3t島を犠牲酸化により側壁がテーパ〔産業上
の利用分野〕
本発明は半導体装置の製造方法、特にSO!(Sili
con On In5ulator)のSi島の形成方
法に係る。耐放射線素子において、厚い素子間分離膜は
放射線損傷が大きく、ソース・ドレイン間リークの発生
の原因になっている。SOtはメサ構造にすることが出
来、厚い素子間分離膜を用いな(でもすむといった利点
がある。従って放射線損傷を小さ(することが可能であ
り、ソース・ドレイン間リークを防ぐことが出来る。[Detailed Description of the Invention] [(Already Required)] To solve the problem of a method for forming Si islands in SO■, where when the side walls of the Si islands have an acute angle, they cause step breakage in the electrodes and a decrease in the withstand voltage of the insulating film. [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, in which the sidewalls of 5olO3t islands are tapered by sacrificial oxidation.
The present invention relates to a method for forming Si islands using a method of forming Si islands (con-on-in-layer). In radiation-resistant devices, thick isolation films are subject to significant radiation damage and cause source-drain leakage. SOt has the advantage that it can be formed into a mesa structure and does not require the use of a thick isolation film between elements. Therefore, radiation damage can be reduced and leakage between the source and drain can be prevented.
第4図に従来の代表的な301におけるSi島の形成方
法を示す。第4図(a)の如く、Si基板1表面にSi
O□やサファイヤによる絶縁11!2を形成した後、全
面にSi層3を形成する。それから、通常のホトリソグ
ラフ法によりレジストマスクなどで選択エツチングする
と、第4図(b)の如きSi島3゛が形成される。FIG. 4 shows a typical conventional method for forming Si islands in 301. As shown in FIG. 4(a), Si is deposited on the surface of the Si substrate 1.
After forming the insulation 11!2 of O□ or sapphire, a Si layer 3 is formed on the entire surface. Then, selective etching is carried out using a resist mask or the like using an ordinary photolithography method to form Si islands 3' as shown in FIG. 4(b).
上記の如くして形成されるSi島の側壁は急岬であるた
め、その後、例えば、第4図(C)の如く、その上にゲ
ート酸化膜4、ゲート5を形成すると、段差が急峻なた
め、ゲート5をエツチングしたときゲートエツチング残
6が生じ、回路が短絡するおそれがある。Since the side wall of the Si island formed as described above has a steep cape, when a gate oxide film 4 and a gate 5 are subsequently formed thereon, for example, as shown in FIG. 4(C), the step becomes steep. Therefore, when the gate 5 is etched, a gate etching residue 6 is generated, which may cause a short circuit in the circuit.
また、第4図(d)に示す如く、Si島3上に下層配線
7を形成後、眉間絶縁膜8、上層配線8を形成する場合
、Si島の段差が鋭いと、眉間絶縁膜8のカバレージ9
が悪(、そのため上層配線8の段差切れ10のおそれが
ある。Further, as shown in FIG. 4(d), when forming the lower layer wiring 7 on the Si island 3 and then forming the glabellar insulating film 8 and the upper layer wiring 8, if the step of the Si island is sharp, the glabellar insulating film 8 will be coverage 9
(Therefore, there is a possibility that the upper layer wiring 8 may be broken 10).
そこで、本発明は、Si島を急激な段差なく、滑らかな
テーパ形状に形成する方法を提供することを目的とする
。Therefore, an object of the present invention is to provide a method for forming Si islands into a smooth tapered shape without sharp steps.
本発明は、上記目的を達成するために、絶縁体基板上に
シリコン半導体層を形成する工程と、該シリコン半導体
層上に選択的に開口部を有するマスクパターンを用いて
該シリコン半導体層を選択酸化し、端部が該開口部周縁
の下部にテーパ形状をもって進入する選択酸化膜を形成
する工程と、該選択酸化膜を選択的にエツチングして側
壁がテーパ形状を有するシリコン半導体島を形成する工
程とを含むことを特徴とする半導体装置の製造方法を提
供する。In order to achieve the above object, the present invention includes a step of forming a silicon semiconductor layer on an insulating substrate, and selecting the silicon semiconductor layer using a mask pattern having selective openings on the silicon semiconductor layer. oxidizing to form a selective oxide film whose end portion tapers into the lower part of the periphery of the opening, and selectively etching the selective oxide film to form a silicon semiconductor island having a tapered sidewall. Provided is a method for manufacturing a semiconductor device characterized by comprising the steps of:
本発明の犠牲酸化法によれば非常に滑らかな側壁形状を
有するSi島が形成される。選択酸化膜の形状は、能動
Si表面に対して対称に形成される為、通常の選択酸化
状態で上記問題が起きないので、これをエツチングした
形状でも段差切れ、エツチング残差等の問題がなくなる
。またSi3N4の厚みなどをコントロールすることに
より連続的な曲線形状を持つSi島を得ることが出来、
ゲート酸化を低温で形成しても部分的に薄くなることは
無くなり(Dah−Bin Kao et al、(I
nternationalElectron Devi
ce Meeting 1985 * 388 ) 、
ゲート酸化膜耐圧の劣化が防げる。According to the sacrificial oxidation method of the present invention, Si islands with very smooth sidewall shapes are formed. Since the shape of the selective oxide film is formed symmetrically with respect to the active Si surface, the above problem does not occur under normal selective oxidation conditions, so even when etched with this film, there are no problems such as step cuts or etching residuals. . In addition, by controlling the thickness of Si3N4, it is possible to obtain Si islands with a continuous curved shape.
Even if the gate oxide is formed at low temperature, local thinning is no longer caused (Dah-Bin Kao et al., (I
international Electron Devi
ce Meeting 1985 * 388),
Deterioration of gate oxide film breakdown voltage can be prevented.
(実施例〕
Si基板11.表面を酸化12したSol基板上にSi
島を形成するためのSt層13を厚さ5000人に形成
する。さらに、33層13の表面を酸化して厚さ100
人の初期酸化膜(図示せず)を形成後、Si3N、膜1
4を厚さ1000人に堆積する。そして、Si、N、膜
14とその下の初期5iO1膜をバターニングして選択
酸化のためのマスクとする。 5iJa膜14と初期酸
化膜との厚みの比は10以上にすると、滑らかな曲線を
持つ側壁の選択酸化膜が得られるのに都合がよい。(Example) Si substrate 11. Si is placed on a Sol substrate whose surface is oxidized 12.
A St layer 13 for forming an island is formed to a thickness of 5000 mm. Furthermore, the surface of the 33 layer 13 is oxidized to a thickness of 100
After forming the initial oxide film (not shown), Si3N, film 1
4 to a thickness of 1000. Then, the Si, N, film 14 and the initial 5iO1 film thereunder are patterned to serve as a mask for selective oxidation. Setting the ratio of the thickness of the 5iJa film 14 to the initial oxide film to be 10 or more is convenient for obtaining a selective oxide film with sidewalls having smooth curves.
〔第1図(a)〕
次に、5iJa膜14をマスクとして5iJi13を選
択酸化する。得られる選択酸化膜15は第1図(b)に
示す如< < 5isNa膜14の下部にテーパ形状を
もって進入し、かつ上下対称である。[FIG. 1(a)] Next, the 5iJi 13 is selectively oxidized using the 5iJa film 14 as a mask. The resulting selective oxide film 15 enters the lower part of the <<5isNa film 14 in a tapered shape, as shown in FIG. 1(b), and is vertically symmetrical.
5isNa膜14を除去し、さらに選択酸化膜15を慣
用手法でSiに対して選択的に除去する。こうして得ら
れるSi島13′は選択酸化1115の形状と相補的で
あり、滑らかな傾斜を有するテーパ形状である。〔第1
図(C)〕
第2図(a)に、このようにして得られたSi島上に配
線層を形成した場合を示す。また、第2図(b)に、第
1図(b)の如く形成された選択酸化膜上に配線層を形
成する場合を示すが、この場合には配線層には断線等の
問題がないことが知られている。一方、前記の如く、第
2図(a)のSi島と第2図(b)の選択酸化膜は実質
的に対称の形状なので、第2図(a)のSi島上に配線
層にも断線等の問題はない。The 5isNa film 14 is removed, and the selective oxide film 15 is further removed selectively with respect to Si using a conventional method. The Si island 13' obtained in this way is complementary to the shape of the selective oxidation 1115, and has a tapered shape with a smooth slope. [1st
FIG. 2(C)] FIG. 2(a) shows a case where a wiring layer is formed on the Si island thus obtained. Further, FIG. 2(b) shows a case where a wiring layer is formed on the selective oxide film formed as shown in FIG. 1(b), but in this case, there is no problem such as disconnection in the wiring layer. It is known. On the other hand, as mentioned above, since the Si island in FIG. 2(a) and the selective oxide film in FIG. 2(b) have substantially symmetrical shapes, there is also a disconnection in the wiring layer on the Si island in FIG. 2(a). There are no other problems.
第3図は第1図で作製したSi&13’を基板とし、そ
の上に厚み200人のゲート酸化膜16、厚み14のア
ルミニウムによるゲート電極17を形成した例を示す。FIG. 3 shows an example in which the Si&13' fabricated in FIG. 1 is used as a substrate, and a gate oxide film 16 with a thickness of 200 mm and a gate electrode 17 made of aluminum with a thickness of 14 mm are formed thereon.
このようなゲート電極17では段差がなだらかなので、
上記の如く断線はなく、またゲート電極17をパターニ
ングしても、第4図に示した如きエツチング残の発生も
ない。Since the step in such a gate electrode 17 is gentle,
There is no disconnection as described above, and even when the gate electrode 17 is patterned, no etching residue is generated as shown in FIG.
なお、従来より、SiNのテーパエツチング法は知られ
ているが、テーパエツチングではテーパ端が鈍角とはい
え鋭く切れるため、その上にゲート酸化膜、ゲート電極
を形成した場合、その鋭い角部で耐圧が低下するという
問題がある。The taper etching method for SiN has been known for a long time, but in taper etching, the taper end is sharply cut, although it has an obtuse angle, so when a gate oxide film and a gate electrode are formed on top of it, the sharp corner will cause damage. There is a problem that the withstand voltage decreases.
従来、Solは耐放射線素子に適しているにもかかわら
ず、前に説明したように、従来技術のSi島の形成方法
では問題があったため、Si基板表面に形成した厚い素
子間分離膜を用い、その際Si基板の不純物濃度を高め
るような不純物を素子分離膜下に入れ、放射線損傷に対
処していた。Conventionally, although Sol is suitable for radiation-resistant elements, as explained earlier, there were problems with the conventional method of forming Si islands, so a thick inter-element isolation film formed on the surface of the Si substrate was used. At that time, impurities that would increase the impurity concentration of the Si substrate were placed under the element isolation film to counter radiation damage.
しかしながら、不純物濃度を限りなく増やすことは基板
−ドレイン間のジャンクション耐圧の低下を招くため実
質上の制約かあ、た。しかし、本発明の方法によれば、
段差切れ、エツチング残、ゲート耐圧の劣化などのない
Sol構造の製作が可能になり、耐放射線素子に実用化
できる。However, increasing the impurity concentration infinitely leads to a decrease in the junction breakdown voltage between the substrate and the drain, so there is a practical restriction. However, according to the method of the present invention,
It becomes possible to manufacture a Sol structure without step cuts, etching residues, and deterioration of gate breakdown voltage, and it can be put to practical use in radiation-resistant elements.
本発明によれば、501構造のSi島の側壁を滑らかな
テーパ形状に形成することが可能になり、その結果、段
差切れ、エツチング残差ゲート耐圧の劣化がないメサ型
構造のトランジ、スターを作ることができ、放射線損傷
によるソース・ドレイン間リークを抑えることができる
。According to the present invention, it is possible to form the side wall of the Si island of the 501 structure into a smooth tapered shape, and as a result, it is possible to form a transistor or star with a mesa structure without step breakage or deterioration of etching residual gate withstand voltage. leakage between the source and drain due to radiation damage can be suppressed.
第1〜3図は実施例の工程を説明する図、第4図は従来
法を説明する図である。
11・・・Si基板、 12−・・Si0g絶縁
膜、13・・・5iJi、 13′・・・Si
島、14・・・Si、N、膜、 15・・・選択
酸化膜、16・・・ゲート酸化膜、 17・・・ゲー
ト電極。
(a)
(a)
(b)
(b)
與2図
13″
実施例
第1 図
63図1 to 3 are diagrams for explaining the steps of the embodiment, and FIG. 4 is a diagram for explaining the conventional method. 11...Si substrate, 12-...Si0g insulating film, 13...5iJi, 13'...Si
Island, 14...Si, N, film, 15...Selective oxide film, 16...Gate oxide film, 17...Gate electrode. (a) (a) (b) (b) Figure 2 13'' Example 1 Figure 63
Claims (1)
、該シリコン半導体層上に選択的に開口部を有するマス
クパターンを用いて該シリコン半導体層を選択酸化し、
端部が該開口部周縁の下部にテーパ形状をもって進入す
る選択酸化膜を形成する工程と、該選択酸化膜を選択的
にエッチングして側壁がテーパ形状を有するシリコン半
導体島を形成する工程とを含むことを特徴とする半導体
装置の製造方法。1. Forming a silicon semiconductor layer on an insulating substrate, selectively oxidizing the silicon semiconductor layer using a mask pattern having selective openings on the silicon semiconductor layer,
A step of forming a selective oxide film whose end portion tapers into the lower part of the periphery of the opening, and a step of selectively etching the selective oxide film to form a silicon semiconductor island having a tapered side wall. A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6080489A JPH02240963A (en) | 1989-03-15 | 1989-03-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6080489A JPH02240963A (en) | 1989-03-15 | 1989-03-15 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02240963A true JPH02240963A (en) | 1990-09-25 |
Family
ID=13152888
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6080489A Pending JPH02240963A (en) | 1989-03-15 | 1989-03-15 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02240963A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014078590A (en) * | 2012-10-10 | 2014-05-01 | Tokyo Electron Ltd | Semiconductor element manufacturing method and semiconductor element |
-
1989
- 1989-03-15 JP JP6080489A patent/JPH02240963A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014078590A (en) * | 2012-10-10 | 2014-05-01 | Tokyo Electron Ltd | Semiconductor element manufacturing method and semiconductor element |
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