JPH02239669A - Soi structure field effect transistor - Google Patents

Abstract

PURPOSE:To improve voltage resistance between a source and a drain, and between the source and a silicon substrate by providing a drain high concentration region in a drain low concentration region or laminating it on the drain low concentration region. CONSTITUTION:A reverse conductivity type source region 104 and a reverse conductivity type drain region 105 are formed at both ends of an insular one conductivity type SOI silicon layer 103 formed on a base oxide film 103 on a silicon substrate 101. The region 105 is formed on a low-concentration drain region 106 and a high-concentration drain region 107, and a channel region 108 is formed between the regions 104 and 105. The region 107 is provided in the region 106 or laminated on the region 105 to form a structure in which the region 107 is not brought into contact with the region 108. Thus, voltage resistance between the source and the drain and between the drain and the substrate can be improved.

Description

[Detailed Description of the Invention] [Summary] Regarding S O J JR field effect transistors, this method is formed on a base oxide film on a silicon substrate for the purpose of improving the withstand voltage between the source and drain and between the drain and the silicon substrate. A source region of an opposite conductivity type and a drain region of an opposite conductivity type are formed at both ends of an island-shaped SOI silicon layer of one conductivity type, and the drain region is formed between a drain low tide region doped with a low concentration of impurities and a drain region doped with impurities. In an SOI field effect transistor, which consists of a highly doped drain region and a channel region between the source region and the drain region, the drain highly doped region is provided within the drain lightly doped region, or the drain region is By stacking the high concentration region on top of the low concentration drain region, we created a structure in which the high concentration drain region does not come into contact with the channel region. [Industrial Application Field] The present invention relates to an SOI structure field effect transistor. In recent years, the performance of display panel driving elements such as plasma displays and power electronics elements such as switching elements has been improved. High voltage output is required. Therefore, SO is applied to the high voltage output part of tC.
I-structure field effect transistors came into use. This SOI field effect transistor must have sufficient high voltage resistance. [Conventional Technology] (Conventional Drama 1) Figure 4 is a diagram showing the first conventional example. In the same figure, 401 is a silicon substrate, 402 is a base oxide film, and 403 is a base oxide film.
is an island-shaped p-type SO formed on the base oxide 111402
■Silicon 15,404 is SOI silicon Iil403
405 is a drain region formed at the end of the SOt silicon layer 403 opposite to the source region 404; 406 is a drain low concentration region;
7 is a drain high concentration region, 408 is a channel region, 40
9 is a gate oxide film, and 410 is a gate electrode. 41l is a wiring insulating film, 4l2 is a source electrode, and 4l3 is a drain electrode.

The reason why the drain region 405 is composed of a low concentration drain region 406 doped with impurities at a low concentration and a high concentration drain region 407 doped with impurities at a high concentration is to increase the withstand voltage between the source and drain. In this conventional example, a base oxide film 40 on a silicon substrate 401 is
The island-shaped p-type SO [silicon layer 403
After a lightly doped drain region 406 doped with n-type impurities is shallowly formed in a predetermined portion of the region by diffusion or ion implantation, a source region 404 and a heavily doped drain region 407 doped with n-type impurities are formed. They are formed simultaneously through a single ion implantation process. When this SOI structure field effect transistor is operated,
Joint failure occurs at the part marked O in Figure 4. this is.
An electric field concentrates on the PN junction formed between the drain high concentration region 407 and the channel region 40B. This is thought to be due to particularly strong electric field concentration at the interface where the drain high concentration region 407 is in contact with the base oxide film 402. For this reason,
This type of SOI field effect transistor has a problem in that its breakdown voltage is reduced.

(Conventional example 2) Figure 5 shows. It is a diagram showing a second conventional example. In the same figure, 501 is a silicon substrate, 502 is a base oxide film, and 503 is a base oxide film.
504 is an island-shaped p-type SOI silicon layer formed on a base oxide film 502, and an n-type source region formed at the end of the SOI silicon layer 503. 505 is an SOt silicon layer 50
3, the drain region is formed at the end opposite to the source region 504, 506 is a lightly doped drain region, 507 is a heavily doped drain region, and 508 is a channel region. 509 is a gate oxide film, 5IO is a gate electrode, 5l1 is a wiring insulating film, 5
12 is the source electrode $1, and 513 is the drain electrode. The drain region 505 is made up of a lightly doped drain region 506 lightly doped with impurities and a heavily doped drain region 507 heavily doped with impurities. This is to increase the breakdown voltage between source and drain. This conventional example is devised to solve the problems of the conventional example 1, and the base oxide film 50 on the silicon substrate 501 is
An island-shaped p-type SOI silicon layer 503 formed on 2
After forming a source region 404 heavily doped with n-type impurities by ion implantation in a predetermined portion, a drain lightly doped fil region 506 lightly doped with n-type impurities is formed.
is formed shallowly by diffusion or ion implantation, and furthermore, n
Drain heavily doped region 50 heavily doped with type impurities
7 by diffusion or ion implantation. It is formed at the same depth as the drain low concentration region 506. however. When this SOI structure field effect transistor is operated. Fifth
Bonding failure occurs at the part marked with a circle in the figure. Although the voltage at which this junction breakdown occurs is higher than in conventional example 1, the higher the impurity concentration in the drain high concentration region 507, the stronger the electric field concentration becomes, and the voltage at which junction breakdown occurs becomes lower. This type of SOI structure field effect transistor. There is a problem in that the breakdown voltage is determined by the impurity concentration of the drain high concentration region 507.

[Problem to be solved by the invention]

In the conventional SOI structure field effect transistor. As in conventional example 1, there is a problem in that the electric field is concentrated at the interface where the high concentration drain region contacts the underlying oxide film, causing junction breakdown and reducing the withstand voltage. Furthermore, as in Conventional Example 2, there is a problem in that the breakdown voltage is determined by the impurity concentration in the high concentration drain region.

The present invention is. Solve the above problems. The purpose of this invention is to provide an SOI structure field effect transistor with improved breakdown voltage between source and drain and between drain and silicon substrate. [Means for Solving the Problems] In order to achieve the above object, the present invention has the following features. An island-shaped SO of one conductivity type formed on a base oxide film on a silicon substrate
A source region of opposite conductivity type and a drain region of opposite conductivity type are formed at both ends of the I silicon layer, and the drain region has a low concentration region doped with impurities and a high tide region doped with high concentration impurities. It consists of
In an SOI field effect transistor in which a channel region is between a source region and a drain region, a high concentration drain region is provided within a low concentration drain region, or a high concentration drain region is stacked on a low concentration drain region. By. [Function] The SOI structure field effect transistor according to the present invention has a structure in which the drain high concentration region does not come into contact with the channel region, so that the 2-channel-drain PN junction is connected to the drain. It exists only between the low concentration region and the channel region. Unlike the conventional method, junction breakdown does not occur between the drain high concentration region and the channel region. Therefore, the breakdown voltage can be increased compared to the conventional example, and unlike the conventional example, the breakdown voltage is not determined by the impurity concentration in the high concentration drain region. [Example] The following example applies the present invention to an n-channel FET. Also. Of course, the present invention can be applied to p-channel FETs by reversing the conductivity type of the impurities.

(Example 1) Figure 1 is a diagram showing the first example. In the same figure, 101 is a silicon substrate, 102 is a base oxide film, and l03 is a base oxide film.
104 is an island-shaped p-type SOI silicon layer formed on the base oxide film 102, and 104 is an n-type source region formed at the end of the SOI silicon layer 103. 105 is the SOI silicon layer 10
The drain region formed at the end opposite to the source region 104 in . 106 is a low concentration drain region. 107 is a drain high concentration region, 10B is a channel region, 109 is a gate oxide film, l10 is a gate electrode, 11l is a wiring insulating film, l
12 is a source electrode, and 113 is a drain electrode.

The silicon substrate 101 is . For example, it is made of p-type single crystal silicon with a specific resistance of 1OΩ1. The base oxide film 102 is . It is a thermal oxide film with a thickness of 1 to 1.5 μm. The SOI silicon layer 103 is made of C on the base oxide film 102.
Polysilicon deposited by the VD method is recrystallized to form a single crystal, and contains p-type impurities such as B at a concentration of 2x10''14.The source region 104 is formed at the edge of the SOI silicon layer 103. It is formed by an implantation method, etc., and uses ^S as an n-type impurity.
Including cm-'. The drain region 105 consists of a low concentration drain region l06 and a high concentration drain region 107.
The drain low concentration region 106 contains 5 X l O "ell-" of As as an n-type impurity. The drain high concentration nodule region 107 contains As as an n-type impurity at 1×10″@1−
3 included.

The channel region 10B is formed of a silicon layer 10 formed with a source region 104 and a low concentration drain region 106.
This is the remaining part of 3. The gate oxide film 109 is a thermal oxide film with a thickness of approximately 2000 nm. The gate electrode 110 is made of n-type polysilicon. The wiring insulating film 111 has a thickness of, for example, 0. 6 1i m
Consists of PSG. The source electrode 112 and the drain electrode 113 are . After depositing N, it is formed by patterning. drain region 1
Drain low concentration tI doped with impurity 05 at low concentration
The reason why it is composed of the drain region 106 and the drain high concentration region 107 doped with impurities at a high concentration is to increase the withstand voltage between the source and drain. In this embodiment, a base oxide film 10 on a silicon substrate 1O1 is used.
Island-shaped p-type SOI silicon 1110 formed on 2
After forming a shallow drain low concentration region i06 lightly doped with an n-type impurity in a predetermined portion of 3 by diffusion or ion implantation. At the same time as the source region 104 heavily doped with n-type impurities, the drain heavily doped region 107 heavily doped with n-type impurities is formed by diffusion or ion implantation. It is formed within the drain low concentration region 106. therefore. In the SOI structure field effect transistor of this embodiment, the channel-drain PN junction exists only between the low concentration drain region 106 and the channel region 108, and the high concentration drain region 107 and the channel region 10B.
No bond failure occurs between the two. Therefore, the withstand voltage can be increased, and the drain high concentration region 107
The breakdown voltage is not determined by the impurity concentration.

(Example 2) Figure 2 shows. It is a diagram showing a second example of actual decoration. In the figure, 201 is a silicon base 1, 202 is a base oxide film, and 203 is a base oxide film.
is an island-shaped p-type SOI silicon layer formed on the base oxide film 202. 204 is an n-type source region formed at the end of the SOI silicon layer 203, and 205 is the SO1 silicon layer 20.
The drain region formed at the end opposite to the source region 204 in No. 3. 206 is a drain low concentration region. 207 is a high concentration drain region. 208 is a channel region, 209 is a gate oxide film, 21O is a gate electrode, and 211 is a wiring insulating film. 2
l2 is the source electrode. 2l3 is the drain electrode. The silicon substrate 201 is made of, for example, p-type single crystal silicon with a specific resistance of 10Ω1. The base oxide film 202 is a thermal oxide film with a thickness of 1 to 1.5 μm. The SOI silicon layer 203 is made of C on the base oxide film 202.
Polysilicon deposited by the VD method is recrystallized to form a single crystal, and contains p-type impurities such as B at a concentration of 2XlO"Cal-". The source area 204 is SO
It is formed at the edge of the I silicon layer 203 by ion implantation or the like. As n-type impurity I
O "cm-" included. The drain region 205 is . It consists of a low concentration drain region 206 and a high concentration drain region 207.

The drain low concentration region 206 is . Contains 5×10 “cr” of As as an n-type impurity.

The drain high concentration region 207 is . Contains A3 as an n-type impurity at I x 10 cm-'. Channel region 208
is the source region 204 and drain lightly doped region 206
The gate oxide film 209, which is the remaining part of the SOI silicon layer 203, is a thermal oxide film with a thickness of approximately 2000 nm. The gate electrode 210 is . Made of n-type polysilicon. The wiring insulating film 2l゜1 is, for example, PS with a thickness of 0.6 μm.
Consists of G. The source electrode 12 1 2 and the drain electrode 213 are formed after N is deposited. Form by buttering. The reason why the drain region 205 is composed of a low concentration drain region 206 doped with impurities at a low concentration and a high concentration drain region 207 doped with impurities at a high concentration is to increase the withstand voltage between the source and drain.

In this example. Base oxide film 20 on silicon substrate 201
An island-shaped p-type SOI silicon layer 203 formed on 2
A source region 204 heavily doped with n-type impurities is formed in a predetermined portion of the region by ion implantation, and a drain lightly doped region 206 lightly doped with n-type impurities is formed shallowly by diffusion or ion implantation. , furthermore, n
Drain high concentration tI region 2 heavily doped with type impurities
07 is formed by epitaxial growth on the drain low concentration region 206.

Therefore, in the SOI side-built field effect transistor of this embodiment, the channel-drain PN junction exists only between the low concentration drain region 206 and the channel region 208; No bonding failure occurs between the two. therefore. The breakdown voltage can be increased, and the breakdown voltage is not determined by the impurity concentration of the drain high concentration region 207.

(Example 3) FIG. 3 is a diagram showing a third embodiment.

In the figure, 30l is a silicon substrate, 302 is a base oxide film, 303 is an island-shaped p-type SOI silicon layer formed on the base oxide film 302, and 304 is an SOI silicon N3 layer.
n-type source region formed at the end of 03. 305 is SOI
A drain region is formed at an end of the silicon layer 303 opposite to the source region 304. 306 is a drain low concentration region,
307 is a drain high concentration region, 308 is a channel region,
309 is a gate oxide film, 3lO is a gate electrode, 311 is a wiring insulating film, and 312 is a source electrode. 3l3 drain i
1M, 314 is a field oxide film.

The silicon substrate 301 is, for example, a silicon substrate with a resistivity of 10Ω.
The mold is made of single crystal silicon.

The base oxide film 302 is a thermal oxide film with a thickness of 1 to 1.5 μm.

The SOI silicon layer 303 is . C on the base oxide film 302
Polysilicon deposited by the VD method is recrystallized to form a single crystal, and B with a concentration of 2XIO "cm-" is used.
Contains p-type impurities such as.

The source nodule region 304 is located at the edge of the SOI silicon layer 303.
It is formed by an ion implantation method and contains A3 as an n-type impurity.

The drain region 305 consists of a low concentration drain region 306 and a high concentration drain region 307.

The drain low concentration region 306 contains 5 x 10 "cm" of As as an n-type impurity.

The drain high tide area 307 is. As is included as an n-type impurity.

The channel region 308 is formed from the SOI silicon layer 30 in which the source region 304 and the drain lightly doped region 306 are formed.
This is the remaining part of 3.

Gate oxidation 11!309 is. It is a thermal oxide film approximately 2,000 thick.

The gate electrode 310 is made of n-type polysilicon.

The wiring insulating film 311 is . for example. PSG with a thickness of 0.6 μm
Consisting of

The source electrode 312 and drain electrode 313 are formed by depositing N and then patterning.

Field oxide film 314 is formed by the LOCOS method.

The drain region 305 is composed of a lightly doped drain region 306 lightly doped with impurities and a heavily doped drain region 307 heavily doped with impurities. This is to increase the withstand voltage between the source and drain.

In this example. Base oxide film 3 on silicon-based Fi 301
A drain lightly doped region 306 lightly doped with n-type impurities is shallowly doped by diffusion or ion implantation in a predetermined portion of the p-type So+ silicon layer 303 formed on the top of the 02 and divided into islands by the field oxide film 314. After forming, a drain high concentration region 307 heavily doped with n type impurities is formed by epitaxial growth on the drain lightly doped region 306 at the same time as a source region 304 heavily doped with n type impurities. .

therefore. In the 301 structure field effect transistor of this example. The channel-drain PN junction exists only between the low concentration drain region 306 and the channel region 308. Drain high concentration region 307 and channel nodule region 3
No joint failure occurs between the 08 and 08. therefore. Can increase pressure resistance. Also, drain high concentration nod area 3
The breakdown voltage is not defined by the impurity concentration of 07.

〔Effect of the invention〕

According to the invention. It becomes possible to improve the breakdown voltage between the source and drain and between the source and the silicon substrate.
This greatly contributes to improving the performance of ozi field effect transistors.

[Brief explanation of drawings]

FIG. 1 is a diagram showing Example 1. Fig. 2 is a diagram showing the second embodiment, and Fig. 3 is a diagram showing the third embodiment. Fig. 4 shows conventional example 1, and Fig. 5 shows conventional example 2. In FIGS. 1 to 3, 101, 201, 301: silicon substrate 102, 202
, 302: Base oxide film 103, 203, 303 + SOI silicon layer 104, 2
04, 3o4: Source order page area 105, 205.30
5: Drain region 106, 206, 306 + drain low concentration region 107, 207, 301: drain high concentration region 108, 208, aoa: channel region 109, 209
, 309: Gate oxide film 110, 210, 310: Gate electrode 111, 211, 311: Wiring insulating film 112, 212, 312: Source electrode

Claims (1)

[Claims] An island-shaped SOI silicon layer (103, 203, 30) of one conductivity type formed on a base oxide film (102, 202, 302) on a silicon substrate (101, 201, 301).
3) source regions (104, 204) of opposite conductivity type at both ends of the
, 304) and a drain region of opposite conductivity type (105,
205, 305) are formed, and drain regions (105, 305) are formed.
205, 305) are lightly doped with impurities (106, 206, 306) and heavily doped with impurities (107, 207).
, 307), and the source region (104, 204,
304) and drain regions (105, 205, 305
) in which the channel region (108, 208, 308) is formed, the drain high concentration region (107, 207, 307) is provided within the drain low concentration region (106, 206, 306) Or drain high concentration region (107, 207, 3
07) to the drain low concentration region (106, 206, 306
), the drain high concentration region (
107, 207, 307) are channel regions (108, 2
08, 308) A field effect transistor having an SOI structure, characterized in that it has a structure that does not make contact with the SOI structure field effect transistor.