JPH02239660A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH02239660A
JPH02239660A JP6034489A JP6034489A JPH02239660A JP H02239660 A JPH02239660 A JP H02239660A JP 6034489 A JP6034489 A JP 6034489A JP 6034489 A JP6034489 A JP 6034489A JP H02239660 A JPH02239660 A JP H02239660A
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Japan
Prior art keywords
layer
gaas
doped
xas
gaas layer
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JP6034489A
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Japanese (ja)
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JP2747316B2 (en
Inventor
Kikuo Kobayashi
小林 規矩男
Mutsuo Yamaga
山賀 睦夫
Takeo Suzuki
健夫 鈴木
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Japan Broadcasting Corp
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Nippon Hoso Kyokai NHK
Japan Broadcasting Corp
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  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

PURPOSE:To reduce a manufacturing cost by uniformly doping In in both a GaAs layer and an AlxGa1-xAs layer to form a hetero structure having small number of deep impurity level. CONSTITUTION:A hetero is composed of a GaAs layer 2 and an AlxGa(1-x)Ga layer 3 in which Si, Sn, S or Te is doped as an impurity. The component ratio (x) of Al in the layer 3 is set to a range of 0.2<=x<=0.4, and In is doped 1-10% (at%) in the layers 2, 3. Accordingly, a hetero structure of the layers 2, 3 having small deep impurity level can be formed. As a result, when Si, etc., is doped as an impurity in the layer 3, a high electron density is obtained, and temperature dependency of its electron density is eliminated. Thus, a manufacturing cost can be reduced.

Description

【発明の詳細な説明】[Detailed description of the invention]

【11!業上の利用分野】 本発明は、GaAs層とAfLGaAs層とを有するヘ
テロ構造.超格子構造または量子井戸構造を有する化合
物半導体装置に係り、特にそのAfl GaAs層にS
1.Sn,S,Teなどの不純物がドーピングされてい
る半導体装置の電気的特性の改良に関するものである. [発明の概要] 本発明は、GaAs層と^11 GaAs層とを有する
ヘテロ構造,超格子構造または量子井戸構造を有する化
合物半導体装置の改良に関するもので、これら構造にお
いて、不純物としてStなどをドーピング(添加)した
場合に生ずる深い不純物準位を、Inをドーブすること
により減少させるようにしたものである.
[11! [Field of Industrial Application] The present invention relates to a heterostructure having a GaAs layer and an AfLGaAs layer. It relates to a compound semiconductor device having a superlattice structure or a quantum well structure, and in particular, S is added to its Afl GaAs layer.
1. This paper relates to improving the electrical characteristics of semiconductor devices doped with impurities such as Sn, S, and Te. [Summary of the Invention] The present invention relates to an improvement of a compound semiconductor device having a heterostructure, a superlattice structure, or a quantum well structure including a GaAs layer and a ^11 GaAs layer. The deep impurity level that occurs when In is doped is reduced by doping In.

【従来の技術】[Conventional technology]

化合物半導体を用いた電子素子または光電子素子におい
ては、GaAs層と ^11 GaAs層とから成るヘ
テロ構造をその構成材料として多用している。その理由
は、GaAsの伝導帯の底に比べて^j2 GaAsの
伝導帯の底の方が電子系から見たエネルギーが高いため
、この二つの材料の接合面でエネルギーの段差が生ずる
ためであることは周知の通りである. 特に、最近は、高電子移動度トランジスタ(OEMT)
 ,量子井戸レーザ,量子井戸発光ダイオードなどにお
いて、かかる構造が用いられている。 しかし、これらの材料にキャリア(電流担体)を発生さ
せるためn型の不純物であるSiなどを^J! GaA
sの領域にドーピングすると深い不純物準位(いわゆる
DXセンター)が形成され、キャリアすなわち電子が十
分な密度に達しないことが知られている(たとえば、D
.V.Lang, R.A.Loagan andMj
aros ”Trapping Characteri
stics and aDonor− Complex
(DX) model for the PersIs
tentPhotoconductivity Tra
pping Center in Te−Doped 
  AIXGat−xAs  ”  Physical
  Review(B)vol.19,N6.2,pp
lo15−1030  1979).深い不純物準位は
GaAsには発生せず、A4 GaAsの混晶にStや
Teなどの不純物をドーピングすると発生する.深い不
純物準位の密度は^1の成分が20%以下の場合は比較
的少ない.すなわち混晶を^j! .Ga.−.^Sと
表わした場合にXが0.2以下の場合は余り問題とはな
らない.Xが0.2から0.3に増加すると深い不純物
準位の密度は急激に増加する.従ってA1の成分比Xを
小さくすることによって深い不純物準位の密度を低下さ
せることはできるものの、このようにすると、伝導帯の
底がGaAsのそれに近づくためにGaAsとAl G
aAsのへテロ界面における伝導帯の底の段差が減少し
てしまう.この段差は^j!GaAs層で発生した電子
をGaAs層内に閉じ込めるために必要である, Ga
As層内に電子を閉じ込めることが二次元電子ガスを利
用する素子では必要な条件となっている. そこで、従来の技術としては、 ^jl GaAsをG
aAsと^1^Sを数十オングストロームの厚みに交互
に積み重ねた超格子で置きかえ、この超格子のGaAs
層またはGaAs層と ^j2As層にSiなどの不純
物をドーピングする方法をとっている(たとえば小川正
毅.馬場寿夫,水谷降『超格子構造と選択的な不純物ド
ーピングによって化合物半導体の電子密度を上げる」日
経エレクトロニクス 1985年1月14日号pp21
3−240,あるいはκ.Kobayashi ,M.
Morita,  N.Kamata and T.S
uzuki  DeepElectron Traps
 in AIAs− GaAs Superlatti
cesas  Studied by  Deep−L
evel TransientSpectroscop
y, Japan Journal Appl1ed 
Physicsvol.27, No.2 ppl92
− 195 1988) .このようにすることによっ
て、深い不純物準位を作らずに、従って高い電子密度が
得られ、かつ超格子の実効的な意味における伝導帯の底
(実際には超格子のミニバンド)を比較的高くできる。 この超格子のAl AsとGaAsの厚さの比および周
期を適当に選定することによって任意所望のA1成分比
Xを持つ^ft,Gat−11ASの混晶と同一のバン
ドギャップを得ることができる. [発明が解決しようとする課題] 前述した超格子を製作するためには数十オングストロー
ムの厚みのGaAsとAj! Asをかなりの層数を積
み重ねなくてはならない.これは分子線エビタクシー(
MBE)または有機金属気相エビタクシー(MOCVD
)などの技術によフて可能ではあるものの、製造工程は
かなり複雑になる.さらに不純物を超格子の各層の界面
にドーピングしないようにするために結晶成長の操作は
さらに複雑なものとなっている。また、不純物のドーピ
ング密度を大きくすると、超格子が無秩序化現象によっ
て混晶化してしまう危険性にさらされる.半導体結晶成
長中や製造後に使用中に素子の温度が上昇しすぎたりし
ても、やはり無秩序化現象によって超格子の部分が混ざ
り合って混晶化する可能性がある. 本発明者は、種々の半導体材料を作って深い不純物準位
を測定しているうちに次のことを発見した。すなわち^
1 .Ga,−xAsにSiをドーピングし、これにI
nを数%ドーピングすると深い不純物準位の密度が減少
するということである. 第2図はAl o, 3Gao. 7AS (X−0.
3)にInをドーピングした場合に深い不純物準位の密
度が減少する様子を示している。特性曲線Aは電子密度
が室温で1 x 10”cm−’になるようにSIをド
ーピングした場合であり、特性曲線Bは4 X 10”
cm−”になるようにSiをドーピングした場合である
。いずれの場合にも、Inを4%程度ドーピングするこ
とによって深い不純物準位の密度が1桁程度低下するこ
とがわかる。 そこで、本発明の目的は、本発明者の上述の知見を利用
して深い不純物準位を減少させることを意図し、従来の
ように超格子を形成して深い不純物準位を減少させる場
合に生じる製造工程の複雑さ、結晶成長の操作の複雑さ
、超格子の混晶化のおそれという従来の問題点の解決を
図った化合物半導体装置を提供することにある。 [課題を解決するための手段] このような目的を達成するために、本発明の第1形態は
、GaAs層とSi,Sn.SまたはTeが不純物とし
てドーピングされている^JL.Ga,−,AS層とに
よりヘテロ構造を構成した半導体装置において、 ^1
1 xGa,−xAs層におけるAiの成分比Xを0.
2≦x″50.4の範囲に定め、かつGaAs層とAj
2 xGa,−xAs層の各々にInを1〜10%(a
t%》 ドーピングしたことを特徴とする。 本発明の第2形態は、GaAs層と51,Sn.Sまた
はTeが不純物としてドーピングされているAJI x
Ga+−xAs層とにより構成した超格子構造を有する
半導体装置において、AJlxGat−xAS層におけ
る^1の成分比Xを0.2≦x≦0.4の範囲に定め、
かつGaAs層と^f.Ga+−.AS層の各々にIn
を1〜10%(at%)ドーピングしたことを特徴とす
る. 本発明の第3形態は、GaAs層とSf,Sn,Sまた
はTeが不純物としてドーピングされているAj! x
Ga+−xAs層とにより構成した量子井戸構造を有す
る半導体装置において、AlxGa.−xAs層におけ
る八℃の成分比Xを0.2≦x≦0.4の範囲に定め、
かつGaAs層とAll .Ga,−xAs層の各々に
Inを1〜lO%(at%)ドーピングしたことを特徴
とする. [作 用] 本発明によれば、InをGaAs層およびAlgGal
−,lAS層の双方に一様にドーピングすることによっ
て、深い不純物単位の少ないAiGaAs層とGaAs
層のへテロ構造を構成することができ、その結果、 A
j2GaAs層にSiなどを不純物としてドーピングす
ると高い電子密度が得られ、また、その電子密度の温度
依存性がなくなる.そのため、HEMT (高電子移動
度トランジスタ)にこの材料を応用すると素子の特性を
向上させることができ、たとえば伝達コンダクタンスG
mが大きくなることと、しきい電圧vthの温度変化を
押えることができる.本発明によればInを車にドーピ
ングするだけで深い不純物準位を減少させることができ
、従来のような超格子構造など複雑な構造が一切不要と
なり、製造コストを大幅に低減することもできる. 【実施例] 以下、図面を参照して本発明の実施例を詳細に説明する
. 第1図(A)は本発明化合物半導体装置の一実施例にお
けるヘテロ構造の断面を示す. ここで、基板1上にInを5%ドーピングしながらGa
As層を成長させる.このGaAs層2の上に、51を
ドービンクすると共にInを5%ドーピングしながら^
ft6. =Gao, ?AS層3を成長させてヘテロ
界面4を有するヘテロ構造を形成する.AIto.sG
ao. yAs (Si)層3にInを5%ドーピング
すると、前述したように、深い不純物準位の密度を1桁
以上低減させることができる.しかし、Inをドーピン
グすることは+l GaAsとInAsの混晶を作るこ
とになる, InAsは禁制帯の幅が約0.36eVと
狭いためにAA GaAsの伝導帯の底が約46meV
 砥下する.このままではGaAsの伝導帯の底との段
差(バンドオフセット)が減少してしまい、GaAs層
に電子を閉じ込める能力が低下する. そこで、本発明では、GaAs層2にもInを同様にド
ーピングして、あらかじめ伝導帯の底を低下させてお<
.Inのドーピング量を5%とすると、伝導帯の底を約
35meV下げることができ、第1図(B)に示すよう
にInをドービン′グしない場合にほぼ等しい段差をつ
けることができる.段差を実験的に直接に正確に測定す
る方法はないが、次の計算によフて求めることができる
.GaAsとAj! o. 3Gao. yAsの禁制
帯の幅は各々1.42eVと1.8eVであり、その差
0.38eVの65%にあたる247meVがInをド
ーブしない場合のGaAsと^j! o. sGao,
 yAsの伝導帯の底の段差である, lnAsの禁制
帯の幅は約0.36eVであり、Af 6. sGao
. yAsのそれとの差1 .44eVの5%にあたる
72meVがInを5%ドーピングすることによる^J
! o. sGao. yAsの禁制帯が減少する量で
ある.これの65%にあたる4B+IeVがInをドー
ピングしたAj! 。, @Ga6.7^Sの伝導帯の
底が低下する大きさである, GaAsとAJ! o.
 3Ga6, ,^Sの禁制帯の幅の差の1i5%が伝
導帯の底の段差になフていることは現在では通説になっ
ている, InAsとGaAs,またはInAsとAi
GaAsの場合に、禁制帯の幅の何%が伝導帯の底の差
になるかははっきりとしたことは不明であるが、InG
aAsとGaAsのへテロ構造の場合にはGaAsと^
j! GaAsの場合と同程度の60%であるという報
告がある(たとえば、安藤,豊島,岡本.伊東r In
GaAsの歪層量井戸共鳴トンネルダイオードの試作お
よび解析』電子情報通信学会 電子デバイス研究会資料
ED86−106 9P13−20(1986)) .
また、Inのドーピング量は5%程度であるから、伝導
帯の底の段差の計算はGaAsと^fLO. 3Gaa
, ?^Sの場合の計算と同じ方法、すなわち禁制帯幅
の65%が伝導帯の底の段差になるという規則を用いて
行うことができる. 同様にして、GaAsと1nAsの禁制帯の幅1 .4
2eVと0.36eVの差は1.08aVとなり、これ
の5%のさらに65%は約35meVとなる.これが、
GaAsにInを5%ドーピングすることにより、伝導
帯の底が低下する大きさである. 本発明では、GaAs層およびAA GaAs層の両層
にInをドーピングすることより、All a. sG
ao. t^S(Si)深い不純物準位を発生させず、
かつGaAs側とのエネルギー段差をほとんど変えずに
保つことができる.段差がわずか(48meV−35+
*eV−11meV)減少するのを防止するためにはG
aAs側にはさらに2%ほど余分にInをドーピングす
ることによって段差を全く変えずに不純物準位の密度を
低減したべテロ構造を作ることも可能である. 第1図(^)は単純なヘテロ構造の例であるが、GaA
s層2の両側に^fL GaAsによる障壁層を配置し
た量子井戸構造、あるいはGaAs層2とAlGaAs
層3とを交互に周期的に積み重ねた超格子構造において
も、ヘテロ構造の場合と同様にInをドーピングするこ
とによってSiなどの不純物を作る深い不純物準位の発
生密度を低減させることができる. Inのドーピング量は多い方が深い不純物準位の低減に
有効であるが、基板1との格子定数が整合しなくなるた
めlO%程度以内におさえることが好ましい. 【発明の効果] 本発明によれば、InをGaAs層および^j!オGa
p−xAs層の双方に一様にドーピングすることによフ
て、深い不純物単位の少ないAl GaAs層とGaA
s層のへテロ構造を構成することができ、その結果、 
AI.GaAs層にSlなどを不純物としてドーピング
すると高い電子密度が得られ、また、その電子密度の温
度依存性がなくなる。そのため、HEMT(高電子移動
度トランジスタ)にこの材料を応用すると素子の特性を
向上させることができ、たとえば伝達コンダクタンスG
oが大きくなることと、しきい電圧vthの温度変化を
押えることができる。本発明によれば!nを単にドーピ
ングするだけで深い不純物準位を減少させることができ
、従来のような超格子構造など複雑な構造が一切不要と
なり、製造コストを大幅に低減することもできる.
In electronic devices or optoelectronic devices using compound semiconductors, a heterostructure consisting of a GaAs layer and a ^11 GaAs layer is often used as a constituent material. The reason for this is that the bottom of the conduction band of ^j2 GaAs has higher energy as seen from the electronic system than the bottom of the conduction band of GaAs, so a step in energy occurs at the junction of these two materials. This is well known. In particular, recently high electron mobility transistors (OEMTs)
, quantum well lasers, quantum well light emitting diodes, and the like, such structures are used. However, in order to generate carriers (current carriers) in these materials, n-type impurities such as Si are added ^J! GaA
It is known that when the s region is doped, a deep impurity level (so-called DX center) is formed, and carriers, that is, electrons, do not reach a sufficient density (for example, D
.. V. Lang, R. A. Logan and Mj
aros “Trapping Character”
sticks and a Donor- Complex
(DX) model for the PersIs
tentPhotoconductivity Tra
Ppping Center in Te-Doped
AIX Gat-xAs” Physical
Review (B) vol. 19, N6.2, pp
lo15-1030 1979). Deep impurity levels do not occur in GaAs, but are generated when the A4 GaAs mixed crystal is doped with impurities such as St and Te. The density of deep impurity levels is relatively small when the ^1 component is less than 20%. In other words, mixed crystals! .. Ga. −. When expressed as ^S, if X is 0.2 or less, there is not much of a problem. When X increases from 0.2 to 0.3, the density of deep impurity levels increases rapidly. Therefore, although it is possible to reduce the density of deep impurity levels by reducing the component ratio
The step at the bottom of the conduction band at the aAs heterointerface decreases. This step is ^j! Ga is necessary to confine the electrons generated in the GaAs layer.
Confining electrons within the As layer is a necessary condition for devices that utilize two-dimensional electron gas. Therefore, as a conventional technology, ^jl GaAs is
We replaced aAs and ^1^S with a superlattice stacked alternately to a thickness of several tens of angstroms, and created GaAs in this superlattice.
(For example, Masatake Ogawa, Toshio Baba, and Furu Mizutani, ``Increasing the electron density of compound semiconductors through superlattice structure and selective impurity doping.'' Nikkei Electronics January 14, 1985 issue pp21
3-240, or κ. Kobayashi, M.
Morita, N. Kamata and T. S
uzuki Deep Electron Traps
in AIAs- GaAs Superlatti
cesas Studied by Deep-L
evel Transient Spectroscope
y, Japan Journal Appl1ed
Physics vol. 27, No. 2 ppl92
- 195 1988). By doing this, a high electron density can be obtained without creating deep impurity levels, and the bottom of the conduction band in the effective sense of the superlattice (actually, the miniband of the superlattice) can be relatively lowered. Can be made high. By appropriately selecting the thickness ratio and period of AlAs and GaAs in this superlattice, it is possible to obtain the same band gap as the Gat-11AS mixed crystal with any desired A1 component ratio X. .. [Problems to be Solved by the Invention] In order to fabricate the above-mentioned superlattice, GaAs and Aj! with a thickness of several tens of angstroms are required. A considerable number of layers of As must be stacked. This is a molecular beam shrimp taxi (
MBE) or metal organic vapor phase epitaxy (MOCVD)
), but the manufacturing process is quite complicated. Furthermore, crystal growth operations have become even more complex in order to avoid doping impurities into the interfaces of each layer of the superlattice. Furthermore, increasing the doping density of impurities exposes the superlattice to the risk of becoming mixed crystals due to disordering phenomena. Even if the temperature of the device rises too much during semiconductor crystal growth or during use after manufacturing, there is still a possibility that the superlattice parts will mix together due to disordering phenomena and form a mixed crystal. The present inventor discovered the following while making various semiconductor materials and measuring deep impurity levels. That is, ^
1. Ga, -xAs is doped with Si, and I
This means that doping a few percent of n reduces the density of deep impurity levels. Figure 2 shows Al o, 3 Gao. 7AS (X-0.
3) shows how the density of deep impurity levels decreases when In is doped. Characteristic curve A is the case when SI is doped so that the electron density is 1 x 10"cm-' at room temperature, and characteristic curve B is the case when SI is doped so that the electron density is 1 x 10"cm-' at room temperature.
This is the case where Si is doped so that the concentration of In is doped to 4% In. The purpose of this is to reduce deep impurity levels by utilizing the above-mentioned findings of the present inventors, and to reduce the deep impurity levels by forming a superlattice as in the conventional manufacturing process. The object of the present invention is to provide a compound semiconductor device that solves the conventional problems of complexity, complexity of crystal growth operations, and fear of superlattice mixing. [Means for solving the problems] As described above. In order to achieve this object, a first embodiment of the present invention provides a semiconductor in which a heterostructure is formed by a GaAs layer and a ^JL.Ga,-,AS layer doped with Si, Sn.S, or Te as an impurity. In the device, ^1
The component ratio X of Ai in the 1xGa, -xAs layer is set to 0.
2≦x″50.4, and the GaAs layer and Aj
2. In each of the xGa and -xAs layers, 1 to 10% (a
t%》 Characterized by doping. A second embodiment of the present invention includes a GaAs layer and 51, Sn. AJI x doped with S or Te as an impurity
In a semiconductor device having a superlattice structure composed of a Ga+-xAs layer, the component ratio X of ^1 in the AJlxGat-xAS layer is set in the range of 0.2≦x≦0.4,
and a GaAs layer ^f. Ga+-. In each AS layer
It is characterized by being doped with 1 to 10% (at%). A third embodiment of the present invention is a GaAs layer doped with Sf, Sn, S, or Te as an impurity. x
In a semiconductor device having a quantum well structure composed of a Ga+-xAs layer, an AlxGa. -x The component ratio X at 8°C in the As layer is set in the range of 0.2≦x≦0.4,
and GaAs layer and All. It is characterized in that each of the Ga and -xAs layers is doped with In at 1 to 10% (at%). [Function] According to the present invention, In is added to the GaAs layer and the AlgGal layer.
-, By uniformly doping both the AiGaAs layer and the GaAs layer with few deep impurity units.
A heterostructure of layers can be constructed, resulting in A
When the j2GaAs layer is doped with Si or the like as an impurity, a high electron density can be obtained, and the temperature dependence of the electron density can be eliminated. Therefore, when this material is applied to HEMT (high electron mobility transistor), it is possible to improve the characteristics of the element, for example, the transfer conductance G
As m increases, temperature changes in the threshold voltage vth can be suppressed. According to the present invention, deep impurity levels can be reduced simply by doping In into a car, eliminating the need for any complicated structures such as conventional superlattice structures, and significantly reducing manufacturing costs. .. [Examples] Examples of the present invention will be described in detail below with reference to the drawings. FIG. 1(A) shows a cross section of a heterostructure in an embodiment of the compound semiconductor device of the present invention. Here, while doping 5% In on the substrate 1, Ga
Grow the As layer. On this GaAs layer 2, 51 is doped and In is doped to 5%.
ft6. =Gao, ? The AS layer 3 is grown to form a heterostructure having a heterointerface 4. AIto. sG
ao. When the yAs (Si) layer 3 is doped with 5% In, the density of deep impurity levels can be reduced by more than one order of magnitude, as described above. However, doping with In creates a mixed crystal of +l GaAs and InAs.InAs has a narrow forbidden band width of about 0.36 eV, so the bottom of the conduction band of AA GaAs is about 46 meV.
Polish. If this continues, the step difference (band offset) between the conduction band and the bottom of GaAs will decrease, and the ability to confine electrons in the GaAs layer will decrease. Therefore, in the present invention, the GaAs layer 2 is also doped with In to lower the bottom of the conduction band in advance.
.. If the In doping amount is 5%, the bottom of the conduction band can be lowered by about 35 meV, and as shown in Figure 1 (B), it is possible to create a step that is almost the same as when In is not doped. Although there is no way to directly and accurately measure the height difference experimentally, it can be determined by the following calculation. GaAs and Aj! o. 3Gao. The width of the forbidden band of yAs is 1.42 eV and 1.8 eV, respectively, and 247 meV, which is 65% of the difference of 0.38 eV, is compared to GaAs when In is not doped! o. sGao,
The width of the forbidden band of lnAs, which is the step at the bottom of the conduction band of yAs, is about 0.36 eV, and Af 6. sGao
.. Difference from that of yAs1. 72meV, which is 5% of 44eV, is due to 5% In doping^J
! o. sGao. This is the amount by which the forbidden band of yAs decreases. 4B+IeV, which is 65% of this, is In-doped Aj! . , which is the size that the bottom of the conduction band of @Ga6.7^S drops, GaAs and AJ! o.
It is now generally accepted that 1i5% of the difference in the width of the forbidden band of 3Ga6, ,^S is used as the step at the bottom of the conduction band.
In the case of GaAs, it is not clear what percentage of the width of the forbidden band corresponds to the difference in the bottom of the conduction band, but in the case of InG
In the case of a heterostructure of aAs and GaAs, GaAs and ^
j! There are reports that it is 60%, which is about the same as in the case of GaAs (for example, Ando, Toyoshima, Okamoto, Itor In
``Prototype and analysis of GaAs strained layer well resonant tunnel diode'', Institute of Electronics, Information and Communication Engineers Electronic Devices Research Group Material ED86-106 9P13-20 (1986)).
Also, since the In doping amount is about 5%, the step difference at the bottom of the conduction band can be calculated between GaAs and ^fLO. 3Gaa
, ? It can be done in the same way as the calculation for ^S, using the rule that 65% of the forbidden band width is the step at the bottom of the conduction band. Similarly, the width of the forbidden band of GaAs and 1nAs is 1. 4
The difference between 2eV and 0.36eV is 1.08aV, and 65% of this 5% is about 35meV. This is,
By doping GaAs with 5% In, the bottom of the conduction band is lowered. In the present invention, by doping both the GaAs layer and the AA GaAs layer with In, All a. sG
ao. t^S (Si) does not generate deep impurity levels,
Moreover, the energy level difference with the GaAs side can be maintained almost unchanged. There is only a slight difference in level (48meV-35+
*eV-11meV) To prevent the decrease, G
By doping an additional 2% of In on the aAs side, it is also possible to create a beta structure in which the density of impurity levels is reduced without changing the step at all. Figure 1 (^) is an example of a simple heterostructure, GaA
Quantum well structure with GaAs barrier layers placed on both sides of the s layer 2, or GaAs layer 2 and AlGaAs
Even in a superlattice structure in which layers 3 and 3 are stacked periodically, the density of deep impurity levels that create impurities such as Si can be reduced by doping In as in the case of a heterostructure. The larger the amount of In doped, the more effective it is in reducing deep impurity levels, but since the lattice constant with the substrate 1 will no longer match, it is preferable to keep it within about 10%. [Effects of the Invention] According to the present invention, In is added to the GaAs layer and the ^j! Oh Ga
By uniformly doping both p-xAs layers, an AlGaAs layer and a GaA layer with few deep impurity units can be formed.
A heterostructure of the s-layer can be constructed, and as a result,
A.I. When the GaAs layer is doped with Sl or the like as an impurity, a high electron density can be obtained, and the temperature dependence of the electron density can be eliminated. Therefore, when this material is applied to HEMT (high electron mobility transistor), it is possible to improve the characteristics of the element, for example, the transfer conductance G
It is possible to increase o and suppress temperature changes in the threshold voltage vth. According to the invention! Deep impurity levels can be reduced simply by doping n, eliminating the need for complex structures such as conventional superlattice structures, and significantly reducing manufacturing costs.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(A)は、本発明の一実施例としてヘテロ構造を
有する半導体装置の構成例を示す構成図、 第1図(B)は、第1図(A)に示した実施例のへテロ
界面の伝導帯の底のエネルギー関係を示すエネルギーレ
ベル図、 第2図はInをドーピングすると深い不純物準位の密度
が低減する様子を説明する特性図である。 1・・・基板、 2・・・GaAs層、 3 −−− Al GaAs層、 4・・・ヘテロ界面。
FIG. 1(A) is a block diagram showing a configuration example of a semiconductor device having a heterostructure as an embodiment of the present invention, and FIG. 1(B) is a block diagram of the embodiment shown in FIG. 1(A). FIG. 2 is an energy level diagram showing the energy relationship at the bottom of the conduction band at the telo interface. FIG. 2 is a characteristic diagram illustrating how the density of deep impurity levels decreases when doping with In. DESCRIPTION OF SYMBOLS 1...Substrate, 2...GaAs layer, 3---AlGaAs layer, 4...Hetero interface.

Claims (1)

【特許請求の範囲】 1)GaAs層とSi、Sn、SまたはTeが不純物と
してドーピングされているAl_xGa_1_−_xA
s層とによりヘテロ構造を構成した半導体装置において
、前記Al_xGa_1_−_xAs層におけるAlの
成分比xを0.2≦x≦0.4の範囲に定め、かつ前記
GaAs層と前記Al_xGa_1_−_xAs層の各
々にInを1〜10%(at%)ドーピングしたことを
特徴とする半導体装置。 2)GaAs層とSi、Sn、SまたはTeが不純物と
してドーピングされているAl_xGa_1_−_xA
s層とにより構成した超格子構造を有する半導体装置に
おいて、前記Al_xGa_1_−_xAs層における
Alの成分比xを0.2≦x≦0.4の範囲に定め、か
つ前記GaAs層と前記Al_xGa_1_−_xAs
層の各々にInを1〜10%(at%)ドーピングした
ことを特徴とする半導体装置。 3)GaAs層とSi、Sn、SまたはTeが不純物と
してドーピングされているAl_xGa_1_−_xA
s層とにより構成した量子井戸構造を有する半導体装置
において、前記Al_xGa_1_−_xAs層におけ
るAlの成分比xを0.2≦x≦0.4の範囲に定め、
かつ前記GaAs層と前記Al_xGa_1_−_xA
s層の各々にInを1〜10%(at%)ドーピングし
たことを特徴とする半導体装置。
[Claims] 1) Al_xGa_1_-_xA doped with a GaAs layer and Si, Sn, S, or Te as impurities.
In the semiconductor device having a heterostructure formed by the GaAs layer and the Al_xGa_1_-_xAs layer, the Al component ratio x in the Al_xGa_1_-_xAs layer is set in the range of 0.2≦x≦0.4, and the Al_xGa_1_-_xAs layer is A semiconductor device characterized in that each of the semiconductor devices is doped with 1 to 10% (at%) of In. 2) Al_xGa_1_-_xA doped with GaAs layer and Si, Sn, S, or Te as impurities
In a semiconductor device having a superlattice structure constituted by the GaAs layer and the Al_xGa_1_-_xAs, the component ratio x of Al in the Al_xGa_1_-_xAs layer is set in a range of 0.2≦x≦0.4, and the GaAs layer and the Al_xGa_1_-_xAs
A semiconductor device characterized in that each of the layers is doped with 1 to 10% (at%) of In. 3) Al_xGa_1_-_xA doped with GaAs layer and Si, Sn, S, or Te as impurities
In a semiconductor device having a quantum well structure constituted by an s layer, the Al_xGa_1__xAs layer has an Al component ratio x in a range of 0.2≦x≦0.4,
and the GaAs layer and the Al_xGa_1_-_xA
A semiconductor device characterized in that each of the s-layers is doped with 1 to 10% (at%) of In.
JP6034489A 1989-03-13 1989-03-13 Semiconductor device Expired - Fee Related JP2747316B2 (en)

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JPH02239660A true JPH02239660A (en) 1990-09-21
JP2747316B2 JP2747316B2 (en) 1998-05-06

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