JPH02238500A - Voice recorder using nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To make this voice recorder small in size, and also, to allow it to display an excellent performance which cannot be obtained by a tape recorder by using a nonvolatile semiconductor memory which can execute electrical rewriting as a voice recording medium. CONSTITUTION:This voice recorder is provided with an A/D converter 12 for converting an output of a microphone 11 to a digital signal, an EEPROM (nonvolatile semiconductor memory) 13 in which this output is written, and a D/A converter 14 for converting this read-out output to an analog signal. Also, this voice recorder is constituted of a loudspeaker 15 for bringing an output of the D/A converter 14 to electo-acoustic conversion and outputting it, an input part 17 having various operating switches containing a sound recording switch and a reproducing switch, and a CPU 16 for controlling the EEPROM 13 by a signal from this input part 17 and executing its write and read-out. In such a way, by using the EEPROM 13, a miniature voice recorder having no mechanical part is obtained, and since an access is executed only electrically, an excellent performance which a tape recorder does not have can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an audio recording device using an electrically rewritable large-capacity nonvolatile semiconductor memory as a recording LA medium.

(Prior Art) Currently, so-called tape recorders that generally use magnetic tape are widely used as small-sized audio recording devices. However, since tape recorders include a complex mechanical structure, there are limits to miniaturization, battery life is short, wear is caused by repeated use, and random access is difficult. Also recording,
There is also a limit to the start-up speed of playback.

On the other hand, the progress of semiconductor technology in recent years has been remarkable, and the capacity of various semiconductor memories has increased significantly. Along with this, various applications of semiconductor memory to analog information processing such as audio information and image information are being considered.

However, to date, the application of semiconductor memory to audio recording has been limited to short-term recordings of a few minutes at most, such as in answering machines and various toys. Moreover, the semiconductor memory used in these devices is so-called dynamic RAM (DRA), which loses information when the power is turned off.
M) and required a backup power source to maintain records.

(Problem to be solved by the invention) As mentioned above, since the tape recorder is mechanical,
There were limits to miniaturization, lifespan, performance, etc.

The present invention solves these problems and provides an audio recording device using semiconductor memory that has functions compatible with tape recorders, is small in size, and can exhibit excellent performance that cannot be obtained with tape recorders. 11th.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a non-volatile semiconductor memory (electronically rewritable) as an audio recording medium.
rlcally E rasablc and P r
A grammable ROM (hereinafter referred to as EEFROM) is used.

That is, the audio recording device according to the present invention includes a microphone. An A/D converter that converts the output signal of this microphone into a digital signal. An EEPROM that stores the output signal of this A/D converter, a D/A converter that converts the output signal of this EEFROM into an analog signal, a speaker that converts the output signal of this D/A converter into audio and outputs it, a recording switch, and an input section including a regeneration switch, and a signal from this input section to
It is characterized by having a processor that controls writing and reading of the OM.

(Function) According to the present invention, by using an EEPROM that digitizes and records audio data as a recording medium instead of a magnetic tape, a compact audio recording device that can replace a tape recorder without a complicated mechanism can be obtained. It will be done. For example, by using 4 Mbit EEPRO-1, it is possible to record several tens of minutes. The casing is not subject to the same restrictions as in the case of magnetic tape, and can be of any shape, such as a card shape or a pencil shape. EEPROM stores data in a nonvolatile manner even when the power is turned off, so it does not require a backup power source. Therefore, for example, if the EEPROM is configured as a card and separate from the casing, it can be handled like a magnetic disk.

Furthermore, since the audio recording device of the present invention is accessed only electrically, it can obtain performance not found in tape recorders. That is, the start-up speed of recording and playback is faster than that of a tape recorder. It is also possible to provide a high-speed cue function during recording and playback. This is, for example, EE
This can be realized in a package by providing a control data area in the PROM separate from the audio data area, and recording the previous recording end address, an address for instructing 11i playback from the middle, etc. as control data. In addition, when performing compressed recording in which silent periods are reduced, conventional tape running systems suffer from cutting off the beginning of the rise and producing unpleasant sounds due to changes in speed, but these problems are resolved.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an audio recording device according to an embodiment, and FIG. 2 shows the memory configuration of its EEPROM. As shown in FIG. 1, this audio recording device includes a microphone 11, an A/D converter 12 that converts the output of the microphone 11 into a digital signal, and an A/D converter 12 that converts the output of the microphone 11 into a digital signal.
EEPROM 13. to which the output of converter 12 is written.
A D/A converter 14 that converts the readout output of this EEPROM 13 into an analog signal, and a speaker 1 that converts the output of this D/A converter 14 into electrical and acoustic signals and outputs it.
5, an input unit 17 having various operation switches including a recording switch and a playback switch, and a CPU 16 that controls the EEPROM 13 and writes and reads data by using signals from the input unit 17. In this embodiment, the input section 17 includes recording switches SWI,
In addition to the regeneration switch SW2, a continuous start switch S
W3 and auto return switch SW4.

EEPROM13 is a 4M bit NAND cell type EE
It is PROM. The configuration and operating principle of this EEPROM 13 will be explained below.

FIG. 10 is a block diagram showing the structure of the NAND cell type EEPROM. Chip enable terminal CE. serves as an external control signal terminal. It has an output enable terminal OE and a write enable terminal WE, 18 address signal terminals AO'-A18, 8 data input/output terminals I/Oo to I/07, and a power supply terminal V.
Has cc and VSS. In this embodiment, the memory cell array 1 has a capacity of 4 Mbits and is made up of four memory cells collectively configured in a NAND type, as will be described later. Bit line BLI of memory cell array 1 =BLm (m
-2048) is connected to the sense amplifier/de-latch circuit 5. Selection gate line S G in, S
G 2n and word line WL! n-WL4n (n-5
12) is connected to the row decoder 3. The address signal is input to the row decoder 3 and column decoder 4 via the address buffer 72, thereby performing valley selection. When reading, is the bit line BL? -B
The data output to Lm is amplified and latched by the sense amplifier/data latch circuit 5, and sent to the input/output terminal via the output buffer 6! /0. ~! /07 is output to the outside.

When writing data, input/output terminal I/O. The data input from -1/O■ is taken into the sense amplifier/data latch circuit 5 via the input buffer 7, and then written into the memory cell at the selected address. 8 is a control logic circuit that generates an internal control signal from an external control signal.

FIG. 11 is an equivalent circuit showing the configuration of the memory cell array 1. The memory cell Mlj is a FETMOS type in which a floating gate and a control gate are stacked over the entire channel region with a thin gate insulating film interposed therebetween. For example, in the case of an n-channel, data erasing (or writing) is an operation that moves the threshold value in the negative direction by applying a high positive voltage to the control gate and temporarily releasing electrons from the floating gate through F-N tunneling. By keeping the control gate at “L” level and applying a positive high voltage to the drain, F
-N} The operation of injecting electrons into the floating gate by tunneling to move the threshold value in the positive direction corresponds to data writing (or erasing). The high voltage used for data writing and erasing is
It is generated by a booster circuit in the decoder 4. These memory cells constitute a so-called NAND cell in which four memory cells are connected in series to form one block, with their sources and drains shared by adjacent cells. NAN
One end of the D cell is connected to bit IIB via selection gate Qsl.
The other end is connected to the source line VS via the selection gate Qs2. The memory cells are arranged in a matrix as shown, and the control gates of the memory cells in the row direction are commonly connected to the word line WL.

FIG. 12 is a timing chart at the time of reading. By setting chip enable terminal CE and output enable terminal OE to "L" level and changing the address by setting write enable terminal WE to "H" level, eight memory cell data are transferred to the sense amplifier/data latch circuit. ? to input/output lines I/Oo to I/O■.

FIG. 13 is a timing chart during writing. By setting the chip enable terminal CE to the "L" level and the output enable terminal OE to the "H" level, and toggling the write enable terminal WE in synchronization with the address signal, the human output line I/O. ~I/07
The data inputted from the memory is latched into the sense amplifier/data latch circuit 5 via the input buffer, and sequentially written to selected addresses.

In such a NAND cell type EEPROM, multiple memory cells are connected to the bit line at once, so the number of contacts with the bit line is significantly greater than when each memory cell is connected to the bit line. Therefore, it has the advantage that it can be integrated at extremely high density.

In this embodiment, the EEPROM 3 is divided into an audio data area and a control data area, as shown in FIG. The control data area stores the previous recording end address, a specified address externally set during reproduction, a signal indicating whether recording is possible, and the like.

Next, the specific operation in the recording mode will be explained according to the flowchart of FIG. 3(a). By turning on the recording switch (2), the CPU 16 detects the signal and starts the flow shown in FIG. 3(a). First, CPU16
The recordability signal B of the control data area of the PROM 13 is read out and determined (PI), and if No, a message is output (P2) and the process ends. If YES, then turn on the continuous start switch ■. Detect off (P3). If the continuous start switch ■ is on, the CPU 16 reads the previous recording end address A from the control data area of the EEPROM and stores it in the address pointer AA (P5).
If it is off, take the start address "OO" of the audio data area of the EEFROM 13 into the address pointer AA (
P4). Then, it detects whether the recording switch ■ is on or off (P6), and if it is off, the address pointer AA at that time is
The contents are stored in the control data area of the EEPROM 13 as the recording completion address A (P7), and the process ends.

If the recording switch [phase] is on, the CPU 16 issues a write control signal and writes audio data to a predetermined address in the audio data area of the EEPROM 13 specified by the address pointer (P8). Then, the contents of the address pointer AA are sequentially updated (P9) and an address signal is issued, and the EEFROMI 3 is accessed serially to sequentially write audio data into the audio data area. When the maximum address AMAx of the audio data area is detected (PIO),
Detects whether the auto return switch is on or off (
P11). If the auto return switch ■ is off, a termination message will be output (P12) and recording will end. When it is detected that the auto-return switch ■ is turned on, the start address "00'' of the audio data area is loaded into the address pointer AA (P13), and writing of audio data is continued again from the start address.

Next, the operation in the case of reproduction will be explained with reference to the flow shown in FIG. 3(b). This flow is started by turning on the playback switch ■. First, turn on the continuous start switch ■. Determine whether it is off (Ql), and if it is off, set the start address of the audio area to address pointer AA, and if it is on, set the address specified from the outside to address pointer A.
Set to A (Q3). Then turn on the playback switch,
It is determined whether it is off (Q4), and if it is on, the audio data is read from the selected address (QB). Then, the address is updated (Q7), and it is determined whether it has reached the final address (Q8). If it has not reached the final address, data reading is repeated. When the final address is detected, it is determined whether the auto-return contest is on or off (Q9), and the auto-return (Q11) or end (Q12) is performed as in the case of recording.

In this way, according to this embodiment, it is possible to perform recording with the same function as a tape recorder. Also, by operating the continuous start switch (■), it is possible to output the start address of the unrecorded area and perform recording from the point at which the previous recording ended. This cueing is done almost instantaneously, so
This can be said to be an excellent feature not found in tape recorders. The same goes for the auto-return function, which allows you to re-record with almost no waiting time.

Next, fast forward. A more multi-functional embodiment having functions such as reverse feed and compression of silent periods will be described. The basic configuration is the same as that shown in FIG. FIGS. 4 to 6 show the control flow by the CPU including recording and playback. Figure 7 shows the switch group of the input section, as shown in the figure, the recording switch
, playback switch■. Start address switch ■ that instructs recording and playback from the first address, continuous address switch ■ that instructs recording and playback from the middle, auto return switch ■, fast forward switch ■. Reverse feed switch■. There are compression switches (■) and random access switches (■) used when recording and playing back with reduced silent periods.

This flow starts if the recording switch ■ or the playback switch ■ is on. First, the content on the display D is determined (St). For example, on display D, 4
Displayed in hexadecimal digits, 00 if recording and playback are possible.
00 is displayed, and if recording is prohibited, recording prohibition data FFFF in the control data is displayed, and other control information such as a password is displayed. If it is FFFF, it is determined whether to record or play in step S2,
If the recording switch is on, a message is output and the process ends. 0000 allows recording and playback, FFF prohibits recording
In cases other than F, it is determined in step S3 whether the content on the display D matches the password, and if they do not match, a message is output and the process ends. If they match, the process advances to the next step S4. Here, the start mode is determined as to whether the first address switch (2) is on, the continuous address switch (2) is on, or the random access switch (2) is on. If the start address switch (3) is on, the start address "00" of the audio data area of the EEPROM is written into the address pointer AA (S8). If the continuous address switch (2) is on, continuous address data A in the control data area is written to the address pointer (S5). If the random access switch ■ is on, it is determined whether this is instructed on the display D by an external setting (S
(1) If so, the address on the display D is written to the address bonder AA (S7).

Next, in step S9, it is determined whether the fast-forward switch (2) is on or the reverse switch (2) is on. If the fast forward switch ■ is on, the setting (α-2) is made to update the address continuously for two steps (S
IO), if the reverse switch ■ is on, the address is updated one step at a time in the reverse direction (α--1)
is made, and in other cases, a setting (α-1) is made to perform normal update one step at a time. These data are recorded in the control data area of the EEFROM. Next, it is determined whether the compression switch ■ is on or not (
S13). If the compression switch ■ is off, the process moves to the flow shown in FIG. 5, and if it is on, the process moves to the flow shown in FIG.

With reference to FIG. 5, the recording and playback operations when not in compression mode will be explained. First, it is determined whether the recording switch ■ or the playback switch ■ is on or off (S14). If both are off, the contents of address pointer AA are written to address A of the control data area and the process ends (S1
5). If the recording switch ■ is on, writing to the EEPROM is executed (S1g). Playback switch■
If is on, read the EEFROM (
S17).

Then, the address that was set earlier is updated in the step (Sl8), and it is determined whether the contents of the address pointer AA have become the final address (S9), and if the contents have not become the final address, the specified address is The process returns to step Sl4 with the sampling timing of , and when it detects one step before the final address where the same cycle is repeated, it determines whether the auto return switch ■ is on or off (S20,
S22), if it is off, output a message and end; if it is on, set the maximum address AMAX to the address pointer AA (S23) Step Sl4
Return to When the final maximum address +1 is detected, the address pointer AA is set to address "00" and the process returns to step Sl4 to repeat the access from the first address. So fast forward. Reverse feed. Recording with features such as auto return. A playback operation is performed.

Next, the operation in the compression mode will be explained using FIG. This compression detects the sound pressure level during recording, and if it is below a certain threshold, stops updating the address when the sound pressure level remains below that threshold for a certain period of time, and sets the interval. This is done by making it larger than normal. Then, the address update stop time is recorded as data that is less than the threshold value T11 at the time of playback, and during playback, the silent period is played back by delaying the update of the address by the time length represented by the data. In other words, first turn on the recording switch ■ or the playback switch ■. If off is detected (S24) and the recording switch is on, the register β for recording the time during which the sound pressure level is below the threshold value is first reset (S24).
G), it is determined whether the sound pressure level is below a threshold value for a certain predetermined period of time (S27). If NO,
Update the address as usual (S33), and
Audio data is written to M (S34). When it is detected that the sound pressure level is below the threshold value for a certain period of time, the register β is incremented by 1 (828), and the contents of the register β are recorded (S30). Then, it is determined whether the contents of register β have reached a certain value (S30),
If it is less than the predetermined value, wait a time predetermined by the timer (S32), and then repeat the judgment whether or not the pressure is less than the threshold value for a predetermined time (S27), and set 1 to register β. I will add. When the contents of register β exceed a certain value, update the address (S31)
. If a silent period continues in this way, for example, the address is made to advance only one step while it normally advances by 64 steps, and data representing the silent period is recorded with a value below the threshold value at the time of reproduction.

When it is determined that the sound pressure exceeds the threshold value (S2
7), EEP from the address set in step S31
Write data to ROM.

During playback, the data value is set to a predetermined threshold value T. It is determined whether or not it is below the L threshold (S35), and if it is not below the L threshold, it is considered normal recording and the address is updated as usual (S40), and the data from the EEPROM is read (S41). If it is below the threshold value, record data indicating the silent period at that time in register γ (33B).
, counts down until the contents of this register γ becomes 0 (S37 to S39), stops updating the address during that time, and determines that the contents of register γ becomes 0 (
S37) Start address update (S49) EE
PRO! The data of vl is read (S41). This allows the compressed and recorded data to be played back including silent periods.

After that, detection of the maximum address (S43) and determination of whether or not to perform auto-return (S44, S413)
) etc. are the same as when not in compression mode.

As described above, according to this embodiment, fast forwarding, reverse forwarding. An audio recording device having various functions such as compressed recording of silent periods can be obtained.

The present invention is not limited to the above embodiments. For example, as an alternative to a small tape recorder, a recording/reproducing device having a card type or other arbitrary shape can be configured with portability in mind. This is because the main body is E E F R
This is possible because there are no restrictions on the shape or size of OM or CPυ. For example, FIG. 8 shows an example of a card type. An EEFROM or other integrated circuit chip 21 is embedded in the card like a memory card, and a battery 22, a switch 23, an earphone 24, etc. are provided as shown. Further, it can easily be made into a pencil type as shown in FIG. EEPROM chips and other integrated circuit chips 3
1 are stacked vertically as shown in the diagram and stored in the case, and batteries 3
2. An amplifier 33 and the like are also incorporated, and an earphone 34 is attached to make it compact. In the case of a pencil type, it would be more convenient if the lower half housing the tip 31 could be replaced. Recordings may be made at home.

[Effects of the Invention] As described above, according to the present invention, by using an EEFROM, a small-sized audio recording device without mechanical parts can be obtained. The shape of the casing is not limited as in the case of magnetic tape, and any shape can be adopted. Furthermore, the entire device can be configured as a card type, like a magnetic disk. In addition, since access is only electrical, the start-up speed of recording and playback is fast, and functions such as compression recording, which records at the beginning of a high-speed recording by closing the silent period, can be easily added.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an audio recording device according to an embodiment of the present invention, and FIG. 2 shows an EEFRO used in the recording device.
Figures 3(a) and 3(b) are diagrams showing the control flow for explaining the recording and playback operations of the recording device, and Figures 4 to 6 are diagrams showing the memory configuration of M. A diagram showing a control flow for explaining the operation of the recording apparatus of the embodiment, FIG. 7 is a diagram showing the configuration of the input section, FIG. TS8 and FIG.
FIG. 10 is a block diagram showing the configuration of EEFROM used in the example; FIG. 11 is a diagram showing its memory cell array; FIGS. 12 and 13 are timing charts for explaining the data write and read operations. 11... Microphone, 12... A/D converter, 13... EEPROM, 14... D/A converter, 15... Speaker, 16... CPU, 17...
...Input section. Figure 1 Applicant's agent Patent attorney Takehiko Suzue Figure 2 Figure (b) Figure 4 Figure 9 Figure 11

Claims (3)

[Claims] (1) A microphone, an A/D converter that converts the output signal of this microphone into a digital signal, an electrically rewritable nonvolatile semiconductor memory that stores the output signal of this A/D converter, and an output of this semiconductor memory. A D/A converter that converts signals into analog signals, a speaker that converts the output signal of this D/A converter into audio and outputs it, an input section that includes a recording switch and a playback switch, and a signal from this input section. An audio recording device comprising: a processor that controls writing and reading of the semiconductor memory. (2) A microphone, an A/D converter that converts the output signal of this microphone into a digital signal, an electrically rewritable nonvolatile semiconductor memory that stores the output signal of this A/D converter, and an output of this semiconductor memory. a D/A converter that converts a signal into an analog signal; a speaker that converts the output signal of the D/A converter into audio and outputs it; an input section including a recording switch, a continuous start switch, and a playback switch; and the recording switch. means for generating a control signal and an address signal for serially writing audio data into the audio data area of the semiconductor memory from the first address by detecting the on state of the recording switch and the off state of the continuous start switch; means for generating a control signal and an address signal for reading a final recording end address from a control data area of the semiconductor memory and serially writing audio data into the audio data area from the next address; means for detecting that the switch is off and storing a recording end address in a control data area of the semiconductor memory, and then stopping writing; and detecting that the playback switch is on or off and serially reading audio data from the semiconductor memory. An audio recording device comprising: and means for generating an address signal and a signal for controlling the stoppage of the audio recording device. (3) The nonvolatile semiconductor memory is an EEPROM in which a plurality of FETMOS type memory cells having floating gates and control gates are connected in series with adjacent ones sharing the source and drain to form a NAND cell ( 1
) or (2).