JPH02238489A - Signal amplifying circuit - Google Patents

Abstract

PURPOSE:To independently and stably amplify plural kinds of signals by setting an input terminal of an operational amplifier to which a first and a second signals are inputted to a virtual ground level at the time of bringing these first and second signals to inversion amplification. CONSTITUTION:When a first signal Sh and a second signal Sv are inputted to an input terminal P1 of an operational amplifying circuit OP, as for a first signal Sh, its amplitude is varied between for instance, a ground level being a reference level or its approximate level and a first level being larger than this reference level. On the other hand, as for a second signal Sv, its amplitude is varied between for instance, the reference level and a second level being smaller than this reference level. By setting the input terminal P1 to which such a first and a second signals Sh, Sv are inputted to a virtual ground level, both the signals can be amplified stably. In such a way, plural kinds of signals can be amplified independently and stably.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a signal amplification circuit that can independently amplify multiple types of signals using a single operational amplifier. .

(Subsidiary Technology) Conventionally, a so-called composite signal containing a video signal and a synchronization signal has been used for an interface of a display device, etc.

The conventional example shown in FIG. 4 has a synchronizing signal sh and a video signal 3v.
This shows a case where the composite signal SC is generated by adding the above. The synchronization signal sh is a digital signal such as a horizontal synchronization signal or a vertical synchronization signal, and has an H level voltage VH.
+, for example 5, indicates an inactive state, and an L level voltage VL1%, for example Ov, indicates an active state.

Further, the video signal 3v has an H level voltage V H 2 , for example -0. When the voltage is 9V, a white image is shown, and when the voltage is L level VL2, for example, -1.75V, a black image is not shown. That is, the synchronization signal sh is a signal that changes between 5V and Ov, and the video signal Sv is a signal that changes between -0.9V and -1.75V.
This is a signal that changes between Figure 4 (C
) is obtained.

To explain specifically, the H level voltage M of the synchronization signal sh
It is set so that when HI and the H-level voltage VH2 of the video signal 3v are added, the H-level voltage VH of the composite signal SC is obtained. Similarly, synchronization signal sh
It is set so that the reference voltage VM of the composite signal SC is obtained by adding the H level voltage VH of the video signal Sv and the L level voltage VL2 of the video signal Sv. In addition, the L level voltage VL+ of the synchronization signal sh and the video signal 3v
The L-level voltage VL of the composite signal SC is obtained by adding the L-level voltage VL2 of the composite signal SC. This composite signal Sc f) H rehe) Lt
(1) The potential difference between the Tl pressure VH and M*IfJIVu is set to, for example, 0.7V, and the potential difference between the reference voltage VM and the L-level voltage VL is set to, for example, 0.3V.

(Problem to be solved by the invention) However, as is clear from FIG.
When the H level voltage VH+ of the video signal 3v and the L level voltage VL2 of the video signal 3v are added, that is, when the maximum voltage VH+ and the minimum voltage VL2 of both signals are added, the reference of the composite signal 3c is obtained. The voltage is set to be VM. Therefore, if the I'' level voltage VH1 of the synchronizing signal sh or the L level voltage L2 of the video signal 3v fluctuates, mutual interference may occur, so it is necessary to stably amplify these video signals 3v and the synchronizing signal sh. There was a problem.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a signal amplification circuit that can independently and stably amplify a plurality of types of signals.

[Structure of the Invention] <<Means for Solving the Problems>> A signal amplification circuit provided by the present invention to achieve the above object has a first digital signal having a first amplitude and a second amplitude. a spoofing amplifier comprising an input terminal for inputting a second signal having a second signal, level setting means for setting the input terminal to a virtual ground level, and feeding back an output signal from the operational amplifier to the input terminal. means of return,
a first setting means for setting the amplitude of a first signal output from the operational amplifier in accordance with the feedback means; and a first setting means for setting the amplitude of a second signal output from the operational amplifier to the feedback means. and a second setting means for setting correspondingly.

<<Operation>> The present invention inputs the first signal and the second signal to the input terminal of the operational amplifier circuit. This first signal number, for example, the ground level which is the reference level or a level similar to this,
The amplitude changes between the first level and the first level, which is higher than this reference level. Further, the amplitude of the second signal changes, for example, between a reference level and a second level smaller than this reference level. By setting the input terminals to which such first and second signals are inputted to the virtual ground level, both signals can be stably amplified.

At this time, the amplification of the first signal output from the operational amplifier is set according to, for example, the resistance ratio between the feedback means and the first setting means, and the amplification of the second signal is set between the feedback means and the second setting means. It is set depending on, for example, the resistance ratio. Therefore, the amplification of both signals output from the amplifier amplifier can be set independently.

(Example) Hereinafter, Ichiji/AiV/4 according to the present invention will be explained in detail with reference to the drawings.

First, with reference to FIG. 2, the overall configuration of an image information storage/retrieval device as an information processing device to which the present invention is applied will be explained.

The image scanner device 1 has a reading section configured with a COD image sensor or the like, and reads the contents written on a manuscript such as a photograph or a manuscript as image data. This image scanner device 1 includes an operation unit 3 for setting parameters such as the document size, document density, and reading density of a document to be read, a memory (not shown) for storing these set parameters, and an image scanner. A CPU (not shown) for performing liljtll of the entire scanner device 1, input information such as setting conditions, and processing vI
a display unit 5 for displaying the time interval, and an automatic paper feed mechanism (ADF>7) for continuously conveying the originals placed on a document tray (not shown) to the reading unit and reading the originals. I'm ready.

The control unit (CPU) i has a DMA 13, a main memory 51, and a buffer 7 memory 53 via a system bus 2o.
a1 page memory 53 b1 code/image converter 71
, display memory 73, lPLJ90 and GODEC95
etc. are connected.

Also l. The IJ control section 11 includes a buffer 7 memory 53a1 page memory 53b1 code/image converting section 71, an H memo') via an image bus 40 for transmitting image information.
7 3, [ P LI9 0 33 J; Tj C
, ODEC 95, etc. are connected to each other.

This control unit 11 controls the overall operation and data flow of the information processing device via the system bus 2o or the image bus 40.

Further, a keyboard 101 and a mouse 103 are connected to the control unit 11 via an interface circuit 11a. The keyboard 101, mouse 103, etc. constitute a data input device @100, and the display device 77 is used, for example, to input character information when creating a fortune telling using a word processor function, or to perform searches and image processing.
Enter search information, ladder command information, array format, etc. for moving the cursor displayed on the display screen and switching various functions.

DMA (DIRECT MEMORY ACCESS)
S) 13 is connected to a storage device 30 formed from a magnetic disk device 31 and an optical disk VA storage 33 via an interface circuit 13a;
For example, the interface circuit 1 transfers data between the buffer 7 memory 53a and the storage device 30 regardless of the operation of the interface circuit 1.
3a.

The magnetic disk device 31 stores search information such as information for specifying desired art information from among a large amount of image information.

The optical disk device 33 stores the above-mentioned large number of image information and search information corresponding to each image information.

The main memory 51 stores the operating program of the above-mentioned ill III section 11 and the like.

The buffer memory 53a has a storage capacity of, for example, 128 kilobytes, and sequentially stores code data whose redundancy has been compressed by the CODEC95. Also, Batsufu 7
The memory 53a is equipped with a counter for counting the number of stored data, and when the amount of stored data based on the count value of this counter reaches, for example, more than half of the storage capacity, that is, code data of 64 kilobytes or more is detected. When stored, this 64 kilobyte data is sent word by word to the optical disk device 33 via the system bus 20 and the interface circuit 13a.

The page memory 53b stores, for example, a number of A4 size documents.
It has a storage capacity that can accommodate 0 pages, and temporarily stores image information input from the image scanner device 1 or image information retrieved from the optical disc 1a 33.

For example, the code/image converter 71 converts the keyboard 10
The character code data inputted from 1 is converted into image data and output to the display memory 73. Further, the code/image converting section 71 performs reverse conversion and correction of characters converted into image data on the display screen by converting Zunawa image data into character code data as necessary.

The display memory 73 is a memory for temporarily storing image information, and when displaying uniformity based on the image information from the page memory 53b on the display device 77, this image information is temporarily stored. do.

The display system III 1 section 75 controls the drive of the display device 77 and the like, and controls the display of image information stored in the display memory 73.

In addition, the display system part 75 is a communication system fill device 99 which will be described later.
When a composite signal is input through the composite signal, the original signal, that is, a video signal consisting of a gage digital signal and a synchronization signal are extracted from the composite signal and sent to the display device 77.

The display device 77 performs a display operation based on the video signal in synchronization with the synchronization signal.

The CODEC 95 is an encoding/decoding circuit unit that reduces the size of image information, that is, reduces the redundancy, thereby saving the storage area of a storage medium such as an optical disk used during registration. can. Also GODEC95
The compressed image information is decompressed, that is, the reduced redundancy is restored to its original value, and the image information is output as the original image information.

This CODEC95 has an IPU (IMAGEPR
OCESS [NG UNIT) 90 is connected. This IPLJ 90 has built-in an enlargement/reduction section 91 for enlarging and reducing image information and an aspect/horizontal conversion section 93 for rotating image information.

Further, the enlarging/reducing section 91 has a reduction processing means for directly reducing the image information read by the image scanner device 1. This reduction processing means has a built-in product-sum operation circuit, and reduces each piece of data to be reduced, which consists of a predetermined number of bits in which black bits or white bits are arranged in a grid pattern in the X-axis direction and the Y-axis direction. Execute the process. That is, point bits are set for performing weight calculation of reduction processing for each data to be reduced. Next, setting the value of the point bit to ``1'', calculate the product of the value of this point bit of ``1'' and the reciprocal of the distance to the black bit that exists around the point bit, and then The total sum of these products is computed by the product-sum calculation circuit. The value calculated by this product-sum calculation circuit is compared with a predetermined reference value by a comparison circuit. This comparison circuit outputs a signal corresponding to one bit of a pixel obtained by reducing the data to be reduced.

Note that the processing of such a reduction processing means may be configured to be executed based on a control program stored in the main memory 51, for example.

Further, the value of the reduction ratio directly reduced by the reduction processing means can be specified to an appropriate value using a management table stored in the main memory 51 or the like or the data input device 100.

Further, input/output devices such as an image scanner Vt station 1 and a printer 9 are connected to the interface circuit 95a.

The printer 9 is a device that prints out image information as visible information such as characters on a recording medium such as paper, and is, for example, a laser printer.

The communication control device 99 is connected to an external device and controls communication υ1 with the information storage and retrieval device. Communication system all device 9
9 has a composite signal generation circuit, which generates a composite signal by directly adding a plurality of signals inputted from an external device, for example, a video signal consisting of a digital signal and a synchronization signal, and generates a composite signal. The signal is sent to the display control section 75.

Next, let's take as an example a case where the image information storage and retrieval device to which the present invention is applied reads a large number of manuscripts, registers the image information written in the manuscripts, and further searches and prints them out according to the operating procedure. explain.

First, when registering 1' the read image information, read the original according to the instructions on the initial information processing screen displayed on the display screen of the display device 77, and then register the read image information in a predetermined optical disk drive@ 33 is inputted from the keyboard 101, and the image information storage and retrieval device is set to the "read/registration" mode.

Next, a large number of originals are stacked and placed on a predetermined position such as the original loading table of the image scanner device 1 constituting this image information storage and retrieval device, and a After setting the "Paper feeding" mode, information related to initial settings such as the document size, document density, and reading density of this document is input from the keyboard 101 or the operation unit 3 of the image scanner device 1.

Further, after the image information from the image scanner device 1 is temporarily stored in the page memory 53b, the buffer memory 53
The data is transferred to the optical disc device 33 via the interface circuit 13a and the interface circuit 13a, so that it can be registered in an optical disc (not shown) that is a storage medium of the optical device disc 33.

Next, use the keyboard 101 to register the title of the manuscript,
Search information such as information sheet and arrangement format is input according to the format displayed on the screen of the display device 77.

This type 8 is used to input and set items such as search keys to specify the original to be registered and facilitate the search process, and is used to input and set items such as search keys to specify the original to be registered and to facilitate the search process. a table for inputting various information such as the remaining capacity of the computer, key items for the search, and the keyboard 101.
The function of this function key is displayed when inputting using the function keys configured in the following.

When reading the document starts, the image information read from the image scanner device 1 is sent to the interface circuit 95a.
The data is temporarily stored in the page memory 53b via the page memory 53b.

After the image information is compressed by the CODEC 95, the search information is registered in the magnetic disk drive 31 via the buffer 7 memory 53a and the interface circuit 13a, and the search information and image information are stored in the optical disk drive N33. will be registered to.

When searching for specific image information from a large amount of image information registered in the optical disk device 33 and printing out or displaying the searched image information on the display device 77, the same steps as in the case of reading and registering described above are performed. Enter a search command using the keyboard 101 and press "Search"
Change the mode.

Next, use the keyboard 101 to input search information for specifying desired image information, select the desired search information from among the large number of search information stored in the magnetic disk device 31, and select the search information for the selected image information. The desired image information registered in the optical disc device 33 is searched based on the information.

The image information retrieved in this way is
3 to the CODEC 95 via the interface circuit 13a and the buffer memory 53a.

The CODEC 95 restores the retrieved image information by processing such as expansion, and displays it on the display device 77 via the display memory 73 or the like.

Further, when making a hard copy of the displayed image information, the user uses the keyboard 101 to designate the image information for which a hard copy is desired, sets the number of copies to be output, etc., and prints out from the printer 9.

Next, the component signal generation circuit built into the communication system II device 99 will be explained.

First, to explain the configuration with reference to FIG. 1, the first signal, synchronous signal @Sh, is connected to a C-MOS (METAL
The signal is generated by a synchronizing signal generating circuit using an OXIDE SEMICONDUCTOR, and is input to the inverting input terminal P1 of the reductive amplifier OP via a resistor R1.

As shown in FIG. 3, this synchronization signal sh is a reference level EL of the ground level or a level close to this + for example, O
v and a first level E greater than this reference level ELI.
The amplitude changes between H+ and, for example, 5V. Further, when the synchronization signal sh is at the reference level EL+, it indicates an inactive state, and when it is at a level EH+, it indicates an active state.

Referring again to Figure 1, the ground and the specified DC power supply,
For example, resistors R5 and R6 are connected in series between -5V and -5V. The connection point between these resistors R5 and R6 is the resistor R
7 to the inverting input terminal P1 of the τ amplifier OP. Also, the connection point between low resistance R5 and R6 is not shown.
CLI (EMITTER CUPLED LOGI)
C>, and the video signal 3v is input to the inverting input terminal P1 of the operational amplifier OP via the resistor R7.

The second signal, the video signal 3v, has a reference level E H 2 , for example -0.0 as shown in FIG. 9V and a second level EL2 smaller than this reference level EH2, for example -1.75V, the "c amplitude changes. When the video signal Sv is at the reference level EH2, the image shows black, and at level EL2, the "c" amplitude changes. In some cases, the image is shown as white.

Referring again to FIG. 1, a resistor R2 is connected between the inverting input terminal P1 of the operational amplifier OP and a predetermined DC power supply, for example, +5V. Furthermore, the non-inverting input terminal P2 of the Korean amplifier OP is connected to ground.

Here, the input impedance of the operational amplifier OP is infinite, and since the non-inverting input terminal P2 is connected to the ground, no current flows into the inverting input terminal P1 from other sources, and it is set to a so-called imaginary short, that is, a virtual ground level. Ru.

The output terminal P3 of the performance amplifier OP is connected back to the inverting input terminal P1 via a resistor R3. That is, resistance R3
is a feedback means for feeding back the output signal outputted from the operational amplifier OP to the inverting input terminal P1. Further, the output terminal P3 of the operational amplifier OP is connected to the resistor R4, and the composite signal SC, which is the output signal of the operational amplifier OP, is connected to the resistor R4.
It is sent to an external device (not shown) via LR4. The operational amplifier OP is used as a so-called inverting amplifier, and the synchronizing signal sh input to the operational amplifier OP is amplified by the ratio of the resistors R1 and R3, that is, the amplification factor -R3/R1.

Similarly, the video signal 3v input to the operational amplifier OP is amplified by the ratio of the resistors R7 and R3, that is, the amplification factor -R3/R7.

Next, the operation will be explained with reference to FIG.

Since the non-inverting input terminal P2 of the performance amplifier OP is connected to the ground, the inverting input terminal P1, which has the same potential as the non-inverting input terminal P2, is set to the ground level, that is, O■. Therefore, the synchronizing signal 3h and the video signal 3v input to the inverting input terminal P1 are inverted and amplified independently, without interfering with each other. That is, the synchronization signal sh is amplified by the amplification degree -R3/R1, and the video signal 3v
is amplified by the amplification degree -R3/R7. The synchronizing signal sh and the video signal Sv, which have been inverted and amplified in this way, are added,
A composite signal Sc as shown in FIG. 3(C) is obtained.

For example, in period T1, the synchronous signal @Sh is at the reference level EL+
When the synchronization signal sh at the reference level EL+ and the video signal SV are inverted and amplified as described above and added, the reference level Ell as shown in FIG. 3(C) 1 is obtained.
A composite signal is obtained that varies between the levels EH and EH. Specifically, when the synchronization signal sh of the reference level EL+ and the video signal 3v of the reference level EH2 are inverted and amplified and tampered with, the composite signal SC of the reference level EJ14 is obtained.

As described above, the reference level synchronization signal sh and the reference level video signal 3v are inverted and amplified and added together to obtain the reference level composite signal Sc, so that the synchronization signal sh and the video signal 3v are mutually Stable amplification without interference.

In addition, the synchronization signal sh of the reference level EL+ and the level EL2
When the video signals Sv and Sv are respectively inverted and amplified and processed, a composite signal SC of level EX is obtained.

At this time, the potential difference between the reference level EM and the level EH is set to be, for example, 0.7V. Therefore, when the composite signal 3c is at the level EH, the image is white, and when it is at the reference level EM, the image is black.

Furthermore, in period ■2, the synchronization signal sh is at level EH+,
The video signal @Sv is at the reference level EH2. When both such signals are inverted and amplified and amplified, the result shown in Fig. 3 (C
) is obtained as a composite signal Sc of level EL. At this time, the potential difference between the level EL and the reference level EM is set to be, for example, 03V. Therefore, when the composite signal Sc is at level E, it indicates that the synchronization signal is in the active state.

As described above, the synchronous signal @Sh generated by the circuit section using C-MOS and the video signal 3V generated by the circuit section using ECL are directly added to produce a composite signal S.
You can get c@. The present invention is not limited thereto, but can be applied to any suitable device, such as TTL (TRA).
NS ISTORTRANSISTOR LOGIC
) etc. can be applied to the case where various signals generated by a circuit section are inverted, amplified, and added.

[Effect of the Invention 1] As explained above, according to the present invention, the first signal that changes between the reference level, which is the ground level or a level close to this, and the first level, and the first signal that changes between the reference level and the second level, When inverting and amplifying the second signal that changes between the level and the second signal, the input terminals of the operational amplifier to which the first and second signals are input are set to the virtual ground level. Signals can be amplified independently and stably.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment according to the present invention, and FIG. 2 is a circuit diagram of an embodiment of the present invention.
FIG. 3 is a diagram showing the configuration of an information processing apparatus to which the embodiment shown in the figure is applied, FIG. 3 is a signal waveform diagram of each part of FIG. 1, and FIG. OP... stage amplifier R1. R3. R7...Resistor P1...Inverting input terminal P2...Non-inverting input terminal

Claims (1)

[Claims] An operational amplifier comprising an input terminal for inputting a first digital signal having a first amplitude and a second signal having a second amplitude, the input terminal being connected to a virtual ground. level setting means for setting a level, feedback means for feeding back an output signal from the operational amplifier to the input terminal, and setting an amplitude of a first signal output from the operational amplifier in accordance with the feedback means. A signal amplification circuit comprising: a first setting means; and a second setting means for setting the amplitude of a second signal output from the operational amplifier in correspondence with the feedback means.