JPH02237224A - Parallel/serial conversion circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption and cost without damaging a processing speed by installing an ECL(emitter coupled logic) type circuit and a TTL (transistor transistor logic) type circuit. CONSTITUTION:Respective conversion circuits 21a-21d consist of TTL type logical gates and a conversion circuit 25 consists of an ECL type logical gate. The conversion circuits 21a-21d convert parallel data PD of 16 bits into parallel data PE 0-PE 3 of four bits and a conversion circuit 23 converts parallel data PE 0-PE 3 in TTL type logical level into parallel data PE0-PE 3 of four bits in an ECL logical level. Then, the conversion circuit 25 converts parallel data PF 0-PF 3 into serial data at a high speed. Thus, power consumption and cost can be reduced without damaging the processing speed.

Description

[Detailed description of the invention] [Object of the invention] (Industrial application field) The present invention provides an ECL (ECL) with extremely small signal propagation delay time.
The present invention relates to a parallel-to-serial conversion circuit for converting parallel data into serial data at high speed using an EMITTER COUPLED LOGIC.

(Prior art) In recent years, in order to convert parallel data consisting of multiple bits into serial data at high speed, a parallel-to-serial conversion circuit using logic gates in an ECL type circuit format with extremely small signal propagation delay time has been proposed. has been done.

Such a conventional parallel-to-serial conversion circuit is, for example, TTL (TRANSISTOR TRANSIST).
After converting 16-bit parallel data consisting of OR LOGIC type logic level to ECL type logic level, convert this 16-bit parallel data to serial data using a logic gate with ECL type circuit type. I have to.

Such a conventional parallel-to-serial conversion circuit will be explained in detail with reference to FIG.

In the conventional example shown in FIG. 8, 16-bit parallel data PD (
PDO, PDI, PD2,... PD15) as ECL
This figure shows the case of converting to serial data using a logic gate circuit format.

First, among the 16-bit parallel data PD, 4-bit parallel data is sequentially transferred to the conversion circuits 101, 10'3,
105 and 107. Each conversion circuit 101, ~
107 converts input 4-bit parallel data of TTL type logic level into 4-bit parallel data of ECL type logic level.

Subsequently, shift registers 111, 113, 115, and 117 each configured using an ECL logic gate circuit format convert the input 4-bit parallel data into serial data at high speed.

(Problems to be Solved by the Invention) ECL type logic gates have an extremely small signal propagation delay time and can operate at high speed, but have the drawbacks of high power consumption and high cost.

Therefore, as mentioned above, in order to convert 16-bit parallel data to serial data, it is necessary to use a large number of ECL type logic gates, which has the problem of increasing power consumption and cost as a whole. Ta.

The present invention has been made in view of the above-mentioned problems, and it is possible to reduce power consumption and cost, and to convert parallel data into serial data at high speed.
The purpose is to provide a serial conversion circuit.

[Structure of the Invention] (Means for Solving the Problems) A parallel method provided by the present invention to achieve the above object.
The serial conversion circuit is composed of a TTL type logic circuit, and includes a first conversion means for converting multiple bits of parallel data into multiple bits of parallel data having a smaller number of bits, and a TTL type output from the first conversion means. a second converting means for converting parallel data of the form into parallel data of the ECL type; and a third converting means configured of an ECL type logic circuit and converting the parallel data outputted from the second converting means into serial data. and converting means.

(Operation) When converting multiple bits of parallel data into serial data, the present invention first converts multiple bits of parallel data at a TTL type logic level into multiple bits of parallel data having a smaller number of bits. Next, this TTL
Converts multi-bit parallel data at the logic level of the ECL format into parallel data at the logic level of the ECL format. Subsequently, this ECL type logic level parallel data is converted into ECL type logic level serial data at high speed.

Therefore, the number of ECL type logic gates can be reduced. This reduces power consumption and costs without reducing processing speed.

(Embodiment) An embodiment of the present invention will be described in detail below with reference to the drawings.

First, the overall configuration of an image information storage and retrieval device as an information processing device to which the present invention is applied will be explained with reference to FIG.

The image scanner device 1 has a reading section configured with a CCD image sensor or the like, and reads the contents written on a manuscript such as a photograph or a document as image data.

The image scanner device W1 includes an operation section 3 for setting parameters such as the document size, document density, and reading density of the document to be read, a memory (not shown) for storing these set parameters, and an image scanner. CP (not shown) for controlling the entire scanner device 1
U, a display unit 5 for displaying input information such as setting conditions and processing time, and a display unit 5 for continuously conveying originals placed on an unillustrated original table to a reading unit for reading the originals. It is equipped with an automatic paper feed mechanism (ADF) 7.

The image scanner device 1 also has a parallel-serial conversion circuit for converting parallel data into serial data, and converts the image data consisting of the read parallel data into serial data and converts it into CODEC 95 (described later).
Send to.

The control unit (CPU) 11 includes a DMA 1B, a main memory 51, and a buffer memory 53a via a system bus 2o.
1 page memory 53b1 code/image converter 71,
A display memory 73, an IPU 90, a CODEC 95, and the like are connected to each other.

The control unit 11 also includes an image bus 4 for transmitting image information.
0 through buffer memory 53a1 page memory 53b
1 code/image converter 71, display memory 73, IP
U90 o. Jl. and CODEC 95, etc. are connected to each other.

This control unit 11 controls the overall operation and data flow of the information processing device via the system bus 20 or the image bus 40.

Further, a keyboard 101 and a mouse 103 are connected to the control unit 11 via an interface circuit 11a. The keyboard 101 and mouse 103 constitute a data input device 100. For example, the display device 77 is used when inputting character information when creating a document using a word processing function, or when performing a search or image processing.
Enter search information, various commanded information, array format, etc. for moving the cursor displayed on the display screen and switching various functions.

DMA (DIRECT MEMORY ACCESS)
S) 13 is connected to a storage device 30 formed from a magnetic disk device 31 and an optical disk device 33 via an interface circuit 13a, and for example, the buffer memory 53a and the storage device 30 can be connected to each other regardless of the operation of the control unit 11. The data between the two is transferred via the interface circuit 13a.

The magnetic disk device 31 stores search information such as information for specifying desired image information from among a large amount of image information.

The optical disk device 33 stores the above-mentioned large number of image information and search information corresponding to each image information.

The main memory 51 stores the operation program for the control section 11 described above.

The buffer memory 53a has a storage capacity of, for example, 128 kilobytes, and sequentially stores code data whose redundancy has been compressed by the CODEC95. Further, the buffer memory 53a is provided with a counter for counting the amount of stored data, and when the amount of stored data based on the count value of this counter reaches, for example, more than half of the storage capacity, that is, 64 kilobytes or more. When storing the code data, this 64 kilobyte data is sent to the optical disk device 33 in units of words via the system bus 20 and the interface circuit 13a.

For example, the page memory 53b stores a number of pages for an A4 size document.
It has a storage capacity that can accommodate 0 pages, and temporarily stores image information input from the image scanner device 1 or image information retrieved from the optical disk device 33.

For example, the code/image converter 71 converts the keyboard 10
The character code data inputted from 1 is converted into image data and output to the display memory 73. Further, the code/image converter 71 performs reverse conversion, that is, converts image data into character code data, as necessary, to correct characters converted into image data on the display screen.

The display memory 73 is a memory for temporarily storing image information, and temporarily stores this image information when displaying an image on the display device 77 based on the image information from the page memory 53b.

The display control unit 75 controls the drive of the display device 77 and the like, and controls the display of image information stored in the display memory 73.

The CODEC 95 is an encoding/decoding circuit unit, and can reduce the storage area of a storage medium such as an optical disk used at the time of registration by compressing image information, that is, by reducing redundancy. Also CODEC95
The compressed image information is decompressed, that is, the reduced redundancy is restored to its original value, and the image information is output as the original image information.

This CODEC95 has an IPU (IMAGEPROC
ESS ING UNIT) 90 is connected.

This IPU 90 incorporates an enlargement/reduction section 91 for enlarging and reducing image information and an aspect/horizontal conversion section 93 for rotating image information.

Further, the enlarging/reducing section 91 has a reduction processing means for directly reducing the image information read by the image scanner device 1. This reduction processing means has a built-in product-sum calculation circuit, and performs reduction processing for each data to be reduced, which consists of a predetermined number of bits in which black bits or white bits are arranged in a grid pattern in the X-axis direction and the Y-axis direction. Execute. That is, point bits are set for performing weight calculation for reduction processing for each data to be reduced. Next, set the value of the point bit to "1",
The product of the value "1" of this point bit and the reciprocal of the distance to the black bits surrounding the point bit is calculated, and the sum of these products is calculated by the product-sum calculation circuit. I try to do that. The value calculated by this product-sum calculation circuit is compared with a predetermined reference value by a comparison circuit. This comparison circuit outputs a signal corresponding to one bit of a pixel obtained by reducing the data to be reduced.

Note that the processing of such a reduction processing means may be configured to be executed based on a control program stored in the main memory 51, for example.

Further, the value of the reduction ratio directly reduced by the reduction processing means can be specified as an appropriate value using a management table stored in the main memory 51 or the like or the data input device 100.

Further, input/output devices such as the image scanner device 1 and the printer 9 are connected to the interface circuit 95a.

The printer 9 is a device that prints out image information as visible information such as characters on a recording medium such as paper, and is, for example, a laser printer.

Next, an explanation will be given of the operating procedure using an example in which an image information storage and retrieval device to which the present invention is applied reads a large number of manuscripts, registers the image information written in the manuscripts, and further searches and prints them out. .

First, when registering the read image information, read the original and transfer the read image information to the predetermined optical disk device 33 according to the instructions on the initial information processing screen displayed on the display screen of the display device 77. A command or the like for continuous registration is input from the keyboard 101, and the image information storage and retrieval device is set in the "read/registration" mode.

Next, a large number of originals are stacked and placed on a predetermined position such as the original table of the image scanner device 1 constituting this image information storage and retrieval device, and an "automatic paper feeder" is installed to continuously read the originals. ” mode, information related to initial settings such as the document size, document density, and reading density of this document is input from the keyboard 101 or the operation unit 3 of the image scanner device 1.

Further, after the image information from the image scanner device 1 is temporarily stored in the page memory 53b, the buffer memory 53
The data is transferred to the optical disc device 33 via the interface circuit 13a and the interface circuit 13a, so that it can be registered in an optical disc (not shown) that is a storage medium of the optical device disc 33.

Next, use the keyboard 101 to register the title of the manuscript,
Search information such as information amount and arrangement format is input according to the format displayed on the screen of display device 77.

This format is used to input and set items such as search keys to specify the document to be registered and facilitate the search process, and includes information such as the remaining capacity of the storage device 30 when the image scanner device 1 reads the document. A table for inputting various information and key items for the search, and a keyboard 101
The function of this function key is displayed when inputting using the function key configured in .

When reading the document starts, the image information read from the image scanner device 1 is sent to the interface circuit 95a.
The data is temporarily stored in the page memory 53b via the page memory 53b.

Subsequently, after the image information is compressed by the CODEC 95, the search information is registered in the magnetic disk device 31 via the buffer memory 53a and the interface circuit 13a, and the search information and image information are registered in the optical disk device 33. Ru.

When searching for specific image information from a large amount of image information registered in the optical disk device 33 and printing out or displaying the searched image information on the display device 77, the same steps as in the case of reading and registering described above are performed. Enter a search command using the keyboard 101 and press "Search"
Set to mode.

Next, use the keyboard 101 to input search information for specifying desired image information, select the desired search information from among the large number of search information stored in the magnetic disk device 31, and select the search information for the selected image information. The desired image information registered in the optical disc device 33 is searched based on the information.

The image information retrieved in this way is stored in the optical disc device 3.
3 to the CODEC 95 via the interface circuit 13a and the buffer memory 53a.

The CODEC 95 restores the retrieved image information by processing such as expansion, and displays it on the display device 77 via the display memory 73 or the like.

Further, when making a hard copy of the displayed image information, the user uses the keyboard 101 to designate the image information for which a hard copy is desired, sets the number of copies to be output, etc., and prints out 1 from the printer 9.

Next, the parallel-to-serial conversion circuit built into the image scanner device 1 will be explained.

First, the circuit configuration for generating output pulses and load pulses will be explained with reference to FIGS. 3 and 4.

A reference pulse CL having a predetermined period T1, for example, 200 MHz is applied to each clock input terminal of the D-type flip-flop circuits 1, 3, and 5. Each of these flip-flop circuits 1, 3.5 is constituted by an ECL type logic gate.

An output terminal Qa of the flip-flop circuit 1 is connected to each input terminal D of the flip-flop circuits 3 and 5. Further, the output terminal Qd of the flip-flop circuit 3 is connected to the input terminal D of the flip-flop circuit 1, and the output pulse PSd from the flip-flop circuit 3 is applied to the input terminal D of the flip-flop circuit 1. As a result, the flip-flop circuit 3 outputs a pulse obtained by dividing the reference pulse CL by 1/4, that is, an output pulse PSc of 50 MHz from the output terminal Qc.

The flip-flop circuit 5 delays the phase of the output pulse PSa from the flip-flop circuit 1 by one period of the reference pulse CL, and outputs the delayed output pulse PSa. The output terminal Qe of this flip-flop circuit 5 and the output terminal Qa of the flip-flop circuit 1 are connected, so-called wire FOR (WI
RED OR) is formed. As a result, from the output terminal Qe of the flip-flop circuit 5, as shown in the truth table of FIG.
When both outputs are at L level, an output at H level can be obtained. Therefore, as will be explained in detail later, a load pulse PSe is output from the output terminal Qe of the flip-flop circuit 5.
That is, a negative pulse having a pulse width corresponding to one period of the reference pulse CL can be extracted every four times the period of the reference pulse CL.

The circuit configuration shown in FIG. 4 is similar to the circuit configuration shown in FIG. 3, with the flip-flop circuit 11 corresponding to the flip-flop circuit 1 and the flip-flop circuit 15 corresponding to the flip-flop circuit 5. Further, an output pulse PSc of 50 MHz outputted from the flip-flop circuit 3 is applied to each clock input terminal of the flip-flop circuit 11.15. Therefore, the circuit section shown in FIG.
Using the output Hals PSc of 0 MHz as a reference pulse, a pulse obtained by dividing this reference pulse into 1/4, that is, an output pulse PSg of 12.5 MHz, is output from the output terminal Qd of the flip-flop circuit 15.

Further, the output terminal Qe of the flip-flop circuit 15 is connected to the output terminal Qb of the flip-flop circuit 11, and a load pulse PSf by this wire FOR is output.

The logic level output signal PSc of the ECL type shown above
, PSg and load pulse PSf are converted into TTL logic levels by a conversion circuit 17 shown in FIG. That is, output pulses PSc, PSg and load pulse PS
f is converted into output pulses PTc, PTg and load pulse PTf, respectively.

The output pulse PTc and load pulse PTf, which have been converted into TTL logic levels as described above, are applied to the circuit section shown in FIG. In FIG. 1, conversion circuits 21a, 21
Each of b, 21c, and 21d is constituted by a TTL type logic gate. In addition, 16-bit parallel data PD (PDI, PDI, PD2
, . . . PD15) are output. Of this 16-bit parallel data PD, 4-bit parallel data of I.sub.2 is respectively applied to conversion circuits 21a, 2lb, 21c, and 21d. Each of these conversion circuits 21a, 2lb, 21
c and 21d each convert input 4-bit parallel data into serial data. Therefore, the conversion circuit 21
a, 21b, 2 C and 21d are 16-bit parallel data PD and 4-bit parallel data PEO, P.
This constitutes a first conversion means for converting into EI, PE2, and PE3.

The conversion circuit 23 converts 4-bit parallel data PEO, PEI, PE2, PE3 of TTL logic level into 4-bit parallel data PFO, PFI of ECL logic level.
, PF2, PF3.

The conversion circuit 25 is supplied with the reference pulse CL and the load pulse PSe shown in FIG.
4-bit parallel data PFO, PFI, PF from
2, PF3 is given.

This conversion circuit 25 is composed of ECL type logic gates, and is a third conversion means for converting 4-bit parallel data PFO, PFI, PF2, PF3 of ECL type logic level into serial data. .

Next, the operation will be explained with reference to FIG.

When a reference pulse CL with a pulse width TO and a period T1 as shown in FIG. It operates at the timing of the rise of pulse CL.

Specifically, when the reference pulse CL rises from the L level to the H level at time t1, the flip-flop circuit 1 is inverted, the output terminal Qa falls from the H level to the L level, and at the same time, the output terminal Qb rises to the L level. It rises to H level. The output pulse PSa of this output terminal Qa is given to each input terminal D of the flip-flop circuit 3.5, and when the reference pulse CL rises from the L level to the H level at time t2, the flip-flop circuits 3 and 5 are inverted. do.

The output pulse PSd of the flip-flop circuit 3 is applied to the input terminal D of the flip-flop circuit 1, and when the reference pulse CL rises from the L level to the H level at time t3, the flip-flop circuit 1 is inverted.

Similarly, the flip-flop circuit 1 uses the reference pulse CL
7(B).
As shown in (C), a pulse having a pulse width corresponding to the period T2 is outputted every period T4, which is four times the period T1.

Further, from the output terminal Qc of the flip-flop circuit 3, as shown in FIG. 7(D), an output pulse PSc obtained by delaying the output pulse PSa by a time corresponding to the period T1 is sent out. Similarly, from each output terminal Qd of the flip-flop circuit 3.5, an output pulse PSb is output as shown in FIG. 7(E).
The output pulse P is delayed by a time corresponding to the period T1.
Sd is sent out.

Since the output terminal Qe of the flip-flop circuit 5 and the output terminal Qb of the flip-flop circuit 1 are connected,
As shown in FIG. 7(F), from the output terminal Qe, a load pulse PSe that is at the L level for a period corresponding to the pulse width T1 of the reference pulse CL is sent out every cycle T4.

The operation of the circuit section shown in FIG. 4 is also similar to that shown in FIG. circuit 15
is the 12.5MHz output pulse PSg from the output terminal Qd.
At the same time, a load pulse P is sent from the output terminal Qe.
Sf is sent.

ECL type logic level output pulse PS shown in 2 below.
c, PSg, and load pulse PSf are converted into TTL logic levels by the conversion circuit 17 in FIG. 5, and then sent to the circuit section in FIG. 1.

The conversion circuits 21a, 2lb, 21c and 21d convert the 6-bit 1.parallel data PD into 4-bit parallel data PEO, PEI, PE2, PE3. Next, the conversion circuit 23 converts the parallel data PEO, PEl, PE2, PE3 of 4 bits 1 to 1 of the TTL type logic level into ECL.
4-bit parallel data PFO consisting of a logic level of
Convert to PFI,, PF2, PF3. Next, conversion circuit 2
5 converts 4-bit parallel data PFO, PFI, PF2, and PF3 consisting of ECL logic levels into serial data at high speed.

As described above, the output terminal Qb of the flip-flop circuit 1,
By connecting the output terminal Qe of the phase flip-flop circuit 5 to form a so-called wired OR, a load pulse, that is, a pulse with a pulse width corresponding to one period of the reference Noculus, is generated every four times the period of the reference pulse. Therefore, the load pulse can be generated with a simple circuit configuration without causing so-called gate delay or the like.

[Effects of the Invention] As explained above, according to the present invention, when converting 16-bit parallel data to 4-bit parallel data in the first stage, processing is performed at a TTL type logic level,
In the next step, when converting the 4-bit parallel data into serial data, we processed it at high speed at the ECL logic level, reducing power consumption and cost without sacrificing processing speed. This can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a configuration diagram of an information processing device to which the embodiment of FIG. 1 is applied,
Figure 3 is a circuit diagram for dividing a 200 MHz reference pulse to generate a 50 MHz output pulse and load pulse, and Figure 4 is a circuit diagram for dividing a 200 MHz reference pulse to generate a 50 MHz output pulse and a load pulse. Figure 5 is a circuit diagram for converting an ECL type logic level to a TTL type logic level, and Figure 6 is a circuit diagram for generating a 12.5MHz output pulse and a load pulse. 7 is a pulse waveform diagram of each part of FIG. 1, and FIG. 8 is a circuit diagram showing a conventional example. 21a 2lb, 21c, 21d...first conversion circuit 23...second conversion circuit

Claims (1)

[Claims] A first converting means configured by a TTL type logic circuit and converting multi-bit parallel data into multi-bit parallel data having a smaller number of bits; a second conversion means for converting TTL type parallel data into ECL type parallel data; and a second conversion means configured by an ECL type logic circuit and converting the parallel data outputted from the second conversion means into serial data. 3. A parallel-to-serial conversion circuit comprising: 3 conversion means.