JPH02237252A - Transmission line encoding/decoding system - Google Patents

Abstract

PURPOSE:To prevent the '0' succession of a prescribed number without deteriorating the efficiency of a line by setting an overhead bit showing whether an all '0' slot exist in respective slots of one block or not. CONSTITUTION:The overhead bit showing whether the all '0' slot exists are set in respective blocks. When the all '0' slot exists, slot information showing whether or not respective slots are the all '0' slot is set in the block instead of the '0' bit of the prescribed all '0' slot, at least one of the '0' bit of the other all '0' slot is converted into '1' bit so as to execute encoding. Thus, the position of the all '0' slot is transmitted to a reception-side while the '0' bit succession can be suppressed, and the use efficiency of the line in data transmission is prevented from being deteriorated.

Description

[Detailed Description of the Invention] [Industrial Field of Application]
The present invention relates to a transmission path encoding/decoding method that prevents 0# from occurring more than a predetermined number in succession.

[Conventional technology]

In communication equipment that extracts timing information from digital data received from a transmission path and sets an operating clock based on this information. If the data from the transmission path contains consecutive 10''s, timing information cannot be extracted on the receiving side, so it may be necessary to limit the number of consecutive 0#s on the transmitting side.For example, AT & T Publica in the United States
In tion 6 2 4 1 1, the situation of continuous "0" is defined as follows.

(1) Do not transmit 16 or more consecutive bits of ``Q'' (2) 8 x ( n + 1
) The width of bits includes n bits or more of "1"' (n-1 to 23) Therefore. Conventionally, for example, LS manufactured by Rockwell I
IR8070 Application Note (Document} No. 2 9 3 0 0 N 2 3. Order No. 3 2 3 Septem-ber 1 9
The bit-7 stuff ink method shown in 86) was used to prevent consecutive ``0''. If all the data bits of are '0'. The above condition is satisfied by forcibly transmitting the seventh bit of the slot as "1". FIG. 15 is an explanatory diagram showing encoding using this bit-7 stuff ink. Figure 15 (.) shows the transmitted data before processing. FIG. 15(b) shows the transmission clock. FIG. 15(c) shows the transmission data sent to the transmission path after bit-7 stuff ink processing. The signal shown in FIG. 15(c) is transmitted at the rising edge of the transmitting clock shown in FIG. 15(b). Here, one slot consists of 8 bits. One frame consists of these 24 slots. A frame bit l-(F) is added to the beginning of each frame. In FIG. 15, the area from slot 23 to the beginning of slot 1 of the next frame is shown. As is clear from this Figure 15. Monitors transmission data in slot units before processing. If the bits that make up the entire slot, such as slot 23, have "1", the data should be transmitted as is. If all the bits making up the slot are @0# like slot 24. Bit stuff ink processing is performed to forcibly replace the 7th bit B7i of that slot with "1#" as shown in Fig. 15 (c).
), the above-mentioned "0" continuous restriction condition is satisfied.

[Problem to be solved by the invention]

As mentioned above, in the conventional transmission line encoding/decoding method. If all bits of a given slot are "0#", the sending side will forcibly replace all the specified bits with "1".
1 slot when the original data is all "0" and a predetermined 1 bit gold is replaced. When the original data originally had only a predetermined bit "1#", one slot becomes the same.The receiving side of this data cannot fully judge which data the original data is. As a result, there was a problem in that data errors occurred.Therefore, in order to realize transparent data transmission, it was necessary to leave one predetermined bit free for bit stuffing in each slot. The data transmission speed is lower than the transmission speed of the transmission line.For example, if one slot consists of 8 bits, the data transmission speed is limited to 7/8 of the transmission line speed.There is a problem that the line usage efficiency decreases. Ta.

This invention was made to solve all the problems mentioned above. A predetermined number of ゛′ without reducing line efficiency.
The purpose of this invention is to obtain a transmission path encoding/decoding method that can prevent 0'' continuation.

[Failure to solve the problem]

The transmission line encoding/decoding method according to this invention is as follows. All bits in multiple slot notes that make up one block are “0”
A head bit is set in the above block to indicate whether a slot (hereinafter referred to as "o" slot) exists or not. If all the above “0” slots exist, the “0” slots of all the predetermined 60” slots are
” Instead of bits, each slot in the above block is all 1
Set the slot information bit indicating whether it is a ``0'' slot or not, and set the 60'' bits of all remaining ``0'' slots to 61#.
Encode it by converting it to bits. Also, based on the overhead bit set at a predetermined position in one received block of a predetermined data length, it is determined whether or not there is an all "0" slot in which all bits are "0" in the block before encoding. If it is determined that all these “0” slots exist. In addition to extracting slot information bits indicating whether or not each slot in the received block is an all-0 slot, a predetermined all-0 slot out of the all-0 slots specified by this slot information bit is extracted. Insert one slot's worth of "o" bit into the position. The decoding is performed by restoring all the bits 1 bit 0 # of the slot corresponding to the other all "0" slot positions.

[Effect]

In this invention, an overhead bit indicates whether or not all 0'' slots exist in each slot of one block. If there are no all 0'' slots, the restriction is exceeded by using the data as it is. Transparent data transmission is possible without consecutive ``0'' bits. If all ``0'' slots exist, a predetermined number of all ``0'' slots out of all ``0'' slots will be transmitted.
In place of the "0" bit of the slot, a slot information bit indicating whether each slot in the block is an all-o' slot is set. Since the 10# bits in all 0# slots other than the predetermined all 0 slots are converted to 1 bits, this converted 1 bit prevents consecutive 0# bits exceeding the constraint. , and when decoding the slot information bits above, all “0” before encoding
Since the position of the slot is indicated and a complete all-zero slot is restored based on this, transparent data transmission can be achieved by leaving only one bit free for overhead bits in one block. is possible. High line usage efficiency can be obtained.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 shows the continuous 0
”, that is, ■ 16 bits or more must not have consecutive “0”s. ■ Satisfy the condition that at any time, n bits or more of ゜゛1# are included in the width of 8 × (n + 1) bits. This is a flowchart showing the processing procedure when encoding data to the transmission path as shown in FIG. This is an explanatory diagram showing the data structure during data encoding and decoding according to the procedure.In this embodiment, as shown in FIGS. 3(a) to (d).1
The frame. It consists of 1 frame bit F and 192 data bits. The data bit portion is made up of four blocks, and each block is made up of six slots, each slot containing eight bits.

The encoding processing procedure will be explained based on the flowchart shown in FIG. First, the data bit part of one frame is 48
The first bit in each block divided into bits, that is, bit 1 of slot 1, is set as an overhead bit (:x.f 7" (11). Next, slot 2
All bits in each slot from to slot 6 are '0'
” (step (2)). In this step (2), all 60# On slots are present.
If it is determined that there is no slot. Step (3
) At K, set the overhead bit i shown in FIG. 3(C) to "1". The other nobits form one block as they are.

As a result, slot 10 bits 2 to 8 are all "o"
Even if bit 1 is set to ``1#, all bits in slot 1 will not be 10#.Also, there are no slots with all bits ``0#'' in slots 2 to 6. This block will always have a ``1'' bit in each slot.゛0 above
``Since it satisfies the continuation restriction conditions and transmits most data bits as is, there is no reduction in line usage efficiency.

Also, if it is determined in step (2) that all "0" slots exist from slot 2 to slot 6. First, in step (4), the overhead bit I
The 5 bits following the overhead bits correspond to slot information bits indicating whether or not slots 2 to 6 before encoding are all ``0'' slots. Set the bit corresponding to a certain slot to 11”. Set the other bits to 10". Also, the last 2 bits of slot 1 following these 5 bits may be set to either "'1" or "0#. Set to either one. Next, the slot Set the first bit of 2, that is, the 8th bit from the overhead bit, to 1.Insert bits 2 to 8 of slot 1 before encoding into the subsequent γ bit.In this way, from slot 2 to at least one of slots 6
The two slots must be all ``'0'' slots or La.
．． ), -- Herhetz}"At least one of the 5 slot information bits following a hit will be "1", and slot 1 after encoding will not be all "0". Also, encoding Bit 1 of the second slot 2 is ″′1#
Therefore, even if bits 2 to 8 of slot 2 after encoding, that is, bits 2 to 8 of slot 10 before encoding, are all 60#, slot 2 after encoding will not be all "0".

Next, in step (5). Delete all ``0'' slots with the lowest number among all 10'' slots in the block. And a predetermined bit of each all "0" slot from the second onward is converted to "1".

Next, in step (6). From subsequent slot 3 to slot 6. One entire II O deleted in step (5)
One block is constructed by sequentially setting data in each slot except the I+ slot. When such encoding processing is performed for each block, encoding of one frame is completed from (C).

Figure 3(d) shows the block configuration after encoding when slot 3 and slot 5 in the block before encoding are all "0" slots.
0" slot exists. The overhead bit of slot 1 is set to "O", and the 5 bits following this bit indicate whether each slot from slot 2 to slot 6 is a full II O II slot. all"
'0'' bits corresponding to slot 3 and slot 5 in slot T6, i.e. bit 3 and bit 5 of slot 1 are 6
1''K. Slots that are not all "0" slots 2. Slot 4. Bits corresponding to slot 6. In other words, bits 1, 2, bit 4, and bit 6 of slot 1 are set to ``0''. Slot 1 before Karigo conversion (Figure 3 (C))
Bits 2 to 8 of are inserted into bits 2 to 8 of slot 2 after encoding (FIG. 3(d)). The first bit of slot 2 is set to "1". Furthermore, the data in slot 2 before encoding is inserted as is into slot 3 after encoding. Furthermore, slots 1-3, which are all "o" slots with the lowest number, are deleted. A predetermined bit among the eight "0" bits of slot 5, which is the second all...0# unit. In this example, the second bit is converted to "1", and slots }4.5.6 before encoding are set to slots 1-4.5.6 of the blocks after encoding. In other words, all “0” of the lowest number slot in the block is 8.
Instead of sending bits. Five of these bits are slot information bits corresponding to each slot in the block. This allows the receiving side to fully indicate whether or not each slot is an all-0 slot, and to restore all slots from all '0' to before encoding. Set at least 1 bit of the 8 bits ``On'' of all tl O # slots from the second to ``1'' to ``1''.
'' to completely suppress continuous ``0''''. In addition. The last two bits of slot 1 after encoding can be either ``1'' or ``0#''. Data bits other than all 'D' slots are sent sequentially, since the position of all '0' slots is indicated by the slot information bit sent in place of the first all '0' slot in the block.
Data transmission is performed without reducing efficiency. Slot 1 is the slot information bit. slot 2
is set as the first bit @1# bit. Also, of the total 60" slots from slot 3 to slot 6, all "0# slots from the second onwards are at the specified positions @
A ``1'' hit with a 0'' bit converted prevents it from becoming all ``0''. Continuation of the above @0#
It is possible to satisfy the restrictive conditions.

According to such encoding. While satisfying the restrictive conditions regarding consecutive "0"s. The overhead required for this in one frame is only 1 bit. For example, when comparing the above embodiment with the conventional bit stuffing method, the overhead can be reduced to 1/6.

Next, the decoding process procedure will be explained based on the flowchart in Figure 2. First, in step (7). The first bit in one received block (48 bits) is extracted as an overhead bit. In step (8), it is determined whether this overhead bit is "1" or "0". If this is ゜'1'', it means that there were no all 0# slots in the block before being encoded. In step (9), all other bits are configured as data bits in one block. Also, if the overhead bit is determined to be "0" in step (8). Indicates that there were all ``0#'' slots in the block before being encoded. -1 step followed by 5 bits '{5 as slot information bits corresponding to slots 2 to 6 respectively. Retrieval. Out of the slots corresponding to the bits set to "1", one slot's worth of "O" is inserted into the position of the lowest slot in the block, and the slot information bit is set to '1'. All bits in the second and subsequent slots among the slots set to "0" are set to 0.Next, in step U, the 8 bits following the overhead bits are deleted, and all bits other than the slots set to "0" are set to 0. slot.
In other words, decoding is performed by setting the data of a slot whose slot information bit is set to 1"O IH in the corresponding position. According to this type of decoding, "1" is The containing slot is sent as is, and among all @0# slots, a "0" bit is inserted in the appropriate position for the lowest numbered slot, and the second and subsequent slots are sent as is. By setting all bits to ``OJ'' bits, each can be accurately restored.

Also. FIG. 4 is a circuit diagram of an encoder showing an example of implementing the transmission line encoding method of the present invention using an electric circuit. FIG. 5 is a circuit diagram of the decoder.

In Figure 4. α7I is transmission data that undergoes transmission line encoding. (1m is a shift register circuit that shifts this transmission data (12 by 1 slot in 1 bit units). α knob is this shift register circuit (8-bit register circuit that stores the output of 13 in parallel in slot units. (15l is this All '0' slot determination circuit that determines whether all 8 bits output from register circuit Q41 are '0'. θ
G is all “0#” which assembles the output of the register circuit α into the frame configuration when there is no IT slot.
Frame configuration circuit without slot. Qη is a frame configuration circuit with all ``0# slots'' that is assembled into a frame configuration when there are 110 and 18 slots. 0″ frame configuration circuit without slot Oe
Or frame configuration circuit Ii with all ``'0'' slots
D Selector circuit that selects either output. (l9 is a parallel load shift register circuit that loads the output signal of this selector circuit QFQ into all blocks and sends it out as a serial signal. ■ is the encoded transmission data outputted from the parallel load shift register circuit αl. ( 2
υ is the bit clock, which is a clock in bits. Shea
is a slot clock, which is a clock for each slot. @
is a block clock output every 48 bits, which is a unit of code conversion. (Incorporated) is the output signal of the total to O H judgment circuit a. This signal indicates whether or not there is a slot in which all 8 bits are "o" in slots after slot 2 of each block.

Further, in FIG. 5, t2e is encoded reception data received from the transmission path. @ represents this received data (a) as 1
For blocks. In other words, a shift register circuit that shifts by 48 bits. (to) this shift register circuit (2'
A register circuit that takes in all 0 output blocks. 0l
takes the first bit of each block from the output of this register (c). All “0” slot presence/absence determination circuit that determines whether the block includes all “0” slots. (
) is the output signal of the all-0 slot presence/absence determination circuit (to) indicating the presence or absence of all "o" slots. 0η is the output signal of the all-0 slot presence/absence determination circuit (to) that is set following the overhead bit of the block when all "0" slots are present. Insert one slot's worth of "0" into the first all "o" slot position in the block based on the information bits. All bits of the slot corresponding to the second and subsequent all "0" slot positions are inserted into II O. I+
year. Furthermore, the ``0'' replacement circuit restores the data string before encoding by deleting the 8 bits following the overhead bits of the received block. A selector circuit that selects the output signal of either the register circuit (c) or the "0" substitution circuit C31) based on (to). ? 33 is a delay circuit that delays the block clock @ by several bits. C34
) is from the block clock @V via this delay circuit (to). Load all the output signals of the selector circuit 0 in block units. Parallel load shift register circuit that outputs at the timing of bit clock OD. C3S
is the decoded received data output from the parallel load shift register circuit (341).

FIG. 6 is a timing chart 1 showing all the timings of each signal in the encoder shown in FIG. 3, and (12b) is the transmission data (12a) expanded by one block. (c) is a frame pulse steal to show the boundary of 192 hits.

An encoder with this configuration. In the decoder. First, let me explain the encoding operation. In Figure 4. The transmission data 07J is converted into a parallel signal by the shift register circuit 13) and the register circuit (141) in slot units.The output of the register circuit I is all 8 bits.
0''' Frame configuration circuit without slot O6l, all ゜'0
``Frame configuration circuit with slots aη. All 0'' slot size circuit (injected into each of 15l. All ``0'' frame configuration circuit without slots (Ie. All shown in FIG. 2(c). As shown in the block configuration without a 0'' slot, the first bit of slot 1 is set to ``1''.Then, data bits are set in sequential slot units to configure the block.

On the other hand, all "O IT slots frame configuration circuit αη
teeth. As shown in the data structure of one block in the case of all "0" slots shown in Figure 3(d). First slot 1
The first bit 'e'' is set to 'O', and the bit 1ff of the second slot is set to '1'. Furthermore, the second slot of slot 1
All bits from bit to 6th correspond to slots 2 to 6, respectively. at these bit positions. All "O'"
``Based on the output signal of the slot determination circuit α9 (based on the 8 bits constituting each slot are all 60'', that is, if each slot is all ``0'' slots, then ``1'' i.
If not, set it to ``0''. Also, after slot 2, delete the first all ``0'' slots in the block, and from the second onward, set all ゛0# slots to 8. 2nd bit k” of bit “0”
1". Also, slots that are not all 60" slots.
The output of the register circuit (+41) is kept as it is, and one block is constructed by sequentially filling the output in the order of input.

The all '0' slot determination circuit a!il is a register circuit a4r for each slot after slot 2 of each block.
Determine whether or not all of the K stored 8-bit signals are ``D''. If there is at least one all Ilo# slot for slots after slot 2 in the block. The output (24) notifies the frame configuration circuit aη with all "0" slots and the selector circuit Nishiki to that effect.

In the selector circuit fil. Due to this total ゜'0# output signal e24) of the slot determination circuit α9. Determine whether or not there are slots that are all 'On' after slot 2 in the block. If there are no slots for all "o". Select the output of the frame configuration circuit (Ie) without all “0” slots. If there is a slot with all “0”, select the frame with all “0” slots. Select the output of the configuration circuit 0η. Parallel load shift register circuit Output to a1.

The parallel load shift register circuit 09 takes in all the output signals of the selector circuit aQ by the block clock (c). The encoded transmission signal ■ is output at the timing of the bit clock Cυ. The block clock (c) resets the output of the all 0# slot determination circuit a5l to prepare for the next block.

In this way, the encoder shown in Figure 4. Captures input transmission data in units of slots. Judgment as to whether or not all slots are all "0" is made by the all "0" slot determination circuit (l9). All 11Q# slotless frame configuration circuit aS and all "0" slotted frame configuration circuit θη Configure a block-based frame in each case.Then, the outputs of both frame configuration circuits oe and
A selector circuit (selected by IS) controlled by IS.
Parallel load shift register circuit Q' in block units
J, converts it into serial form, and outputs the entire encoded signal as transmission data Cυ.

Next, the decoding operation in the decoder shown in FIG. 5 will be explained. The received data (2[9'e) sent from the encoded transmission path is shifted to the shift register circuit (5) in 1-bit units. ) is the output of
It is sent to selector circuit 02 and “0” replacement circuit 0
υ, all "o" are sent to the slot presence determination circuit 01. The “0” replacement circuit t3υ is. For example, it decodes the encoded data when there are all 0# slots as shown in Figure 3(d).It decodes the encoded data from the second bit of slot 1 to the first bit of slot 2 of each pronoque. At the same time, the second to sixth bits of slot 1 are made to correspond to slots 2 to 6, respectively.
This is the slot corresponding to the bit set to "1". Insert all "0" bits for one slot into the first slot position. All the bits in the slot positions set to ``'1'''' are set to ``0'' bits, and the slot positions corresponding to the bits set to tlQll are filled with the same data to form one block. Please decrypt it.

on the other hand. The circuit (a) for determining the presence or absence of all “0” slots is as follows. Capture the first bit of each block. That block is all” o
” It is determined whether the slot is included or not. The result of the determination is notified to the selector circuit 02 as an output signal (to).

In selector circuit 07J. Based on this output signal (7). If the block does not have all ``0'' slots, the output signal from the register circuit (to). Also, if the block has all "0" slots, the "0" replacement circuit G
Select all decoded signals from υ.

And the output of this selector circuit 0. By parallel load shift register circuit (foundation). Block clock @
is captured with a delay of several bits. And do this at the timing of bit clock Qυ. Output the decoded received data as 0.

Like this. In the decoder shown in Fig. 5. Input received data (2 [9) is captured in units of all blocks. The captured signal is decoded by the ``0'' replacement circuit (3υ) assuming that there are all ``0'' slots. Then, the overhead bits at the beginning of the block are ffi. All "0" slots are taken into the presence/absence determination circuit. Determine whether all 10" slots in the block are present or absent. If not, output from the register circuit (to). If present, decoded. Select the output of “0” replacement circuit 0υ.This is an all-parallel load shift register circuit (
decoding is performed by capturing the data into a computer (product) and outputting it serially.

In addition. In the above embodiment, all head bits are placed at the beginning of a block of 48 bits as shown in FIGS. 3(c) and 3(d). It may also be placed in other locations within the block. For example, it may be placed at the 8th bit of K slot 5 as shown in FIGS. 7(C) and 7(d).

Also. In the above embodiment, all the first 10" slots in a block are deleted and slot information bits are set in the entire block instead. The second or last all "0" slots, etc. ``0'' slot may be deleted and slot information bits may be set in its place in the slot information bit block.
#Slot H - Shows the frame configuration when deleted.

Also. In the above embodiment, as shown in FIG.
Since then, it has been made to correspond to slot 6. For example, Fig. 9 (d
) as shown in the other bits I-'r slot 2 before encoding.
It is also possible to make it correspond to slot 6K.

Furthermore, in the above embodiment, as shown in FIG. 3(d), all 5 bits of the slot information bits that follow the overhead are made to correspond to each other on a one-to-one basis from slot 2 to slot 6. As shown in the example in Figure 10. All 0s are created from 25 5-bit binary codes (o.o, o.
2-1 chords excluding the o, o) chords and . Slots 2 to 6 are all in one-to-one correspondence with the combinations of states that are all ``'0'' slots or not. The code may be used as the slot information bit.

Also. In the above embodiment, as shown in FIGS. 3(c) and 3(d), at least one of the eight "0" bits of all II 0 37 slots from the second onwards is converted to "1". It is placed in the same position as the original slot. For example, this is shown in the example in Figure 11. For example, place it in the last slot position of the block. It may also be placed at other predetermined positions.

Also. In the above embodiment, one block is made up of 48 bits, or 6 slots, as shown in FIG. It goes without saying that the entire transmission line encoding/decoding method of the present invention can be applied to a block of 64 bits, that is, 8 slots as shown in FIG. 12. In this case. Since there are three blocks in one frame, there are three overhead bits in one frame. In the case of the above embodiment, even fewer overhead bits are required. As mentioned above “
θ″Continuity rule condition is satisfied.

Also, in the above example. As shown in step (2) in Figure 1, the encoding process is performed regardless of whether or not slot 1 is an all-0 slot, but this slot 1 is also the same as the other slots. Encoding may be performed by determining whether or not there are all 10'' slots, and FIG. 13 shows the data structure when slot 1 is all @0'' slots in this case.

Also. In the above embodiment, as shown in FIGS. 3(C) and (d), the bits corresponding to all 601 slots among the slot information bits are set to 61". As shown in FIG. 14, bits corresponding to all "0" slots are set to 61". Bit 1”o”. All “0”
#The bit corresponding to a slot that is not a slot may be set to "1".

However, in this case, it is necessary to fix the last two bits of the three bits following the fifth bit, that is, bit 8 of the first slot and bit 1 of the second slot, to 1.

Furthermore, in the above embodiment, the second bit of the ``0'' bits of all ``0'' slots is converted to a ``1'' bit.
The bits may be converted to ``'1# bits.Also, the positions of all the ``'0'' slots may be used to convert the bits to ``1# bits.
It is also possible to send some information using a code that always includes bits l-'{5, that is, a code that excludes values that are all "0#".In this case, the slot indicated by the slot information bit is also sent. By setting all @0# bits, the data before encoding is restored.

〔Effect of the invention〕

As described above, according to the present invention, in each block. All zero
In addition to setting all the overhead bits that indicate whether or not a ``slot'' exists, if all ``OH'' slots exist, each slot is set with all ``o'' slots instead of the @0# bit of the specified all ``0'' slots. In addition to setting slot information bits in all blocks to indicate whether or not there is a slot information bit, at least one of the ``0# bits of all other ``0'' slots is converted to all ``1'' bits and encoded. ．While conveying all "0" slot positions to the receiving side. ″′0″
It is possible to suppress the continuation of bits. Also, since the ``'θ'' bit is restored to all @0# slot positions based on the slot information bit, all ``0'' slots are accurately restored. This has the effect that line usage efficiency in data transmission does not decrease.

[Brief explanation of drawings]

FIG. 1 is a flowchart showing the encoding processing procedure according to an embodiment of the transmission line encoding/decoding method of the present invention. Figure 2 is a flowchart showing the decoding processing procedure.
FIG. 3 is an explanatory diagram showing the structure of data when data is encoded/decoded by these processing procedures. FIG. 4 is a circuit configuration diagram of an encoder showing an example of implementing the present invention using an electric circuit. Figure 5 is a circuit diagram of the decoder. Figure 6 is a time chart of each signal in the encoder of Figure 3. FIGS. 7 to 14 are explanatory diagrams showing data structures during data encoding/decoding according to other embodiments of the present invention, respectively. FIG. 15 is an explanatory diagram showing a data structure in a conventional transmission path encoding/decoding system. In the figure. 0z is the transmission data before encoding. 03l is a shift register circuit. (I41 is a register circuit. (15
1 is all “0#” slot determination circuit. aO is all “0” slotless frame configuration circuit. a”n is a frame configuration circuit with all “0” slots. a (to) is a selector circuit. 0
! J is a parallel load shift register circuit, and (A) is encoded transmission data. (b) is received data before decoding. @ is a shift register circuit. (to) is a register circuit. The wire is a circuit that determines the presence or absence of all “0” slots. I3υ is a “0” replacement circuit. G2ld: Selector circuit. (To) P is a delay circuit, and (B) is a parallel load shift register circuit. (c)
is the received data after decoding. Note that the same reference numerals in each figure indicate the same or equivalent parts.

Claims (2)

[Claims] (1) An overhead bit is set in the block that indicates whether or not there is an all-0 slot in which all bits are “0” among the plurality of slots constituting one block of a predetermined data length, and , if the all "0" slots are present, a slot information bit indicating the position of all "0" slots in the block is set at a predetermined position in the block instead of the predetermined all "0" slots, and A transmission line encoding method characterized by converting all "0" slots of 2 to slots having "1" bits. (2) Determine whether or not all “0” slots existed in the block before encoding based on the overhead bit set at a predetermined position in one received block of a predetermined data length,
If it is determined that all “0” slots exist, the slot information bit set at the predetermined position is extracted from the received block, and the position of all “0” slots specified by this slot information bit is extracted. , is characterized by inserting and restoring all "0" slots in a predetermined all "0" slot position, and restoring all bits of slots corresponding to other all "0" slot positions to "0" bits. Transmission path decoding method.