JPH02236534A - Lens interchangeable type camera system - Google Patents

Abstract

PURPOSE:To reduce the number of terminals by a line by using a terminal which sends prescribed data for specifying the address of the ROM of an interchangeable lens from a camera main body to the interchangeable lens and a terminal which sends the prescribed data from the interchangeable lens to the camera main body in common. CONSTITUTION:Terminals (a - f) electrically connect between the camera main body 1 and accessories 2 - 4 and between the accessories 4 and 5 respectively. Hereby, when the address of the ROM of the interchangeable lens 5 is specified, a clock generated in the camera main body 1 is sent to the interchangeable lens 5 through a first terminal and based on the clock, the prescribed data for specifying the address of the ROM is sent to the interchangeable lens 5 through a second terminal. In the interchangeable lens 5, read memory data is sent in a series on a camera main body side through the second terminal and read based on the clock. Thus, the number of terminals can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a camera system comprising a camera body and an interchangeable lens detachably attached to the camera body, and particularly relates to a camera system in which data is exchanged between the two. Regarding the system.

Conventional technology A camera system in which a storage device such as a ROM is provided on the interchangeable lens side to store various data specific to the interchangeable lens, and this data is read in series by the camera body is disclosed in Japanese Patent Laid-Open No. 54-108628, for example. proposed in No. Since this camera system communicates data in series, the number of data communication terminals between the camera body and the interchangeable lens can be reduced compared to when data is communicated in parallel.

Problems to be Solved by the Invention In this camera system, in order to read desired data stored in the ROM, an address data sending terminal for specifying the address of the desired data from the camera body, and a clock terminal for reading the data are provided. A total of three terminals were provided, including a data input terminal for inputting the desired data from the interchangeable lens.

However, it is desirable that the number of terminals be as small as possible because the number of terminals increases the cost and increases the probability of data communication failure due to dust adhesion or dirt on the terminals.

Another object of the present invention is to provide a camera system that can further reduce the number of terminals.

Means for Solving the Problems The present invention provides an interchangeable lens camera system including a clock generating means provided in the camera body for generating a clock for data communication, and a clock generating means provided in the camera body for transmitting the clock toward the interchangeable lens. ml terminal, a predetermined data output means provided on the camera body and outputting predetermined data in series in synchronization with the clock, and predetermined data outputted from the predetermined data output means provided on the camera body and directed to the interchangeable lens. a third terminal provided on the interchangeable lens and connected to the first terminal; a fourth terminal provided on the interchangeable lens and connected to the second terminal; a ROM that stores a plurality of data specific to the interchangeable lens at corresponding addresses; and a predetermined data read that reads the predetermined data provided on the interchangeable lens and input to the fourth terminal based on a clock input to the third terminal. means, and a third terminal that converts data in the ROM stored in an address corresponding to the predetermined data provided in the interchangeable lens and read by the reading means into serial data based on a clock input to the third terminal. The device includes a data exit means for sending data to the terminal, and a ROM data reading means provided on the camera body and reading the ROM data inputted to the second terminal via the fourth terminal based on the clock of the clock generation means. It is characterized by

In addition, the interchangeable lenses used in the above camera system are:
A first terminal that receives a data communication clock sent from the camera body, a second terminal that receives data that is sent out as serial data from the camera body in synchronization with the clock, and data input to the second terminal. a ROM that stores a plurality of data unique to itself at corresponding addresses, and a ROM that stores a plurality of data unique to itself at addresses corresponding to the data read by the data reading means. The device is characterized by comprising data output means for serially outputting stored data in the ROM to the second terminal based on a clock input to the first terminal.

With the above configuration, when specifying the address of the ROM of the interchangeable lens, the clock generated in the camera body is sent to the interchangeable lens via the first terminal, and based on the clock, the address of the ROM is specified. Predetermined data is sent to the interchangeable lens via the second terminal. In the case of an interchangeable lens, the clock and predetermined data sent from the camera body are read by the interchangeable lens, and R is adjusted according to the data.
The lens data stored at the address of OM is read out. The read stored data is serially sent to the camera body side via the second terminal based on the clock and read.

Embodiment FIG. 1 is a block diagram showing the entire photographing system that is the premise of the present invention. (1) is the camera body,
A central control circuit (IO) is provided inside the camera body for outputting address data to accessories attached to or connected to the camera body and for inputting data from the accessories.

(2) is an electric drive accessory (motor drive)
A data power device (20) is provided inside this to output data unique to the motor drive. (
3) is an accessory (strobe) for flash photography, and a data output device (30) for outputting data specific to the strobe is provided inside. (4) is a lens accessory such as an intermediate ring or a bellows, and a data output device (40) for outputting data about the lens accessory is provided inside the lens accessory. (5) is an interchangeable lens, and a data output device (50) for outputting data specific to the interchangeable lens is provided inside this lens.

Camera body (1) and accessories (2), (3),
(4) and accessories (4) and (5) are electrically connected by terminals (a) to (r), respectively. Here, as described later, the terminals (a), (b
), (C), and (d) from the camera body (1) to the data output device of each accessory, respectively.
A reference clock pulse, address data, and a reset signal are supplied. Further, data unique to each accessory is supplied to the camera body (1) from the data output device of each accessory via the terminal (e). Terminal (r) is a ground terminal.

FIG. 2 is a block diagram of the central control circuit (lO) of the camera body (1). (11) is a power supply control circuit which supplies power from a terminal (a) to a data output device (50) of an accessory such as an interchangeable lens (5). (SW 1)
is a switch that is closed when the lens (5) is attached to the camera body (1). (SW2) is a release switch for starting exposure control operation, and (SW3) is a photometry switch for starting photometry operation. For example, when the release button is pressed in the first step, the photometry switch (SW3) is activated in the second step. The eye closes the release switch (SW2). The photometry switch (SW3) may close in response to a change in resistance of a pressure-sensitive element caused by a current flowing through the user's finger or pressure from the finger when the user's finger touches the release button. (l2) is a timing circuit, and a switch (
Address output device (13) and data input device (l4) based on the closing signals of SWI), (SW2), and (SW3)
A timing signal is applied to the terminals to control the timing of address data output and data capture, respectively, and a reference clock pulse is supplied to the terminal (b) and a reset signal is supplied to the terminal (d). The address output device (13) is controlled by the timing circuit (12) and serially outputs address data bit by bit from the terminal (e). The data input device (!4) reads data unique to each accessory that is serially input bit by bit from the terminal (e), converts it into parallel data, and converts it into parallel data.
5). The arithmetic circuit (l5) calculates data for exposure control and the like based on the above data, and sends the data to the aperture control device (16), shutter control device (17), and display device (18), respectively.

Table 1 is a table showing an example of the contents of a ROM that is provided for each data output device of each accessory and stores data unique to each accessory.

Table 2 is a table showing the relationship between the above data output from the ROM and the meaning of the data. In Table 1, the upper two bits (a6) and (a5) of the address data are data indicating which accessory, ie, which ROM, to select.If the selected accessory is an interchangeable lens, "lO"; if it is a strobe, "lO" For lens accessories, it is "l1". Although not shown in Table 1, if it is a motor drive, it is "00'°."

The lower 5 bits (a4) to (aO) of address data are R
This specifies the address of OM. Next, input data when various accessories are installed will be explained based on Tables 1 and 2. Focal length 59mm, maximum aperture F1
．． 4. A case will be explained in which, in addition to the minimum aperture value Fl6, a lens capable of outputting distance information corresponding to the amount of lens protrusion is attached.

First, as mentioned above, data specific to the lens is output from the lens by the upper two bits of the address data (a6
), (a5) are "10".

The lower 5 bits (a4) to (ao) are “o o o
o o”, the interchangeable lens outputs data with a check code “11100” indicating that the lens is attached to the camera body (1). Therefore,
When the address "1000000" is specified from the camera body, if the data "11100" is input to the camera body (1), it can be confirmed that an interchangeable lens is attached. Similarly, as shown in Table I, “0100000
If the data of ``11100'' is input to the camera body when `` is specified, it means that the strobe is attached.
If data of 0''' is input to the camera body, it means that the lens accessory is attached.

Next, when the address "l 0 0 0 0 0 1" is specified, it means that the address of the ROM where the data of the open aperture Avo is stored is specified, and the F
l. 4 data "00010" is sent to the camera body. Next, when the address "l 0 0 0 0 1 0" is specified, the minimum aperture A v! For example, data "01111" of F16 is sent. This data corresponds to F16 as shown in Table 2. When the address "1000011'" is specified, a signal indicating whether the attached lens is configured to output the distance information is output. For example, in the case of the 50mmF1.4 lens in Table 1, the data of "oooooo" is output because it is a lens that outputs distance information, whereas in the case of the 28mmF2 lens, the data of "oooo i" is output because no distance information is output. Output.

Next, when the address "+000100" is specified, it means that the address of the ROM in which focal length data is recorded is specified, and 50+mmFl. In the case of lens No. 4, the focal length is 50 mm, so data "00110" indicating that the focal length is within the range of 40 to 60 mm is output. Also, the data on the amount of lens extension described later is the address of the lens ROM. The distance information is output based on this address data.If the extension amount data is "ioooo", 'l0
When the address of 10000'' is specified, the data "11111" corresponding to the distance ■ is output, and if the protrusion amount data is ゛1 1 1 1 1', the address "1011" is output.
111" is specified, and data "00111" corresponding to a distance of 1.4 m is output.

Next, if a strobe is attached, as with the lens, if the address "otooooo" is specified, a check will be made, and the code "11100" will be entered into the camera body, confirming that the strobe is attached. be done. Next, the address "0100001" is specified. This address stores the data of the minimum guide number, for example, the data “00010” for guide number 1.4.
" is output. Next, when the address "0100010" is specified, the maximum guide number data is stored in this address, for example, guide number 28.
Data “10010” is output. Next, “010
When the address "0011" is specified, the data of the light distribution characteristics is stored in this address, and in this example, ゜'
Data of 00001" is output. This data indicates that the vertical direction is 45 degrees and the horizontal direction is 60".

1 1 0 if lens accessories are attached
If the address “0 0 0 0” is specified, “11
100" check code is entered into the camera body to confirm that the lens accessory is attached.
When the address ``1100001'' is specified,
If the data "00011" is input, it is confirmed that the teleconverter is installed. As shown in Table 2, if the data is "00001", the bellows
If the data is “00010”, the reverse adapter “
If it is 00100'', it is confirmed that the intermediate ring is attached.

Although not shown as an example in Table 1, if a winder (motor drive) is installed, the winder will
), (a5) is "00"°, data unique to the winder is input to the camera body.

And like other accessories, “0000000
”, the check code “1110” is specified.
0'' is input into the camera body, '0000001'',
Once the address is specified, the number of images that can be taken per second (
The data of the frame speed) is input. As shown in Table 2, if the data is “oooooo゜゜, it is 1 frame/second,” 0110
If it is 0", it is 7 frames/second.

Figure 3 shows the address output device (1) on the camera body (1) side.
FIG. 3 is a circuit diagram showing specific examples of a partial circuit of 3), a partial circuit of the data input device (14), and a data output device of each accessory. Note that an interchangeable lens is shown as an example of an accessory. Further, FIG. 4 is a time chart of FIG. 3. In FIG. 3, (OSC) is a reference clock pulse output circuit. The clock pulse (CP in Figure 4) from this circuit (OSC) is sent to the lens (CP) via the terminal (b).
5) is also sent. (CNTI) is the clock pulse (
It is a counter that counts c p), and (DECI)
are the outputs (CBO) and (CBI) of the counter (CNTI)
．． A decoder that decodes the data of (CB2),
The output of this decoder is (TBO) to (TB7) in Figure 4.
The timing signal is shown below. In addition, the lens (5
) side, the counter (CNT2) and decoder (D
EC2) is the counter (CNTI) on the camera body (1) side.
This decoder (DECI) has the same configuration as the decoder (DECI).
The outputs of the DEC2) are timing signals shown in (TLO) to (TL7) in FIG.

The outputs of the two decoders (DEC l) and (DEC2) decode the output of the counter (CNTI) (CNT2) that counts the same clock pulse (c p), so the same timing signal is output and the camera body (1
) side and the lens (5) side are synchronized. Table 3
counter (CNT1), (CNT2) and decoder (D
HCI). The relationship between the outputs of (DEC2) will be shown below.

When the camera body outputs a reading start signal, the flip
7 lop (F1) is set (FIQ in FIG. 4), and the reset state of the counter (CNTI) is released.

As a result, the counter (CNTI) starts counting clock pulses, and the detector (DECl) starts outputting timing signals (TBO) to (TB7). Note that the counter (CNTl). (CNT2) output is “0”
When 00#, decoder (DEC l). (DEC2) outputs to AND circuits (AN2) and (AN6) are “Hi”
gh”, so the AND circuit (AN2) and (
AN6) is provided so that a "High" level timing signal (TBO).(TLO) is output only after the counters (CNTI) and (CNT2) start counting.

First, in step (S O) in Figure 4 (from when the read start signal is input until the first timing signal (TB7) is output), (TBI) rises to “High”. Address data “iooooooo” is latched in the register (REGI) at the timing, and then (TB7
) is output and the AND circuit (AN
This data is latched into the shift register (SRI) at the timing when the output of II) falls to "Low". During this step (SO), the Q output (F2Q in FIG. 4) of the clip/7lop (F2) is "Low", so other circuits do not operate. When transitioning from step (SO) to step (Sl), that is, when the 9th clock banorless (c p) is counted, the counter (CNTI
) output (CB3) rises to “High” (Fig. 4C
B3) As a result, the D input of the flip-7 lop (F2) is taken in, and its Q output becomes "High" (Fig. 4 F).
2Q). As a result, the gate of the AND circuit (ANI) is opened and a clock pulse is supplied to the shift register, and the reset state of the circuit on the lens (5) side is released via the terminal (d). Shift register (SRI)
) serially outputs the latched address data "toooo000" bit by bit from the terminal (C) in synchronization with the rising edge of the clock pulse. This output data is sequentially taken into the shift register (SR3) on the interchangeable lens (5) side in synchronization with the falling edge of the clock pulse, and is output to the terminals (Lad) to (La4) (4th Figure (Lad) ~ (La4)). And the terminal (TL5
) becomes “High”, the terminal (La4
). The output of (La3) becomes "10", the output of the AND circuit (AN5) becomes "High", and the Q output of the 7-rip/7-lop (F3) which receives this output at the D input becomes "High". (Fig. 4 F3Q). At the timing when the terminal (TL7) of the decoder (DEC2) on the lens (5) side rises, the data at the output terminals (La4) to (Lad) of the shift register (SR3) are the lower 5 bits of the address data ( In the case of step SL, “ooo
oo''), and the address of ROM (51) ``o o o o o'゜ is specified. As a result of this address designation, the data of the aforementioned check code "Ill00" is output from the ROM (51).

The above data from this ROM (5 1) is sent to the terminal (TL
7) is latched into the shift register (SR4) at the rising edge.

Since the Q output of the flip-flop (F3) is “High” at the time of the timing pulse (TL5),
When the next timing pulse (TLO) rises to "High", the clip-flop (F4) takes in the Q output of the flip-7 flop (F3) and changes the Q output to "High".
” (FIG. 4 F4Q). As a result, the switch circuit (GS) becomes conductive and the data “11100” is transferred to the terminal (
e) It becomes possible to output.

The data taken into the shift register (SR4) is output in the order of "11100" to the terminal (e) via the switch circuit (GS) in synchronization with the clock pulse, and on the camera body (1) side, the falling edge of the clock pulse 7 in sync with
This data is taken into the register (SR2) (fourth
Figures BbO to Bb4).

At this time, the 7 flip-flop (F5) is a flip-flop.
7 Since the Q output of Ronob (F2) is “High”, the next timing pulse (TBO) is “High”.
h” (TBO rises in step S2), its Q output is “High”.Therefore, the gates of the AND circuits (AN3) and (AN4) are open after step S2. It's dark.

Then, at the rising edge of the timing pulse (TBS), the output of the shift register (SR2) is latched into the register (REG2).

In step S2, the above-mentioned data "11100'" is taken in, and the next address data "t o
o o o o t” to the lens (5), and in step S3, the lens data “00010” based on this address specification is transferred to the camera body, and the lens with the next address data “l000010” is transferred. (5), and thereafter addresses and data are transferred in the same manner.

As shown in Table 1, the upper address of the lens is '10''
Therefore, this is determined by the data output device (50) of the lens (5) and the switch circuit (GS) is turned on, but in the case of other accessories such as strobes, lens accessories, motor drives, etc. As shown in Figure 5, AND circuits (A.N.
5) The input voltage level of the input terminal is modified. In other words, in the case of a strobe, the upper address data is "Ol'°, so when this signal is input, the AND circuit (AN5-1)
output becomes "High", and in the case of lens accessories it is "11", so the AND circuit (AN5-2) becomes "High".
In the case of a motor drive, it is “00”, so configure the circuit so that the output of the AND circuit (AN 5-3) becomes “High”.The other circuit configuration in these accessories is the internal circuit of the lens (5). It is similar to the configuration.

In Figure 3, the distance between the camera body (1) and the lens (5) is as follows.
Clock pulse terminal (b), address data terminal (
C), a total of six terminals were required: a power supply terminal (a), a ground terminal (f), a reset terminal (d), and a data terminal (e), but the number of such connection terminals was It is desirable to have as few as possible.

Therefore, in the first embodiment of the present invention shown in FIGS. 6 and 7, the number of terminals is reduced by one by using a common terminal for address data and data. Also, the 8th
In the embodiments shown in FIG. 9, FIG. 9, and FIG. 1θ, the number of terminals is reduced by one by using a common terminal for address data and reset.

The circuit configuration in Figure 6 is basically the same as the third factor, but since the address data transfer line and the data transfer line are shared at the terminal (g), the address and data transmission is A circuit is added to switch the timing. And the terminal (g) has a counter (CNTI)
(CB3) terminal is “High” (step S
l, S3, S5...) are the address data, and when the (CL3) terminal of the counter (CNT2) is "High" (steps S2, S4, S6...), the accessory data is sent. It has become.

In the SO step, (TBI) becomes “Hi” as in Fig. 3.
gh”, address data is latched in the register (REGl), and the shift register (SRI
), the address data from the register (REG1) is latched at the time the output of the AND circuit (ANII) falls to "LOW".

In the next step Sl, the counter (CNTI) terminal (C
B3) goes high, the switch circuit (GS
I) becomes conductive, and in synchronization with the clock pulse from the AND circuit (ANI), the address data latched in the shift register (SRI) is sequentially output bit by bit to the terminal (g). At this time, the switch circuit (GS3) is out of conduction, contrary to the above switch circuit (GSI).
The address data input from the terminal (g) to the lens (5) is never input to the shift register (SR2).
3) is “Low”, the switch circuit (
GS2) becomes conductive, which causes the shift register (SR
3) (Fig. 7 LaO-La4).
And the terminal (TL7) of the decoder (DEC2) is “H”.
The data from the ROM (5l) is latched into the shift register (SR4) by the signal from the AND circuit (ANl5) when rising to ``high''' (see Fig. 7).
Latch). Also, at the timing when (TL5) becomes “High”, the output of the AND circuit (AN l 2) rises, and at this time, the upper 2 bits of the address data become “
lO'', the output of the AND circuit (AN5) is “H i
gh”, so 7 rip flops (F 3)
The Q output of becomes “High” (FIG. 7, F3Q). S
In step 2, the terminal (CL3) of the counter (CNT2)
) becomes "High" (CL3 in Fig. 7), and the terminal (CB3) of the counter (CNTI) becomes "Low" (CB3 in Fig. 7). When the terminal (CL3) becomes "High", the switch circuit (GS2) becomes non-conductive, and when this terminal (CL3) rises to "High", 7rip and 7lop (F4) become D. Take in the input, that is, the Q output of 7 lips and 7 lops (F3), and the Q output is “
becomes High (F4Q in Fig. 7). Therefore, the output of the AND circuit (AN14) becomes High, the switch circuit (GS) becomes conductive, and the shift register (SR4
) can be output to terminal (g). on the other hand,
When the terminal (CB3) of the counter (CNTI) becomes “Low”, the switch circuit (GSI) becomes non-conductive (GS3)
becomes conductive. Then, in synchronization with the clock pulse from the AND circuit (AN4), the shift register (SR2)
takes in the data from the shift register (SR4) (
7BbO-Bb4), the shift register (
The data taken into SR2) is latched into the register (REG2) (FIG. 7 REG2 Latch). Also,
In the S2 step, the next address data is taken into the shift register (SRI) at the falling timing of the clock pulse when the terminal (TB7) is "High", so in the S3 step, the address is transferred from the terminal (g). The signal is output to the lens (5), and the same operations as the above-mentioned steps S1 and S2 are repeated.

Figure 8 shows the address data transfer line (
c) and the reset signal line (a) are connected to a common line (
FIGS. 9 and 10 show a circuit example and a time chart for the case h). Reading start signal (Figure 9 Start)
is input, 7 lip flops (Ft). (F9
) is set (FIQ.F9Q in Figure 9) and the operation starts.

The Q output of the flip 7p/7p knob (F9) is “HiHh”
As a result, the output of the OR circuit (ORI) becomes “High”
Then, the multiplexer (MPI) outputs the input "1 1 1 1 1 1 1 1" from (A), and uses this output as the falling edge (9th
Figure S R I Latch) and shift register (S R I Latch)
Rl). Since the flip-flop (F9) is reset (F9Q in Figure 9) at the falling edge of the timing pulse (TB7), the multiplexer (MPI)
is the normal address data (register (RE) from (B)
GI) output). Here, the multiplexer (M
Data from (A) of PI) “I l l l l l
1 1 ” is data that is not an address of any accessory, and when the input of this data is determined, the reset state of the circuit in the accessory (5) is released.

The data latched in the shift register (SRI) is sequentially output from the terminal (h) bit by bit based on the clock pulse from the AND circuit (ANI) and sent to the lens (5).
It is taken into the shift register (SR3) on the side (9th
Figure LaO=La7).

When the terminal (La7) becomes "High", all outputs of the register (SR3) become "High"'
The output of the NAND circuit (AN22) is “High”
Standing up, at this time flip 7 lop (F I 5)
is reset and the Q output is "High"', so the output of the AND circuit (AN23) rises and the flip-7 lop (Fil) is set (FIG. 9, F11Q). Then, at the rising edge of the next clock pulse, the Q output of 7 rip and 7 lop (Fl2) becomes "High" (Fig. 9).
Fl2Q), thereby releasing the reset state of the circuit. Subsequently, at the rising edge of the clock pulse, the Q outputs of flip 7' (F13), (Fl4), and (Fl5) sequentially become "High" (Fig. 9 Fl
3Q. Fl4Q, Fl5Q). Flip 7 lops (F
When the Q output of l5) becomes “Low”, the AND circuit (AN23)
When the gate of the AND circuit (AN24) is closed and the gate of the AND circuit (AN24) is opened, the output of the AND circuit (AN22) rises to "HJgh"'.
11) is reset. Thereafter, addresses and data are exchanged in the same manner as in FIG.

The read end signal is a timing pulse (
TB6). As a result, 7 lips and 7 lobes (FIO) are set (FIG. 1O FIOQ), and the multiple plexer (MPI) outputs "1 1" from (A).
1 1 1. 1 1 1" data is output. This data is output from the AND circuit (ANIl) and latched into the shift register (SRI) (see Figure 10).
Latch) terminal (h) to the shift register (S R 3) on the lens (5) side. Then, when the output of the AND circuit (AN22) becomes “High” (the first
Figure AN2 2), and the AND circuit (AN2
Since the gate of 4) is open, flip 7 lots (
Fil) is reset (FIIQ in Figure 1O), and the next clock pulse causes a flip/7 lop (F 1 2).
'7) Q output becomes "Low" (Fig. 10 F12
Q) The circuit on the lens (5) side goes into a reset state. And flip 7 flop (F l 3). (F l
4), the Q outputs of (Fl5) sequentially become “Low” based on the clock pulse (FIG. 1O FI.3
Q. F 1 4Q. F l 5Q). In FIG. 10, the hatched portions (Lad) to (La7) indicate that this output can be in either a "High" or "Low" state. However, since none of the signals becomes "High" except when the read end signal is output, the above operation is not affected.

On the other hand, on the camera body (1) side, when the reading end signal is input, 7 lips and 7 lops (F6) are set, and (
Figure 1O F6Q), next timing pulse (TB7)
At the falling edge of 7 rip/7 lop (F7), the Q output becomes
Then, at the falling edge of the next timing pulse (TB7), the Q output of the flip-7 lop (F8) becomes "High" (FIG. 10, F8Q).

Then, a clock pulse is output from the AND circuit (AN21), and at the fall of this clock pulse, 7 rip, 7 lop (Fl). (F2). (F6). (F7).
(F8), the counter (CNTI) is reset and the circuit on the camera body (1) side is also reset, waiting for the next reading start signal to be input.

In the embodiment shown in FIG. 6, the address data transfer line and the data transfer line are made common, and in the embodiment shown in FIG. 8, the address data transfer line and the reset signal line are made common, and the camera body (1) The number of electrical connection terminals between the
In the illustrated example, the address data transfer line, the data transfer line, and the reset signal line are used in common, and the number of electrical connection terminals is reduced to four. In addition,
FIG. 12 is a time chart when the reading operation of the circuit shown in FIG. 11 is started, and FIG. 13 is a time chart when the reading operation of the circuit is completed.

Based on these FIGS. 11 to 13, the second aspect of the present invention
An example will be explained. When the read start signal is input, 7 lip-flops (Fl). (F9) is set (FIQ.F9Q in Figure 12), and the counter (
CNTI) is released from the reset state and the circuit starts operating. At this time, since the flip-7 lop (F9) is set, the output of the OR circuit (ORI) is “High”.
h” and the multiplexer (MPI) outputs “11
Fixed data (A) of 111111'' is output.

7 rip-flop (F21) is an AND circuit (AN31)
) is set at the falling edge of the AND circuit (AN32), and reset at the falling edge of the AND circuit (AN32). It becomes "High" at the timing shown by ANII in FIG. The shift register (SRI) that receives this output inputs the output of the multiplexer (MPI) in parallel at the rising edge of the clock pulse while the parallel input/serial output switching terminal (SP) is "High", and outputs the output from the multiplexer (MPI) in parallel. While the output of (ANII) (ie, the switching terminal (SP)) is "Low", data is serially outputted to the output terminal in synchronization with the rising edge of the clock pulse.

At the time of transition from the (S O) step to the (s l) step, the flip-flop (F9) is reset (Fig. 12 F9Q), and the output of the OR circuit (ORI) becomes “L”.
ow", and from then on, the multiplexer (MPI) outputs the address data from the register (REGI). In the .(St) step, the terminal (CB3) of the counter (CNTI) is "High", so the switch circuit (G
SI) is conductive and terminal (i) has reset data “1”.
1111111" is output. At this time, the counter (
CNT2) is in the reset state, so the terminal (
CL3) becomes "Low", and the Q output of the D flip/7 lop (Fl2) becomes "Low".

Therefore, the output of the exclusive output circuit (EOI) becomes "Low". (Fig. 12 EO), the switch circuit (GS2) becomes conductive, and the data from the terminal (i) is taken into the shift register (SR3) in synchronization with the falling edge of the clock pulse (Fig. 12 LaO to La7). . All of the outputs of the shift register (SR3) are “Hi”.
At the moment the output of the AND circuit (AN22) becomes "High", the flip-flop (Fil) is set via the AND circuit (AN23) (the 12th
At the rising edge of the next clock pulse, the Q output of the flip-flop (F12Q) becomes “High” (FIG. 12F12Q), and the
3). (F4), the reset state of the counter (CNT2) is released. Then, on the next clock pulse, 7 rip.
The Q output of the 7-lop (F l 3) becomes "High", the gate of the AND circuit (AN23) is closed, and conversely, the gate of the AND circuit (AN24) is opened, and the shift register (S R 3) is opened again. Flip-flops (Fll) and (Fl2) until all outputs of
, (F l 3) are "High".

In the step (S2), the address data is latched in the register (REGI) at the rising edge of the timing pulse (TBl), and the address data is latched in the register (REGI) at the rising edge of the timing pulse (TB7) (the timing of the clock pulse while the AND circuit (ANIl) is "High"). At the rising edge timing), the shift register (SRI) contains address data “l 0 0 0
0 0 0 0” is imported.

In the step (S3), the shift register (SRl) is set again.
The data from is taken into the shift register (SR3), and the output of the AND circuit (AN5) becomes "High" at the timing of the rising edge of the timing pulse (TL5), so 7 rip and 7 lop (F3) The Q output becomes ``High'' and the timing pulse (TL7)
At the rising edge of , the Q output of 7-rip/7-lop (F4) becomes "High" (F4Q in Figure ml2). Also, like the shift register (SRI), the shift register (SR4) takes in data from the ROM (51) in parallel at the rising edge of the clock when the switching terminal (SP) is "High".

Here, the AND circuit (AN l 5) is the AN of FIG.
Since it becomes "High" only during the period indicated by +5, the output of the exclusive OR circuit (EOI) is "L".
At the rising edge of the timing pulse (TL7) at the time of OW'''', data from the ROM (51) is taken in in parallel to the shift register (SR.4). Then, in step (S4), when the output of the exclusive OR circuit (EOI) becomes "High" (EO in Fig. 12), the switch circuit (GS) becomes conductive and (G
S2) becomes non-conductive, and data from the shift register (SR4) is sequentially output to terminal (i). At this time,
In the circuit on the camera body (1) side, the counter (CNTI)
The terminal (CB3) is “Low (CB3 in Fig. 12),
Since the Q output of the flip-7 lop (F5) is “High” (Fig. 12 F5Q), the switch circuit (G
SI) is nonconductive, (GS3) is conductive, and the AND circuit (A
N3). (AN4) gate is open. Therefore,
Data from the terminal (i) is sequentially taken into the shift register (S R 2) in synchronization with the falling edge of the clock pulse, and data is taken into the register (REG 2) at the timing of the rising edge of the timing pulse (TBS). Similarly, address data is sent from the camera body to the accessory via terminal (i) at step (32k-1) (k is an integer), and data is sent from the accessory to the camera body at step (52k). Repeat this action.

Now, if the address "200000" (the first address of the lens accessory address in Table 1) is specified in the step (S2n-5), the check code "11100" is read in the step (S2n-4). ,
The address “1100001” is specified in the step (S2n-3), and the address “O O” is specified in the step (S2n-2).
0 1 1'' data is read, and data indicating that the lens accessory is a teleconverter is read. When the reading of the data regarding this lens accessory is completed, a reading end signal is output at the timing of the timing pulse (TB6). (End of Figure 13), flip 7 lop (FIO), (F6) is set (FIOQ, F6Q in Figure 13).As a result,
The output of the OR circuit (ORI) becomes ``High'' again and the multiplexer (MP!) outputs ``1111111''.
1" data is output and this data is taken into the shift register (SRI) in parallel. On the other hand, the flip 7
The flop (F l O) is reset by the timing pulse (TB7) (FIG. 13 FIOQ), and the D flip 7 flop (F7) changes the Q output of the 7 flip flop (F6) at the falling edge of (TB7). Incorporate (13th cause F7
Q). Further, data "11111111" from the multiplexer (MPI) is fetched in parallel into the shift register (SRl) at the rising edge of the clock pulse when the AND circuit (ANII) is at "High".

When the step (S2n-1) comes, the AND circuit (AN
In synchronization with the rising edge of the clock pulse from I), the data “11111111” is transferred to the shift register (SRI).
The signal is sent to the input terminal of the shift register (SR3) via the switch circuits (GSI) and (GS2), and is sequentially fetched in synchronization with the falling edge of the clock pulse. And all the outputs of the shift register (SR3) are “High”.
”, the output of the AND circuit (AN22) becomes “
rises to High.At this time, the Q output of the flip-flop (Fl3) is also high, so
The output of the AND circuit (AN24) rises and the 7 lip-flop (Fil) is reset. Then, with this next clock pulse, the D flip 7 flop 7' (F12) takes in the Q output of the flip 7 lop (Fil), and the Q output falls to "L ov" (FIG. 13 Fl2Q).
D flip-flop (F3). (F4), counter (
CNT2) is reset, the output (TLO) of the AND circuit (AN6) and the output of the exclusive OR circuit (EOI) become "Low", and at the rise of the next clock pulse, the Q of the D flip 7 log (Fl3) is reset. Output is “Low”
” (Fig. 13 Fl3Q), accessories (5)
The side circuit waits for the next read start signal to be input.

In the circuit on the camera body (1) side, (S2n-1)
At the falling edge of the timing pulse of step (TB7), the Q output of D flip 7 log (F8) goes high.
h” (Fig. 13 F8Q), and the AND circuit (AN2
A clock pulse is output from 1), and at the falling edge of this clock pulse, 7 rip/7 lop (F l). (F6)
, D clip 7 lop (F2). (F7). (F8
) is reset, ``Furthermore, flip 7 lop (F
1), the counter (CNTI) is also reset and enters a state of waiting for the next read start signal to be input.

In addition, Fig. 3. Figures 6 and 8. In the circuit shown in FIG. 1l, it is needless to say that the camera body (1) side needs to be reset by a power-on reset signal when the power is turned on. Also, a power-on reset signal generation circuit is installed inside each accessory so that the power-on reset signal is generated when the accessory is connected to the camera body (!) and power supply starts to the data output device of the accessory. It is also necessary to reset the circuitry inside the accessory.

In addition, in the case of accessories such as lens accessories, which have only a small number of types of data to be fixedly stored and which are produced in small numbers, the ROM installed inside the accessory may be a programmable ROM or fuse ROM suitable for small-volume production.
etc. may also be used.

Alternatively, the wiring may be performed using a wiring pattern of a printed circuit board or wiring with a /% solder.

FIG. 14 shows the part in the address output device It (13) that sends address data to the register (REGI) in FIG.
FIG. 2 is a circuit diagram of a portion that reads data from REG2).

When the photometric switch (SW3) is closed, the power supply transistor (BTI) becomes conductive, and a reset signal (power ON reset signal FOR
) is output, and the flip-flops (F41) and (F4
2), (F43) and the counter (CNT5) are reset. Also, when the photometric switch (SW3) is closed, the output of the inverter (INI) becomes "High", the gate of the AND circuit (AN40) is opened, and the clock pulse ( CP) is input, and the divider (D!) outputs a pulse with a constant period obtained by dividing the above clock pulse, and the one-shot circuit (051)
A reading start signal is output at regular intervals. Therefore, in this embodiment, while the photometric switch is closed,
Since the device is configured to automatically read data from accessories periodically, there is no need for a switch to detect that an accessory is attached, such as the switch (St) in FIG. 2.

First, the operation of sending address data to the register (REGI) in response to a read start signal will be described. When the read start signal is output, the flip-flop (F40). (
F4 1) is set and the AND circuit (AN4 1).
(AN42) is opened, and the counter (CNT6). (CNT7). (CNT8) is reset. Then, in the (SO) step, (TBO
), the output of the counter (CNT5) becomes "Ols", and the falling edge of this timing pulse (TBO) resets the 7 lip-flop (F 4 0), and from then on, the counter (CNT5) receives no timing pulses. (TBO) is no longer input. Then, as mentioned above, at the rising edge of the timing pulse (TBI), the register (R
EGI) is a counter (CNT5) and a multiplexer (
The output of MP2) is latched as address data, but
At this time, the output of the counter (CNT5) is “Ol”,
The output of the multiplexer (MP2) is “o o o o
o”, so the address data latched into the register (REGI) is “l 0 0 0 0 0 0”, which is the first address of the lens.The output of the counter (CNT5) is before and after that output bit. is input to the register (REGI) in the opposite state.Here,
The multiplexer (MP2) inputs the input data (α) to the multiplexer (MP2) when the counter (CNT5) is “Ol”, inputs (β) when the counter (CNT5) is “11
”, (γ) is output respectively.

At the rising edge of (TB2), the counter (CNT6) counts by one via the AND circuit (AN42) and outputs "oo".
t"". Then, in the next step (Sl), at the rising edge of (TBI), the register (REGI) is set to “
1000001” address data is latched and (T
At the rising edge of B2), the output of the counter (CNT6) becomes “01”.
0”.

Thereafter, the same operation is repeated, and the address data of the lens is sequentially fetched into the register (REGl). Then, in step (S4), the address data "1000100" (the final address of the lens) is latched in the register (REGI) at the rising edge of (TB1), and the counter (C N T 6) is latched at the rising edge of (TB2).
) becomes “101”, the AND circuit (AN56
) rises to "High", and a pulse is output from the one-shot circuit (OS2). This pulse causes the flip-flop (
F41. ) is reset, the flip-flop (F40) is set via the OR circuit (OR5), and the flip-flop (F42) is directly set.

In step (S5), at the rising edge of (TBO), the output of the counter (CNT5) becomes "10" degrees, and the data of (β) is output from the multiplexer (MP2).

Therefore, at the next rising edge of (TBI), register (REGI)
) The address data latched in is “0100000”
', which becomes the strobe's start address. and,(
The timing pulse of TB2) is an AND circuit (AN4j)
It is sent to the counter (CNT7) via the counter (CNT7), and its output becomes "001". Hereafter, the same operation is repeated and (S
8) In step 7, “010” is set at the rising edge of (TBI).
0011” address data (the final address of the strobe) is latched in the register (REGI), and the next (TB2
), when the most significant output bit of the counter (CNT7) becomes "High" (output is "100"), a "High" pulse is output from the one-shot circuit (053). This pulse causes the OR circuit (OR7) to
The flip-flop (F42) is reset through the OR circuit (OR5), the flip-flop (F40) is set through the OR circuit (OR5), and the flip-flop (F40) is set through the OR circuit (OR5).
F43) is set directly. As a result, the gate of the AND circuit (AN43) is closed and the gate of the AND circuit (AN43) is closed.
1), the gate (AN44) is opened.

(S9) In the step/bus, the output of the counter (CNT5) becomes ``1 1'' at the rising edge of (TBO), and the data of (γ) is output from the multiplexer (MP2). ) rises to “1100000”
The address data (the first address of the lens accessory) is latched into the register (REGI). And (T
At the rising edge of B2), the output of the counter (CNT8) becomes “0 bit”, and in the step (S l O), (TBI
), the address data "1100001" is latched into the register (REGI). And (TB2
), the upper bit of the counter (CNT8) becomes “H”.
When the output becomes "High" (output is "10"), a "High" pulse is output from the one-shot turn l (053).This pulse causes 7 rip/7 lop (F 4 3
) is reset, the gate of the AND circuit (AN44) is closed, and the flip-7-knob (F40) is set via the OR circuit (OR5), and the gate of the AND circuit (A
N40) gate is opened. Then, the step (Si
At t), the output of the counter (CNT5) changes from "ll' to "00" by the timing pulse (TBO),
At the falling edge of the timing pulse (TBO), the 7 lip/7 log (F40) is reset and the AND circuit (AN40) is reset.
) gate is closed. With the above operations, the operation of outputting address data is completed, and a state is entered in which it waits for the next read start signal to be output from the one-shot circuit (OSl).

Next, the operation of reading the data read into the register (REG2) into the registers (REG3) to (REG13) will be described. The counter (CNT9) is reset by the read start signal and counts the timing banorless (TB2). Then, the output of the counter (CNT9) is input to the decoder (DEC3), converted into outputs (dO) to (dlo) as shown in Table 4, and then output to the decoder (DEC3).
EC3).

As mentioned above, in steps (So) and (Sl), data from the accessory has not yet been read into the register (REG2) (Fig. 4), so the decoder (D
All outputs of EC3) are "Low". Therefore, the gates of the AND circuits (AN45) to (AN55) are closed, and no data is taken into the registers (REG3) to (REGl3). In step (S2), the first data is taken into the register (REG2) at the rising edge of (TBS). Here, the terminal (dO)
is “High”, the AND circuit (AN4
The gate of 5) is opened, and the data latched in the register (REG2) is latched in the register (REG3) at the next rising edge of (TB6).

Similarly, the registers (REG4) to (REGl3) are sequentially transferred to the registers (REG4) to (REGl3) at the rising edge of the timing pulse (TB6) via the AND circuits (AN46) to (AN55).
The data from REG2) is imported. and,
At step (Sl2), the register (REGl3) is activated by the timing pulse of (TB6) via the AND circuit (AN55).
) when the last data is latched, it means that the read operation has ended, so the timing pulse (TB6) from this AND circuit (AN55) is simultaneously sent to the circuit shown in Figure 3 as a read end signal to start the read operation. ends. Various data from the accessories latched in these registers (REG3) to (REG13) are used for exposure control operations and the like.

Fig. 15 shows the circuit configuration of the address output device and data input device when reading only data from the interchangeable lens, and is also a circuit diagram of the camera body (1) side in which distance information is also read from the interchangeable lens. It is. Lens (5
) is attached and the attachment switch (SWI) is closed, the delay circuit (DL) will close the delay circuit (DL) after a certain period of time.
The output of L) becomes "High". This delay time is set to the time required for the chattering of the signal bottle contact portion between the lens and the camera body, which will be described later, to stop and become stable. Then, the photometric switch (SW3) is closed and the AND circuit (
When the output of AN61) becomes "High", a read start signal is output from the one-shot circuit (055) via the OR circuit (ORII), and the read operation is started. In addition, when the AND circuit (AN61) becomes "High", the gate of the AND circuit (AN60) is opened and the clock pulse (CP) is input to the divider (DI), and the pulse with a constant period is divided into the frequency divided i (DI). is output from. Therefore, similarly to FIG. 14, the reading start pulse is sent to the one-shot circuit (OSI
), is output via the OR circuit (ORII).

The photometry switch (SW3) is closed and the capacitor (CI
), and a resistor (Rl), when a power-on reset signal (FOR) is output from the power-on reset circuit, the clip-flops (F50) and (F51) are reset. The multiplexer (MP3) receives data from (X) when the input to the (S E) terminal is “Low”.
When it is "High", the data from (Y) is output, so when the photometry switch (SW3) is closed and the reading operation starts, the data from the D7 lip-flop (F 5 0) is output. The Q output is “Low” (
The data from X) is output. In the (SO) step, the Q output of the D flip/7 lop (F2) in Fig. 3 remains “Low”, so the counter (CNTII
) remains in the reset state and its output is “000H
It has become. Therefore, data of "1000000" is output from the multiplexer (MP3), and the register (
REGI), this data is latched as address data at the rising edge of the timing pulse (TBI). This data is the leading address of the interchangeable lens (5).

At step (S1), the Q output of the D flip/7 lobe (F2) in Figure 3 becomes "High", the reset state of the counter (CNTII) is released, and the timing pulse (TBO) counts by one. Uploaded '00
1” is output, and the multiplexer (MP3) outputs “l
O 0 0 0 0 1'' is output. This data is latched into the register (REGI) at the rising edge of (TBI). At step (S2), the counter (C
The output of the NTII) becomes “0 1 0”, and as shown in Table 5, the output terminal (aO) of the decoder (DEC5) becomes “0 1 0”.
Table 5 shows the counter (CNTII
) decoder (DEC5) that decodes the count contents of
shows the input/output relationship.

Then, at the rising edge of (TBI), “
The data 1000010'' is latched as an address. On the other hand, the first data 11100 (check code) is input to the register (REG2) (Fig. 3), and the timing pulse of (TB6) is input to the AND circuit (
This data is output from the register (RE
Gl5). (S3) In step (S3), (T
At the rising edge of BO), the output of the counter (CNTII) becomes “0”.
11", the terminal (el) of the decoder (DEC5) becomes "High"', and the gate of the AND circuit (AN64) is opened. Then, at the rising edge of (TBI), "1000011" is stored in the register (REGI). It is latched as address data, and at the rising edge of (TB6), the open aperture value (Avo) data is latched into the register (REGl6) via the register (REG2).

In step (S4), the output of the counter (CNTII) becomes "100" at the rising edge of (TBO), and the output of the register (REGI) becomes "100010" at the rising edge of (TBI).
0" data is latched as address data. Then, at the timing of the rising edge of (TB2), the Q output of the D flip-flop (F 5 0) becomes "High", and the multiplexer (MP3) thereafter (Y ) data will be output.

This (Y) data indicates the amount of extension of the interchangeable lens (5), and the amount of extension is detected on the camera body (1) side by a mechanism described later. Here, taking advantage of the fact that the relationship between the amount of extension of each interchangeable lens (5) and the distance at which the focus has been adjusted is constant for each interchangeable lens, the ROM of each interchangeable lens (5) contains a table. As shown in FIG. 1, distance data is fixedly stored in correspondence with the above-mentioned feed-out amount data. Therefore, once the data of the extension amount detected on the camera body (1) side is designated as the address of the ROM (5l) in the interchangeable lens (5), the distance data stored at that address will be transferred to the camera. It is taken into the main body (1) side so that distance data can be obtained.

Reference numeral (55) denotes a member provided on the side of the interchangeable lens (5), which moves in the left-right direction in the figure in conjunction with a focus adjustment member (not shown, for example, a distance ring) of the interchangeable lens (5). (70) is provided on the camera body (1) side, and the member (55) has a spring (
The member (55) is in contact with the spring force of the member (71).
It moves left and right as it moves. This camera body (
1) side member (70) includes guide bins (72) and (73).
) and a brush (74) as an electrical contact.
, (75), (76), (77), and (78) are provided, and all the contacts are electrically connected. (80) is a code board, the blacked out part is the electrode, and the electrode (80) is the code board.
l) is connected to ground, (82), (83), (84
) and (85) are each connected to the power supply (+E) via a resistor.

Contact points (74), (75), (
76), (77), and (78) are in the position (g), the outputs of terminals (f3) to (fO') are "o".
oot” and the output of the multiplexer is “10100
01". Therefore, the attached interchangeable lenses are shown in Table 1.
of 50o+mFl. If it is a 4-meter lens, the 4ra data "01101" will be output from the interchangeable lens, and if it is a 135-mF3.5 lens, the 19- data "10110" will be output from the interchangeable lens.

Furthermore, when the contacts (74) to (78) come to the position (h), "1001"' is detected through the terminals (f3) to (fO), and "101100" is detected from the multiplexer (MP3).
1" address is output, and if it is 50omFl.4, the data of 0.6-"00010" is l 3 5an
F3. If it is 5, data of 2.5m+“01oio” will be output.

In step (S4), the terminal (e) of the decoder (DEC5)
2) is "High", the timing pulse of (TB6) is output from the AND circuit (AN65), and the minimum aperture data (A v + m) is stored in the register (REG).
l7). In the following step (S5), lens type data is latched in the register (REG18), and in step (S6), focal length data is latched in the register (REG19). In step (S7), the output of the counter (CNTII) becomes "l l l", and the output of the AND b path (AN62) becomes "High".
rises, the flip 7 lop (F51) is set, the gate of the AND circuit (AN68) is opened, and (TB
6), the distance data is latched in the register (REG20), and at the same time, the pulse (TB6) from the AND circuit (AN68) is sent to the circuit shown in FIG. 3 as a read end signal.

If the photometering switch (SW3) remains closed even after reading is completed, the one-signit circuit (SW3) will open after a certain period.
1) outputs the next reading start signal. At this time, 7
The Q output of Rip 7 Lop (F50) and (F51) is ″
Since it remains "High", the register (REGI
), only the data according to the feed amount is output, and (S2
), the distance data is latched in the register (REG20) and the reading operation is completed. In other words, the photometry switch (
When SW3) continues to be closed, only the distance information is repeatedly read. Therefore, in the case of this embodiment, fixed information such as the minimum aperture of the interchangeable lens is read only once, and variable information such as distance information (in addition, for example, focal length information and setting aperture information of the zoom lens) is read repeatedly. It looks like this.

In Figures 3, 6, 8, and 11, the shift register (SRl) for address data output and the shift register (SR4) for accessory data output have 7-bit or 8-bit input. It is configured as a shift register.

For example, in the case of 8-bit input, these shift registers
Read the data input in parallel at the rising edge of timing (TB7) and (TL7), and then read the data input in parallel at the rising edge of timing (TB7) and (TL7).
At the rising edge of TBO) to (TB7) and (TLO) to (TL7), data is sequentially output from the most significant bit to the output terminal (OUT) in series. A shift register that performs such an operation has the following circuit configuration.

First, 81 II flip 7-lops are provided for each bit, in which the data of each bit input in parallel is preset. The output terminal of the flip-7 flop corresponding to the lower bit is connected to the input terminal of the flip-7 lop corresponding to the bit immediately above the lower bit. By doing this, the data that has been pre-noted in each flip/7-lop is sequentially transferred from the lower bits to the upper bits in synchronization with the clock pulse. Further, the output terminal of the 7-rip-flop to which the data of the most significant bit among the 8 is preset is connected to the input terminal of the ninth 7-rip-flop. The output terminal of this ninth 7-rip/7-lop is set as the output terminal of the shift register. By doing this, the 9th flip/7 lop takes in the output of the flip/7 lop whose most significant bit data is preset in synchronization with the clock pulse, so that it outputs data with a delay of exactly one clock pulse. It has become.

Effects As described above, according to the present invention, the terminal that sends predetermined data for specifying the address of the ROM of the interchangeable lens from the camera body to the interchangeable lens, and the address that is written in the address corresponding to this predetermined data. Since the terminal for sending the lens data in the ROM from the interchangeable lens to the camera body is shared, the number of terminals can be reduced by one compared to the conventional model.

kui t9, ethos of the specification (no change in content) nJ11i engraving (no change in content) engraving of the specification (no change in content)
No changes to the contents) Table 2 Reprint of the data declaration specification for ROM contents (No changes to the contents) Revision of the table specification! F (No change in content) Table (continued) Table

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the camera system that is the premise of the present invention, and FIG. 2 is a block diagram showing the configuration of the camera system. Figure 3 is a block diagram showing the circuit configuration; Figure 3 is a circuit diagram showing a part of the data input/output unit on the camera body side and the data output device on the accessory side; Figure 4 is a time chart diagram showing its operation; Fig. 5 is a circuit connection diagram showing an example of connection to other accessories, Fig. 6 is a circuit diagram showing a first embodiment of the present invention that is an improvement on the circuit shown in Fig. 3, and Fig. 7 is the circuit shown in Fig. 6. FIG. 8 is a circuit diagram showing a modification of the circuit in FIG. 3. FIGS. 9 and 10 are time chart diagrams showing the operation of the circuit in FIG. A circuit diagram showing a second embodiment of the present invention, which is an improvement on the circuit of FIG. 3, No. 12
Fig. 13 is a time chart diagram showing the operation of the circuit in Fig. 11, Fig. 14 is a circuit diagram showing the circuit of other parts of the data input/output section on the camera body side in Fig. 3, and Fig. 15 is a time chart diagram showing the operation of the circuit in Fig. 11. FIG. 15 is a circuit diagram showing another embodiment of FIG. 14; l: Camera body, 2: Interchangeable lens, OSC: Clock generation means, 13, REGI, SRI, ANI, GS, l:
Predetermined data output means, b=first terminal, g, i: second terminal, SR3, GS2: predetermined data reading means, 51:
ROM%SR4,GS: Data sending means, 1 4. S.R.
2, GS3: ROM data reader. Figure 5 Applicant: Minolta Camera Co., Ltd. 11 TARD LIFE Procedural Amendment Form 1. Correct the display of the incident. A copy of the detailed statement originally attached to the RA letter.
There is no change in the contents.'' The phrase ``Figure 3'' on page 68 of the specification, lines 13 and 14, will be corrected to ``Figure 11''. Address: Osaka Kokusai Building, 2-3-13 Azuchi-cho, Chuo-ku, Osaka [Administrative division change on February 13, 1989]5. March 31, 1999 (Shipping date: April 25, 1999) "Detailed description of the invention" column and "Brief description of drawings" column of the specification subject to amendment

Claims (2)

[Claims] (1) In an interchangeable lens camera system, a clock generating means provided on the camera body generates a data communication clock, a first terminal provided on the camera body and transmitting the clock toward the interchangeable lens, and a camera body. a predetermined data output means provided on the camera body for outputting predetermined data in series in synchronization with the clock; a second terminal provided on the camera body for sending predetermined data from the predetermined data output means toward the interchangeable lens; a third terminal provided on the interchangeable lens and connected to the first terminal; a fourth terminal provided on the interchangeable lens and connected to the second terminal; and a fourth terminal provided on the interchangeable lens and configured to transmit a plurality of data unique to the interchangeable lens. a ROM stored in a corresponding address; a predetermined data reading means provided on the interchangeable lens for reading the predetermined data input to the fourth terminal based on a clock input to the third terminal; the ROM stored at an address corresponding to the predetermined data read by the means;
data sending means for sending the data to the fourth terminal as serial data based on a clock input to the third terminal; and data sending means for sending the data to the fourth terminal as serial data based on a clock input to the third terminal; ROM data reading means for reading ROM data based on the clock of the clock generation means. A lens exchangeable camera system. (2) In an interchangeable lens that communicates data with the attached camera body, the first terminal receives the data communication clock sent from the camera body, and the first terminal receives the data communication clock sent out from the camera body and transmits serial data from the camera body in synchronization with the clock. a second terminal for receiving sent data; a data reading means for reading the data inputted to the second terminal based on a clock inputted to the first terminal; and a plurality of data unique to itself, respectively, at corresponding addresses. and the data of the ROM stored at an address corresponding to the data read by the data reading means are output in series to the second terminal based on a clock input to the first terminal. An interchangeable lens equipped with a data output means.