JPH01302239A - Flash device having data transmitting function - Google Patents

Abstract

PURPOSE:To decrease the number of terminals between a main body and flash device and to simplify the constitution of the main body of a camera by transmitting, in series, various kinds of data such as on the amount of light emission and on the orientation characteristic in response to a command signal from the main body of a camera, depending on input clock. CONSTITUTION:The main body 1 of the camera has a central control circuit 10 which outputs address data to a mounted accessary and inputs data from the accessory. Inside the accessory 3 used for flash photographing, data output device 30 outputting data inherent in strobe is provided. Electric power, reference clock pulse, address data, and reset signal are fed via terminals a, b, c, and d, respective to between the main body 1 and accessary 3; and data inherent in the accessory is fed via an terminal e. The address '01' of the strobe selects ROM 30, which outputs data on minimum and maximum guide numbers and on the orientation characteristic. Based on the clock from the main body 1 they are digitally transmitted in series, so that circuit configuration is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a flash device that is detachably attached to a camera body.

2. Description of the Related Art In conventional flash photography, the aperture of a camera is controlled and the flash synchronization shooting distance is calculated based on the amount of light emitted by a flash device. In order to do the above on the camera body side, for example, the amount of light emitted by the flash device is replaced with a resistance value and then transmitted to the camera body by connecting it to the circuit section of the camera body.

Problems to be Solved by the Invention However, in this case, what is transmitted to the camera body is an analog quantity, so if the above-mentioned control and calculations are performed digitally, an A10 conversion circuit etc. will be required on the camera body side, which will require a different configuration. It becomes complicated.

The present invention provides a camera system in which data communication between the camera body and a flash device can be performed rationally when predetermined controls and calculations are performed digitally on the camera body side using various data specific to the flash device. This is what we are trying to provide.

Means for Solving the Problems The present invention provides a flash 7 that is detachably attached to a camera body.
The unit includes a data output means for outputting a plurality of types of data including light distribution characteristics and light emission amount, a command signal input means for inputting a signal from the camera body for commanding data communication, and a command signal input means for inputting a signal from the camera body for commanding data communication, and a command signal input means for inputting a signal from the camera body for commanding data communication. The present invention is characterized by comprising a clock input means for inputting a clock from the camera body, and a sending means for sending out the data in series to the camera body in synchronization with the clock.

Operation With the above configuration, when a signal instructing data communication is input, multiple types of data possessed by the flash device are sent out in series toward the camera body based on the clock input from the camera body.

Embodiment FIG. 1 is a block diagram showing the entire photographic system using the present invention. (1) is a camera body, inside which outputs address data for accessories attached to or connected to the camera body, and outputs address data for accessories attached or connected to the camera body.
A central control circuit (10) is provided which inputs data from.

(2) is an electric drive accessory (motor drive)
A data output bag fit (20) for outputting data specific to the motor drive is provided inside the bag. (3) is an accessory (strobe) for flash photography, and a data output device (30) for outputting data specific to the strobe is provided inside. (4) are lens accessories such as intermediate rings and bellows;
A data output device (40) for outputting lens accessory-specific data is provided inside the lens accessory. (5) is an interchangeable lens, and inside this is a data output bag that outputs data specific to the interchangeable lens! (50) are provided. Camera body (1) and accessories (2), (3)
, (4) and accessories (4) and (5) are electrically connected by terminals (a) to (f), respectively. Here, as described later, terminals (a), (
Electric power, reference clock pulses, address data, and reset signals are supplied from the camera body (1) to the data output devices of each accessory via channels b), (C), and (d), respectively. In addition, each accessory can be connected via terminal (e).
Data unique to each accessory is supplied to the camera body (1) from the data output device. Terminal (f) is a ground terminal.

FIG. 2 is a block diagram of the central control circuit (10) of the camera body (1). (11) is a power supply control circuit which supplies power from a terminal (a) to a data output device (50) of an accessory such as an interchangeable lens (5). (SWI) is a switch that is closed when the lens (5) is attached to the camera body (1). (SW2) is a release switch for starting exposure control operation, and (SW3) is a photometry switch for starting photometry operation. For example, when the release button is pressed,
The photometric switch (SW3) is closed in the second stage, and the release switch (SW2) is closed in the second stage. The photometry switch (SW3) may close in response to a change in resistance of a pressure sensitive element caused by a current flowing through the user's finger or pressure from the finger when the user's finger touches the release button. (12) is a timing circuit, and a switch (SW
Based on the closing signals of I), (SW2), and (SW3), timing signals are given to the address output device (13) and external data input device (14) to control the timing of address data output and data capture, respectively. In addition to controlling
A reference clock pulse is supplied to the terminal (b) and a reset signal is supplied to the terminal (d). The address output device (13) is controlled by the timing circuit (12) and serially outputs address data every l bit from a terminal (C). The data input device (14) reads each accessory-specific data that is input in series for each pin from the terminal (e), converts it into parallel data, and sends it to the arithmetic circuit (15).
Send to. The arithmetic circuit (15) calculates data for exposure control, etc. based on the above data, and sends the data to the aperture control device (16), the aperture control device (17), and the display device (18), respectively. .

Table 1 is a table showing an example of the contents of a ROM that is provided for each data output device of each accessory and records data unique to each accessory.

Table 2 is a table showing the relationship between the above data output from the ROM and the meaning of the data. In Table 1, the upper two bits (a6) and (a5) of the address data are data indicating whether to select an accessory with, that is, a ROM with, and if the selected accessory is an interchangeable lens, "I O ”, in the case of a strobe, it is “O1”, and in the case of a lens accessory, it is Pa11”. Also, if it is not shown in Table 1 or if it is a motor drive, ' o
o”.

The lower 5 hints (a4) to (aO) of address data are R
This specifies the address of OM. Next, input data when various accessories are installed will be explained based on Tables 1 and 2. Focal length 5Qmm, open aperture F1
．． 4. A case will be explained in which a lens capable of outputting distance information corresponding to the lens extension λ is attached in addition to the minimum aperture value F16.

First, as mentioned above, data specific to the lens is output from the lens in the upper 2 bits of address data (aO
), (a5) is 'IO'.

When the lower 5 bits (a4) to (aO) become 'ooooo', the interchangeable lens sends a check code ""l 1 indicating that the lens is attached to the camera body (1).
Data of 100"' is output. Therefore, if the address "' l OOOO00" is specified from the camera body and the data of "'11100" is input to the camera body (1), it means that an interchangeable lens is attached. can be confirmed.

Similarly, as shown in Table 1, “OI OOOO
If the data “11100” is input to the camera body when “O” is specified, it means that the strobe is attached, and when “1100000” is specified, “111
If data of 00'' is input to the camera body, it means that the lens accessory is attached.

Next, when the address "1000001" is specified, it means that the address of the ROM where the data of the open aperture Avo is stored is specified, and the data "'00010'" of Fl, 4 is the address of the camera body. sent to. Then °
When the address '1000010' is specified, the minimum aperture A vmax, for example, data '01111' of Fl6 is sent. This data corresponds to Fl6 as shown in Table 2. When the address "lO00011" is specified, a signal indicating whether the attached lens is configured to output distance information is output. For example, 5QmmF in Table 1
In the case of a 1.4 lens, since it is a lens that outputs machining distance information, data of ``o o o o o'' is output, while on the other hand, 28
In the case of a mmF2 lens, no distance information is output, so data of "00001" is output.

Next, when the address “”+000100” is specified, it means that the address of the ROM in which focal length data is recorded is specified.For a 50mm F1.4 lens, the focal length is 50mm, so from 40 to 60mm. Data "'00110" indicating that the focal length is within the range is output.Furthermore, data on the amount of lens protrusion, which will be described later, is used as address data of the lens ROM.
The distance information is output based on this address data. If the total extraction data is ``l 0000'', the address 1010000'' is specified and the data corresponding to distance beauty ``'+1111'' is output, and if the extraction amount data is ``11111'', the address ``IO'' is specified.
+1111" is specified, and data "00111"' corresponding to a distance of 1.4 m is output.

Next, if a strobe is attached, as with the lens, when the address "'0100000" is specified, a check code "11100" is entered into the camera body, confirming that the strobe is attached. be done. Next, the address "0100001" is specified. This address stores the data of the minimum guide number, for example, the data of guide number 1.4 '00
010" is output. Next, "0100010"
When the address of ``'01000+1'' is specified, the data of the maximum guide number is stored in this address, and for example, the data of guide number 28 ``10010'' is output.Next, the address of ``'01000+1'' is specified. and,
This address stores data on light distribution characteristics,
In this example, data "OOOO1" is output. This data indicates that the vertical direction is 45° and the horizontal direction is 60°.

'1100 if lens accessories are installed
When the address ``000'' is specified, the check code 11100'' is input into the camera body, it is confirmed that the lens accessory is attached, and the ``I
When the address “0OOl” is specified, °“00
If the data of ``011'' is input, it is confirmed that the teleconverter is installed.As shown in Table 2, if the data is ``OO001'', the bellows is installed, and if the data is ``00010'', it is confirmed that the teleconverter is installed. Reverse adapter, °“
00100'', it is confirmed that the intermediate ring is attached.

Although not shown as an example in Table 1, if a winder (motor drive) is installed, the winder will use the upper 2 bits (a6
), if (a5) is 'o o', data unique to the winder is input to the camera body.

And, like other accessories, "ooooo."

If you specify the address 000'', the check code °
'11100' is input into the camera body and °°0000
When the address ``001'' is specified, data on the number of images that can be taken per second (frame speed) is input.As shown in Table 2, the data is ``oooo''.

If it is 7, it is 1 frame/second, and if it is 01100, it is 7 frames/second.

Figure 3 shows the address output device 1 (on the camera body (1) side).
FIG. 3 is a circuit diagram showing specific examples of a part of the circuit of +3), a part of the circuit of the data input device (14), and a data output device of each accessory. Note that an interchangeable lens is shown as an example of an accessory. Further, FIG. 4 is a time chart of FIG. 3. In FIG. 3, (OSC) is a reference clock pulse output circuit. A clock pulse (CP in FIG. 4) from this circuit (OS C) is also sent to the lens (5) via the terminal (b). (CNTI) is a counter that counts zero pulses (cp), and (DEC
I) is the output (CBO) of the counter (CNTI), (CB
This is a decoder that decodes the data of I) and (CB2), and the output of this decoder is the data of (TBO) to (TB
The timing signal is shown in 7). In addition, the counter (CNT2) and decoder (DEC2) provided on the lens (5) side are replaced by the counter (CNT2) on the camera body (1) side.
I) and decoder (with the same configuration as DH(1), this decoder'
The output of the -da (DEC2) is ('TLO) ~ (T in Figure 4).
This is the timing signal shown in L7).

The outputs of the two decoders (DECI) and (DEC2) are connected to a counter (C) that counts the same clock pulses (CP).
NTI) (CNT2) Since the Q output is decoded,
The same timing signal is output, and the circuits on the camera body (1) side and the lens (5) side are synchronized. Table 3 shows the counter (CNT1), (CNT2) and decoder (DEC
The relationship between the outputs of (DEC2) and (DEC2) is shown below.

When the camera body outputs a reading start signal, the flip
The value 70 (Fl) is set (FIQ in FIG. 4), and the reset state of the counter (CNTI) is released.

As a result, the counter (CNTI) starts counting σ pulses, and the decoder (DECl) starts outputting timing signals (TBO) to (TB7). In addition, the counter (CNTI).

When the output of (CNT2) is 'ooo'-, the decoder (D
AND circuit (AN2) of (ECl), (DEC2), (A
Since the output to the counter (CN6) is “High”, the AND circuits (AN2) and (AN6)
Only after T1) and (CNT2) start counting, the “High” level timing signals (TBO) and (
TLO) is provided so that it is output.

First, in the step (SO) in FIG. 4 (from when the read start signal is output until the first timing signal (TB7) is output), the register Address data "' l OOOOOO" is latched in (REGI), and further (TB
7) timing signal is output and the AND circuit (A
This data is latched into the shift register (SRI) at the timing when the output of the NII) falls to "Low". During this step (SO), the Q output (F2Q in Figure 4) of the clip-flop (F2) is at LOV''', so other circuits do not operate.The transition from (SO) to step (Sl) occurs. In other words, when the ninth clock pulse (cp) is counted, the output (C84) of the counter (CNTI) rises to 'High' (Fig. 4, 5bo).
), the D input of 7 lips and 70 tubes (F2) is taken in, and the Q output becomes "High" (Figure 4, 5bo).
). As a result, the gate of the AND circuit (ANI) is opened and a clock pulse is supplied to the shift register, and the circuit on the lens (5) side is released from the positive state via the terminal (d). The shift register (SRI) outputs the latched address data "'1000 o o o" to the terminal (C) in synchronization with the rising edge of the clock pulse.
Each bit is sequentially output in series. This output data is sequentially taken into the shift register (SR3) on the interchangeable lens (5) side in synchronization with the falling edge of the clock pulse, and is output to the terminals (Lad) to (La4) (
Figure 4 (Lad)-(La4)). And the terminal (TL
5) becomes °l High”, the terminal (
The outputs of La4) and (La3) become '10', the output of the AND circuit (AN5) becomes 'H'1gh', and the Q output of the flip 70 tube (F3) receives this output as the D input. becomes 'High' (Figure 4, 5bo).

Decoder (DEC2) terminal (TL7) on the lens (5) side
) rises, the shift register (SR3
) output terminals (La4)-(Lad) are the lower 5 bits of the address data (“ooooo” in the case of SL step), and the data is the address “o o o o o” of the ROM (51). is specified. As a result of this address designation, the data of the aforementioned check code "l1100" is output from the ROM (51).

The above data from this ROM (51) is transferred to the terminal (TL7).
) is latched into the shift register (SR4) at the rising edge of the signal.

Since the Q output of the flip-flop (F3) is "High" at the time of the timing pulse (TL5),
When the next timing pulse (TLO) rises to ``High'', the flip 70 tube (F4) takes in the Q output of the 7 lip 70 tube (F3) and changes the Q output to ``High''.
'' (FIG. 4, 5bo). As a result, the switch circuit (CS) becomes conductive and becomes capable of outputting the data ``11100'' to the terminal (e).

The data taken into the shift register (SR4) is output in the order of '11100' to the terminal (e) via the switch circuit (GS) in synchronization with the clock pulse, and on the camera body (1) side, the falling edge of the clock pulse is output. This data is taken into the shift register (SR2) in synchronization with (FIG. 4, 5bo-Bb4).

At this time, the flip 70 knob (F5) is the flip
Since the Q output of the 70 tube (F2) is "High", the next timing pulse (TBO) is "'High".
” (TBO rises at S2 step)
, its Q output is 'High'. Therefore,
The gates of the AND circuits (AN3) and (AN4) are open after the S2 step.

Then, at the rising edge of the timing pulse (TBS), the output of the shift register (SR2) is launched into the register (REG2).

In the step S2, the above-mentioned data 11100''
At the same time, the next address data “100
0001” to the lens (5), and in step S3, the lens data “O
OOI O'' is transferred to the camera body, and the next address data ``■ooooio'' is transferred to the lens (5), and addresses and data are transferred in the same manner.

As shown in Table 1, the upper address of the lens is “lO”
Therefore, this is determined by the data output device (50) of the lens (5) and the switch circuit (GS) is turned on, but in the case of other accessories such as strobes, lens accessories, motor drives, etc. , as shown in FIG. 5, the input voltage level of the input terminal of the AND circuit (AN5) is changed corresponding to each accessory. That is, in the case of a strobe, the upper address data is "O1", so when this signal is input, the output of the AND circuit (AN5-1) becomes "Hi".
In the case of a lens accessory, it is "11", so the AND circuit (AN 5-2) is "High", and in the case of a motor drive, it is "o o", so the output of the AND circuit (AN 5-3) is "High". The other circuit configurations in these accessories are the same as the internal circuit configuration of the lens (5).

In the circuit shown in FIG. 3, it is needless to say that the camera body (1) needs to be reset by a power-on reset signal when the power is turned on.

In addition, a power-on reset signal generation circuit is provided inside each accessory, and a power-on reset signal is generated when the accessory is connected to the camera body (1) and power supply starts to the data output device of the accessory. In this way, it is also necessary to reset the circuitry inside the accessory.

In addition, in the case of accessories such as lens accessories, which have only a small number of types of data to be fixedly stored and which are produced in small quantities, the ROM installed inside the accessory may be a programmable ROM or a fuse ROM suitable for small-volume production.
etc. may also be used.

Alternatively, the wiring may be performed using a wiring pattern on a printed circuit board or wiring by soldering.

FIG. 6 shows a part of the address output device (I3) that sends address data to the register (REGI) in FIG.
and a register (RE) in the data input device (14).
FIG. 2 is a circuit diagram of a portion that reads data from G2). When the photometric switch (SW3) is closed, the power supply transistor (BTI) becomes conductive, and the capacitor (C1) and resistor (R
The power-on reset signal (power-on reset signal FOR) is output from the power-on reset circuit consisting of
F43) and the counter (CNT5) are reset.

Also, when the photometric switch (SW3) is closed, the output of the inverter (INI) becomes 'High', the gate of the AND circuit (AN40) is opened, and the frequency divider (DI
), the clock pulse (CP) is input to the frequency divider (D
I) outputs a pulse with a constant period obtained by dividing the clock pulse, and a one-shot circuit (osl) outputs a read start signal at every constant period. Therefore, in this embodiment, while the photometry switch is closed, the data from the accessory is automatically read periodically, so that the switch (S1) in FIG. There is no need for a switch to detect that an accessory is attached.

First, the operation of sending address data to the register (REGI) in response to a read start signal will be described. When the read start signal is output, the flip-flop (F2O), (
F41) is set and the AND circuit (AN41), (A
The gate of the counter (CN42) is opened and the counter (CN42) is opened.
T6), (CNT7), and (CNT8) are reset. Then, in the (SO) step, the output of the counter (CNT5) becomes "O" at the timing pulse of (TBO).
l'', and the flip-flop (F2O) is reset at the falling edge of this timing pulse (TBO),
After that, the counter (CNT5) receives a timing pulse (TB
O) will no longer be input. Then, as mentioned above, at the rising edge of the timing pulse (TBI), the register (REGI) is
)1, counter (CNT5) and multiplexer (MP
The output of 2) is latched as address data, but at this time, the output of the counter (CNT5) is '01' and the output of the multiplexer (MP2) is 'o o o o o
"Therefore, the address data launched into the register (REGI) is °' l O00000", which is the leading address of the lens. In addition, the counter (CNT5)
The output of is input to the register (REGI) with the front and rear of the output bit reversed. Here, when the counter (CNT5) is O1'°, the multiplexer (MP2) inputs the input data (α) to the multiplexer (MP2).
, when “lO”, (β), and when 11”, (γ
) are output respectively.

At the rising edge of (TB2), the counter (CNT6) counts up by one via the AND circuit (AN42) and reaches "0".
1". Then, in the next step (Sl), at the rising edge of (TBI), the register (REGI) is set to "'".
The address data of 1000001″′ is latched and (
At the rising edge of TB2), the output of the counter (CNT6) is 'o'.
to”.

Thereafter, the same operation is repeated, and the address data of the lens is sequentially fetched into the register (REGl). Then, in step (S4), the address data of "'1000100'" (
The final address of the lens) is latched in the register (REGI), and when the output of the counter (CNT6) reaches 101 at the rising edge of (TB2), the output of the AND circuit (AN56) rises to "High". One-shot circuit (
A pulse is output from O32). This pulse causes
Flip-flop (F4) via OR circuit (OR6)
1) is reset, the flip-flop 70 knob (F2O) is set via the OR circuit (OR5), and the flip-flop (F42) is directly set.

In step (S5), the output of the counter (CNT5) becomes "'10" at the rising edge of (TBO), and the data of (β) is output from the multiplexer (MP2).

Therefore, at the next rising edge of (TBI), register (REGI)
) is latched in the address data “0100000
”, which becomes the strobe's first address. Then,
(TB2) timing pulse is AND circuit (AN43)
) is sent to the counter (CNT7), and its output becomes '001'.Then, by repeating the same operation, (
In step S8), '01 at the rising edge of (TBI)
The address data of “00011” (the final address of the strobe) is latched in the register (REGI), and the next (TB
2), when the most significant output bit of the counter (CNT7) becomes "High" (output is '100'), a 'High' pulse is output from the one-shot circuit (053). This pulse resets the clip 70 tube (F42) via the OR circuit (OR7),
Flip 70 tube (F) via OR circuit (OR5)
40) is set, and then a flip 70 knob (F
43) is set directly. As a result, the gate of the AND circuit (AN43) is closed and the gate of the AND circuit (AN41) is closed.
), (AN44) gates are opened.

In step (S9), the output of the counter (CNT5) becomes 'It' at the rising edge of (TBO), data of (γ) is output from the multiplexer (MP2), and at the rising edge of (TBI), the output of the counter (CNT5) becomes 'It'. The address data '+100000' (the leading address of the lens accessory) is latched into the register (REGI). And (TB2
At the rising edge of ), the output of the counter (CNT8) becomes "O1", and in step (S10), the address data of '1100001' is latched into the register (REGI) at the rising edge of (TBI). At the rising edge of CNT8, the upper bit of the counter (CNT8) becomes
h” (output is '10'), one-shot circuit (
053) outputs a 'High' pulse. This pulse resets the flip 70 block (F43) and closes the gate of the AND circuit (AN44), and then through the OR circuit 1 (OR5). The flip 70 tube (F2O) is set and the gate of the AND circuit/AN40) is opened.Then, in step (Sll), the counter (CNT5) is opened by the timing pulse (TBO).
) is “l l” to “OO” l: Output changes,
At the fall of the timing pulse (TBO), the flip-flop (F2O) is reset and the AND circuit (AN40
) gate is closed. With the above operation, the operation of outputting the address data is completed, and a state is entered in which it waits for the next read start signal to be output from the one-shot circuit (O31).

Next, the operation of reading the data read into the register (REG2) into the registers (REG3) to (REGl3) will be described. The counter (CNT9) is reset by the read start signal and counts timing pulses (TB2). Then, the output of the counter (CNT9) is input to the decoder (DEC3), converted to outputs (dO) to (dlo) as shown in Table 4, and output to the decoder (DEC3).
3) is output.

As mentioned above, in steps (So) and (Sl),
Since data from the accessory has not yet been read into the register (REG2) (Figure 4), the decoder (DEC
All outputs of 3) are "'Low"'.

Therefore, the gates of the 121 circuits (AN45) to (AN55) are closed and the registers (REG3) to (REGI3) are closed.
No data import operation is performed. In step (S2), the first data is taken into the register (REG2) at the rising edge of (TBS). Here, the terminal (dO)
is “High”, the AND circuit (AN4
The gate of 5) is opened, and the data latched in the register (REG2) is latched in the register (REG3) at the next rising edge of (TB6).

Similarly, the data from the register (REG2) is sequentially taken into the registers (REG4) to (REGI3) via the AND circuits (AN46) to (AN55) at the rising edge of the timing pulse (TB6:M7). Then, in step (S12), the timing pulse of (TB6) via the AND circuit (AN55) is used to register (REG)
When the last data is latched in I3), it means that the read operation has finished, so the timing pulse (TB6) from this AND circuit (AN55) is simultaneously sent to the circuit in Figure 3 as a read end signal, and the read operation is completed. The operation ends. Various data from the accessories are loaded into these registers (REG3) to (REGI3) and are used for exposure control operations and the like.

Fig. 7 shows the circuit configuration of the address output device and data input device when reading only data from the interchangeable lens, and is also a circuit diagram of the camera body (1) side in which distance information is also read from the interchangeable lens. It is. Lens (5)
When the is attached and the attachment switch (swl) is closed,
After a certain period of time, the delay circuit (DL)
) becomes “High”. This delay time is set to a time required for the signal pin contact portion between the lens and the camera body, which will be described later, to stop chattering and become stable. Then, the photometric switch (SW3) is closed and the AND circuit (AN) is connected via the inverter (INS).
When the output of 61) becomes l High II, a read start signal is output from the one-shot circuit (O35) via the OR circuit (ORII), and the read operation is started.

In addition, when the AND circuit (AN61) becomes "High", the gate of the AND circuit (As2O) is opened and the clock pulse (CP) is input to the frequency divider (DI), and the pulse with a constant period is transmitted to the frequency divider (DI). DI). Therefore, similarly to FIG. 6, the reading start pulse is sent to the one-shot circuit (O
8I) and is outputted via the OR circuit (ORII).

The photometry switch (SW3) is closed and the capacitor (CI
) and a resistor (R1) output a power-on reset signal (FOR), the flip-70 tubes (F50) and (F51) are reset. The multiplexer (MP3) receives data from (X) when the input to the (SE) terminal is “Low”.
When it is "High", data from (Y) is output, so when the photometric switch (SW3) is closed and the reading operation starts, the Q of the D flip-flop (F50) is output. The output is II L o, 11, and the data from (X) is output.In the (SO) step, the Q output of the D flip 70 tube (F2) in Figure 3 remains "Low". Therefore, the counter (CNTI
I) remains in the reset state and its output is °'oo
o”. Therefore, the multiplexer (MP3)
Data of "1000000" is output from the register (REGI), and this data is latched as address data into the register (REGI) at the rising edge of the timing pulse (TBI). This data is the leading address of the interchangeable lens (5).

(Sl) step, the Q output of the D flip-flop (F2) in Figure 3 becomes "High'", the reset state of the counter (CNTII) is released, and the timing pulse (TBO) counts by one. It was uploaded°'0
01” is output, and the multiplexer (MP3) outputs “
l OO0001” is output. This data is (T
It is latched into the register (REGI) at the rising edge of BI). (s2) At step, counter (CNTII)
The output becomes '010', and the output terminal (eo) of the decoder (D, EC5) becomes 'High' as shown in Table 5. Table 5 shows the decoder that decodes the count contents of the counter (CNTII). (DEC5) input/output relationship is shown.

Then, at the rising edge of (TBI), the register (REGl) is
The data ``1000010'' is latched as an address. On the other hand, the first data ``+1100'' (check code) is input to the register (REG2) (Figure 3), and the timing pulse of (TB6) is input to the AND circuit (
This data is output from the register (RE
Gl5). (S3) In step (S3), (T
At the rising edge of BO), the output of the counter (CNTII) becomes 01.
1", and the terminal (el) of the decoder (DEC5) becomes "
'High' and the gate of the AND circuit (AN64) is opened. Then, at the rising edge of (TBI), '1000011' is latched as address data in the register (REGI), and at the rising edge of (TB6), the open aperture value is set. (
The data of A vo) is launched into the register (REG l 6) via the register (REG 2).

In step (S4), the output of the counter (CNTIl) becomes "l OO" at the rising edge of (TBO), and '+000' is stored in the register (REGI) at the rising edge of (TBI).
100" data is latched as address data. Then, at the timing of the rising edge of (TB2), the Q output of the D flip 70 tube (F2O) becomes "High", and the multiplexer (MP3) thereafter outputs the (Y) data. Data will now be output.

This (Y) data indicates the amount of extension of the interchangeable lens (5), and the amount of extension is detected on the camera body (1) side by a mechanism described later. Here, taking advantage of the fact that the relationship between the amount of extension of each interchangeable lens (5) and the distance at which the focus has been adjusted is constant for each interchangeable lens, the ROM of each interchangeable lens (5) contains a table. As shown in FIG. 1, distance data is fixedly stored in correspondence with the above-mentioned feed-out amount data. Therefore, if the data of the extension amount detected on the camera body (1) side is specified as the address of the ROM (51) in the interchangeable lens (5), the distance data stored at that address will be The data is taken into the camera body (1) and distance data can be obtained.

Reference numeral (55) denotes a member provided on the side of the interchangeable lens (5), which moves in the left-right direction in the figure in conjunction with a focus adjustment member (not shown, for example, a distance ring) of the interchangeable lens (5). (70) is provided on the camera body (1) side, and the member (55) has a spring (
The member (55) is in contact with the member (55).
It moves left and right as it moves. This camera body (
1) side member (70) includes guide pins (72) and (73).
) and is supported by a plan (74) as an electrical contact point.
, (75), (76), (77), and (78) are provided, and all the contacts are electrically connected. (80) is a code board, the blacked out part is the electrode, and the electrode (80) is the code board.
,1) are connected to ground, (82), (83), (8
4) and (85) are each connected to the power supply (+E) via a resistor.

Contacts (74), (75) provided on the member (70),
For example, when (76), (77), and (78) are in the position (g), the outputs of terminals (r3) to (fO) are “00”.
01"", and the output of the multiplexer is "'1010
001". Therefore, the attached interchangeable lenses are shown in Table 1.
For a 50mm F1.4 lens, the data ``01101'' for 4 m will be output from the interchangeable lens, and for a 135 mm F3.5 lens, the data ``10110'' for 19 m will be output from the interchangeable lens.

Also, when the contacts (74) to (78) come to the position (h), "tool" is detected through the terminals (f3) to (fO), and the multiplexer (MP3) outputs "'101100".
1" address is output, and if it is 50mmF1.4, the data of 0.6m "OOOI O" is output, and 135mmF
3.5, data of 2.5m "01010" will be output.

In step (S4), the terminal (e) of the decoder (DEC5)
2) is set to °'High, the timing pulse of (TB6) is output from the AND circuit (AN65), and the minimum aperture data (A vm) is stored in the register (REGI7).
latched to. In the following step (S5), lens type data is latched in the register (REGI8), and (
In step S6), the focal length data is stored in the register (R
EGI9). In step (S7), the output of the counter (CNTII) becomes "ill", the output of the AND circuit (AN62) rises to High, the flip 70 tube (F51) is set, and the AND circuit (AN68) The gate of (TB6) is opened, and the distance data is latched into the register (REG20) at the rising edge of (TB6), and at the same time, the distance data from (TB6) from this AND circuit (AN68) is latched.
The pulse is sent to the circuit of FIG. 3 as a read end signal.

If the photometry switch (SW3) remains closed even after reading is completed, the one-shot circuit (O3) will close after a certain period.
1) outputs the next reading start signal. At this time, the Q output of the clip 70 tube (F2O) and (F51) is H
Since it remains "high", only the data according to the feed amount is output from the multiplexer (MP3) to the register (REGI) in the (SO) step, and the distance data is launched to the register (REG20) in the (S2) step and the read operation is performed. In other words, when the photometry switch (SW3) continues to be closed, only the distance information is read repeatedly.Therefore, in the case of this embodiment, the minimum aperture of the interchangeable lens, etc. is fixed. The information is read only once, and the variable information such as distance information (other than that, for example, focal length information of a zoom lens, setting aperture information) is read repeatedly.

In FIG. 3, the shift register (SRI) for outputting address data and the shift register (SR4) for outputting accessory data are constructed as shift registers with 7 hint inputs or 8 bit inputs. For example, in the case of 8-bit input, these shift registers read the data input in parallel at the rising edge of timing (TB7) and (TL7), and then read the data input in parallel at the rising edge of timing (TB7) and (TL7).
) to (TB7) and (TLO) to (TL7), the data is sequentially output from the most significant bit to the output terminal (O
output in series to UT). A shift register that performs such an operation has the following circuit configuration. First, eight flips and 70-tubes are provided for each bit, in which the data of each bit input in parallel is preset. Then, it is connected to the output terminal of the flip-flop corresponding to the lower hint or to the input terminal of the free knob 70 knob corresponding to the bit immediately above the lower bit. By doing so, the data preset in each of the seven flip-flops is sequentially transferred from the lower bits to the upper bits in synchronization with the clock pulse. Further, the output terminal of the 70-tube flip-flop to which the data of the most significant bit among the eight is preset is connected to the input terminal of another ninth flip-flop.

The output terminal of this ninth flip-flop is used as the output terminal of the shift register. By doing this, 9
The 7th flip-flop (a flip-flop that is preset with the most significant hit data in synchronization with the clock pulse)
By taking in the output of the prop, data is output with a delay of exactly one clock pulse.

Effects As described above, according to the present invention, when a signal instructing data communication is input from the camera body, in response, the flash device transmits a plurality of unique data such as light emission amount and light distribution characteristics to the camera. Since data is transmitted in series based on the clock input from the camera body, the number of terminals between the camera body and flash device can be significantly reduced compared to when multiple data are communicated in parallel. , is reasonable.

Furthermore, since the data is sent as digital data, there is no need for an A10 conversion circuit or the like in the circuit section of the camera that reads it, which simplifies the configuration of the camera body.

Comb 1.1ri, b) Ilk revision of the specification (no change in content) Engraving of the statement (no changes to the contents) Engraving of Memorandum A (no changes to the contents) Table 2 ROM content data table Details Zcr) Engraving (no changes to the contents) Table 2 (continued) '　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　Table 3 Table 4 Table 5

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the principle of the present invention, Figure 2 is a block diagram showing the circuit configuration of the camera body, and Figure 3 is a part of the data input/output section on the camera body and data on the accessory side. A circuit diagram showing the circuit with the output device, Fig. 4 is a time chart showing its operation, and Fig. 5 shows other accessories.
6 is a circuit diagram showing an example of the connection to the camera main body side of FIG.
FIG. 7 is a circuit diagram showing another embodiment of FIG. 6. 1: Camera body, 3: Flash device, 51: Data output means, 5R3-1, AN5-1: Command signal input means, b: Clock input means, SR4: Sending means. Applicant Minolta Camera Co., Ltd. Procedural Amendment (Method) 1. Display of the case 1986 Patent Application No. 318899 2, Name of the invention Flash V device with data transmission function 3, Person making the amendment Relationship to the case Applicant address 2-3-13 Azuchi-cho, Chuo-ku, Osaka, Japan Kokusai Building [Administrative division change on February 13, 1989] March 3, 1999
1st (Delivery date: April 25, 1999) 5. Column 6 of "Detailed description of the invention" of the specification to be amended, Contents of the amendment

Claims (1)

[Claims] (1) In a flash device that is detachably attached to the camera body, a data output means that outputs multiple types of data including light distribution characteristics and light emission amount, and a command that inputs a signal from the camera body that commands data communication. A flash device comprising a signal input means, a clock input means for inputting a clock from a camera body for reading the data, and a sending means for sending the data in series to the camera body in synchronization with the clock.