JPH0223643A - Pretreatment of component lead - Google Patents
Pretreatment of component leadInfo
- Publication number
- JPH0223643A JPH0223643A JP63174049A JP17404988A JPH0223643A JP H0223643 A JPH0223643 A JP H0223643A JP 63174049 A JP63174049 A JP 63174049A JP 17404988 A JP17404988 A JP 17404988A JP H0223643 A JPH0223643 A JP H0223643A
- Authority
- JP
- Japan
- Prior art keywords
- component
- component lead
- preliminary soldering
- plating
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005476 soldering Methods 0.000 claims abstract description 25
- 238000007747 plating Methods 0.000 claims abstract description 18
- 239000004065 semiconductor Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 8
- 238000002203 pretreatment Methods 0.000 claims description 5
- 238000007781 pre-processing Methods 0.000 claims description 4
- 239000006193 liquid solution Substances 0.000 claims 1
- 239000000203 mixture Substances 0.000 abstract description 3
- 229910000679 solder Inorganic materials 0.000 description 17
- 239000010931 gold Substances 0.000 description 13
- 238000007598 dipping method Methods 0.000 description 5
- 229910001128 Sn alloy Inorganic materials 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 230000032258 transport Effects 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/79—Apparatus for Tape Automated Bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3468—Applying molten solder
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Molten Solder (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
半導体装置等の電子部品をプリント基板にハンダ付は実
装する際に適用される部品リードの前処理方法に関し、
部品リードに対する前処理、即ち予備ハンダ付は工程の
効率化を目的とし、
へＵメッキが施された前記部品リードを先ずＳｎディッ
プ槽に浸漬して第１回目の予備ハンダイ１番ノを行い、
次にこれをＩｎ−５ｎディップ槽に浸漬して第２回目の
予備ハンダ付けを行うようにしたことを特徴とするもの
である。[Detailed Description of the Invention] [Summary] Regarding a component lead pretreatment method applied when soldering or mounting electronic components such as semiconductor devices on a printed circuit board, pretreatment of component leads, that is, preliminary soldering is For the purpose of streamlining the process, the U-plated component leads were first immersed in an Sn dip bath and subjected to a first preliminary soldering process.
This is then immersed in an In-5n dip bath for second preliminary soldering.
本発明は部品リードにＡｕメッキ（金メッキ）が施され
た半導体装置等の電子部品をプリント基板に実装する際
に適用される部品リードの前処理方法に関する。The present invention relates to a method for preprocessing component leads that is applied when mounting electronic components such as semiconductor devices whose component leads are plated with Au (gold plating) on a printed circuit board.
最近は部品実装の高密度化が進み、接続部（ハンダ付は
部）に加わるストレスは益々大きくなる傾向にある。そ
のため、実装に用いるハンダも、疲労強度の低い従来の
５ｎ−Ｐｂ （錫−鉛）系ハンダから、融点が低いこ
とからステンプソルダリングが可能で、かつ疲労強度の
高いインジウム系のハンダ（Ｉｎ＝５２質量％、 ５ｎ
＝４８質量％のハンダであって、以下これをＩｎ−３ｎ
ハンダと呼ぶ）に移行しつつある。しかしこのＩｎ−５
ｎハンダは、Ｉｎと八〇が金属間化合物を形成する過程
でボイドを発生したり、或いはハンダ流動性が悪化して
強度劣化を起こす等の欠点があるため、実装前に部品リ
ード側のＡｕを除去しておく必要がある。Recently, the density of component mounting has increased, and the stress applied to the connection parts (soldered parts) has tended to increase. Therefore, the solder used for mounting has changed from the conventional 5n-Pb (tin-lead) solder, which has low fatigue strength, to the indium-based solder (Indium), which has a low melting point, allows stamp soldering, and has high fatigue strength. =52% by mass, 5n
= 48% by mass of solder, hereinafter referred to as In-3n
solder). However, this In-5
N-solder has drawbacks such as voids being generated during the process of In and 80 forming an intermetallic compound, or poor solder fluidity resulting in strength deterioration. need to be removed.
本発明はＩｎ−３ｎハンダを用いて部品実装を行う際に
適用される部品リードの前処理方法に関するもので、部
品リード上の＾Ｕメッキの除去を効率化した点にその特
徴がある。The present invention relates to a component lead pretreatment method applied when mounting components using In-3n solder, and is characterized by efficient removal of ^U plating on component leads.
第３図は半導体装置の実装構造を模式的に示した要部側
断面図である。FIG. 3 is a side sectional view of a main part schematically showing the mounting structure of a semiconductor device.
部品リード１０にＡｕメッキ（図示せず）が施された半
導体装置２０の実装は、
■、 Ａｕメッキされた部品リード１０をＩｎ−３ｎハ
ンダに浸漬して＾Ｕを槽内のＩｎ−３ｎハンダに拡散さ
せて除去する。Mounting of the semiconductor device 20 in which the component leads 10 are plated with Au (not shown) is as follows: 1. Dip the Au-plated component leads 10 into In-3n solder and insert the In-3n solder in the tank. Diffuse and remove.
■１部品リート１０のＡｕメッキ除去を行った半導体装
置２０を第３図に示す如く矢印方向に移動させ、部品リ
ード１０をプリント基板５０側のパッド１５上に位置決
めする。(1) The semiconductor device 20 from which the Au plating of the component lead 10 has been removed is moved in the direction of the arrow as shown in FIG. 3, and the component lead 10 is positioned on the pad 15 on the printed circuit board 50 side.
■、雰囲気温度を上げてＩｎ−３ｎハンダで構成された
パン１１Ｇを溶融させ、該バンプ１６によって両者を接
合する。(2) The ambient temperature is raised to melt the pan 11G made of In-3n solder, and the bumps 16 are used to join the two.
といった手順でこれを行っていた。This was done in the following steps.
しかしながら、前記Ｉｎ−３ｎハンダはＡｕの拡散速度
が遅いため、上記従来の方法では部品リード１０のＡｕ
メッキの除去に多大の工数が必要である。本発明の目的
は、このＡｕメッキを短時間で除去する方法を提供する
にある。However, since the In-3n solder has a slow diffusion rate of Au, the conventional method described above
A large number of man-hours are required to remove the plating. An object of the present invention is to provide a method for removing this Au plating in a short time.
本発明による部品リードの前処理方法は、第１図の実施
例図に示す如＜、Ａｕメッキ２が施された前記部品リー
ド１０を先ずＳｎディップ槽３に浸漬して第１回目の予
備ハンダ付けを行い、次にこれをＩｎ−Ｓｎディップ槽
４に浸漬して第２回目の予備ハ〔作 用〕
本発明によれば、第１回目の予備ハンダ付けによって部
品リード１０上のＡｕメッキがＳｎ中に拡散して効率的
に除去され、第２回目の予備ハンダ付けによって部品リ
ード１０上にバンブ１６と同一組成のＩｎ−３ｎ層が形
成されるので、部品実装時の条件も著しく改善される。The component lead pretreatment method according to the present invention is as shown in the embodiment diagram in FIG. According to the present invention, the Au plating on the component lead 10 is removed by the first preliminary soldering. It diffuses into the Sn and is efficiently removed, and an In-3n layer with the same composition as the bump 16 is formed on the component lead 10 by the second preliminary soldering, so the conditions during component mounting are significantly improved. Ru.
以下実施例図に基づいて本発明の詳細な説明する。 Hereinafter, the present invention will be described in detail based on embodiment figures.
第１図（ａ）と（ｂｌは本発明の−・実施例を工程順に
示した模式的要部側断面図であるが、前記第３図と同一
部分には同一符号を付している。FIGS. 1(a) and 1(bl) are schematic side sectional views of main parts showing embodiments of the present invention in the order of steps, and the same parts as in FIG. 3 are given the same reference numerals.
第１図（ａｌと（ｂ）に示すように、本発明による部品
リードの前処理方法は、Ａｌｌメッキ２を施した部品リ
ード１０を備えた半導体装置２０を基板プリント基板５
０（第３図参照）上に実装するに際して、その部品リー
ドｌＯに施される前処理方法に関するもので、Ａｕメッ
キ２が施された前記部品リート１０を先ずＳｎディップ
槽３に浸漬して第１回目の予備ハンダ付けを行い、次に
これをＩｎ−Ｓｎディップ槽４に浸漬して第２回目の予
備ハンダ付けを行う、というように予備ハンダ付けを２
段階に分離して行う点にその特徴がある。As shown in FIGS. 1A and 1B, in the component lead pretreatment method according to the present invention, a semiconductor device 20 having a component lead 10 subjected to All plating 2 is placed on a printed circuit board 5.
0 (see FIG. 3), the component lead 10 is first immersed in the Sn dip bath 3, and then Preliminary soldering is performed twice, such as performing the first preliminary soldering, then immersing it in the In-Sn dip bath 4 and performing the second preliminary soldering.
Its distinctive feature is that it is carried out in separate stages.
以下本発明による部品リードの前処理方法を工程順序に
従って説明する。The method for preprocessing component leads according to the present invention will be described below in accordance with the order of steps.
（１）第１回目の予備ハンダ付け〔第１図（ａ）〕Ｓｎ
デＳｎディップ槽３のＳｎディップ槽には、質量％が１
（１０％のＳｎが充填されている）中に半導体装置２０
の一方の部品リード１０を約１５秒間浸漬する。(1) First preliminary soldering [Figure 1 (a)] Sn
In the Sn dip tank of de-Sn dip tank 3, mass% is 1
A semiconductor device 20 inside (filled with 10% Sn)
One component lead 10 is immersed for about 15 seconds.
その結果、部品リート１０の浸漬部分（点線円で囲んだ
部分）のＡｕメッキ２はＳｎ中に拡散され、それに代わ
ってその表面には右側の拡大図に示ず３ＹうなＡｕ −
Ｓｎ合金層５が形成される。図中、１は部品リード１０
の母材であるリード母材、２はＡｕメッキをそれぞれ示
す。なお、この予備ハンダ付けはもう一方の部品リード
１０に対しても同様に行う。As a result, the Au plating 2 on the immersed part (the part surrounded by the dotted line circle) of the component REET 10 is diffused into the Sn, and instead, the surface is covered with 3Y-shaped Au −
A Sn alloy layer 5 is formed. In the figure, 1 is the component lead 10
The lead base material is the base material of , and 2 represents Au plating. Note that this preliminary soldering is also performed for the other component lead 10 in the same manner.
（２）第２回目の予備ハンダ付け〔第１図（ｂ）］上記
第１回目の予備ハンダ付けが終了すると、次は部品リー
ドｌＯをＩｎ−Ｓｎディップ槽４ （このＩｎＳｎディ
ップ槽には、Ｉｎ ＝ ５２質量％、 ５ｎ＝４８質景
％のＩｎ −Ｓｎハンダが充填されている）中に１２０
〜１８０秒間浸漬する。この操作により、Ｉｎと結合し
た＾Ｕの化合物はその殆どが前記ディップ槽４内のＩｎ
−３ｎ中に拡散するので、部品リード１０上のハンダの
組成はＩｎ−３ｎハンダのみとなる。このＩｎ−５ｎに
よる合金層６は、成分的に前記第３図に示したバンプ１
６と略同等な成分を持っているため、半導体装置２０を
プリント基板５０に実装する。即ち部品リード１０とパ
ッド１５とを接合する際の条件が特に良好となる。(2) Second preliminary soldering [Fig. 1(b)] After the first preliminary soldering is completed, the component lead lO is connected to the In-Sn dip bath 4 (this InSn dip bath is In-Sn solder (In = 52% by mass, 5n = 48% by mass) is filled with 120
Soak for ~180 seconds. Through this operation, most of the ^U compounds combined with In are transferred to the In in the dip tank 4.
Since the In-3n solder is diffused into the In-3n solder, the composition of the solder on the component lead 10 is only In-3n solder. This In-5n alloy layer 6 is composed of the bump 1 shown in FIG.
6, the semiconductor device 20 is mounted on the printed circuit board 50. In other words, the conditions for bonding the component lead 10 and the pad 15 are particularly favorable.
第２図は本発明の一応用例を模式的に示した要部側断面
図である。FIG. 2 is a side sectional view of a main part schematically showing an application example of the present invention.
第２図に示すように、本応用例は、Ｓｎディップ槽３と
Ｉｎ−Ｓｎディップ槽４とを一つの予備ハンダ装置６０
内に装置すると共に、半導体装置２０を保持する治具９
と、該治具９を保持してこれを所望の個所へ搬送するア
ーム４０とを具備している。As shown in FIG. 2, in this application example, the Sn dip tank 3 and the In-Sn dip tank 4 are integrated into one preliminary soldering device 60.
A jig 9 for holding the semiconductor device 20 and holding the semiconductor device 20 therein.
and an arm 40 that holds the jig 9 and transports it to a desired location.
以下この装置の動作について説明する。The operation of this device will be explained below.
■、治具９によって保持された半導体装置２０をアーム
４０がつかんでこれを矢印方向Ａ方向に移動させる。そ
して部品リード１０のみを第１のディップ槽であるＳｎ
ディップ槽３内に浸漬させる。(2) The arm 40 grabs the semiconductor device 20 held by the jig 9 and moves it in the direction of arrow A. Then, only the component lead 10 is placed in the first dipping tank.
It is immersed in the dip tank 3.
■、所定のディップ時間が経過するとアー１１４０は一
旦矢印Ｂ方向に上昇する。そして今度は保持した治具９
を矢印Ｃ方向−矢印り方向に移動さ・已てこれを第２の
ディップ槽であるＩｎ−５ｎディップ槽４内に浸漬させ
る。(2) After a predetermined dip time has elapsed, the arm 1140 once rises in the direction of arrow B. And this time, the jig 9 held
is moved in the direction of arrow C--in the direction of arrow C, and then immersed in the In-5n dip tank 4, which is the second dip tank.
■、このディップが終わるとバキュームノズル１１が作
動して半導体装置２０のみを吸着して矢印Ｅ方向に持ち
上げる。そしてこれを所定の保管場所へ移動させて収納
する。(2) When this dipping is completed, the vacuum nozzle 11 is activated to suck only the semiconductor device 20 and lift it in the direction of arrow E. Then, it is moved to a predetermined storage location and stored.
■、半導体装置２０の収納が終わると今度は前記アーム
４０が再び作動して治具９を保持し、これをスタンバイ
位置まで搬送する。(2) Once the semiconductor device 20 has been stored, the arm 40 operates again to hold the jig 9 and transport it to the standby position.
なお、これら各ディップ時間は、部品リード１０に施さ
れた篩メッキ２の厚さに対応して設定されるが、例えば
Ａｕメッキ２の厚さが５μｍの場合は、Ｓｎディップ時
間は約１５秒であり、 Ｉｎ−Ｓｎディップ時間は１２
０〜１８０秒である。そして、このディップ時間の合計
は、Ｉｎ−Ｓｎディップ槽のみを用いてＡｕメッキを除
去する場合の１１５〜１／１５に相当する。Each of these dipping times is set in accordance with the thickness of the sieve plating 2 applied to the component lead 10. For example, if the thickness of the Au plating 2 is 5 μm, the Sn dipping time is approximately 15 seconds. and the In-Sn dip time is 12
It is 0 to 180 seconds. The total dipping time is equivalent to 115 to 1/15 of the time required to remove Au plating using only the In-Sn dip bath.
以上の説明から明らかなように本発明によれば、部品リ
ード上に施されたＡｕメッキを確実に、しかも短時間で
除去することができるので、部品実装時の信転性が著し
く向上し、且つ部品リードの前処理作業の作業効率が大
幅に改善されるといった優れた工業的効果がある。As is clear from the above description, according to the present invention, Au plating applied to component leads can be removed reliably and in a short time, so reliability during component mounting is significantly improved. In addition, there is an excellent industrial effect in that the work efficiency of component lead pre-processing work is greatly improved.
第１図（ａ）とｆｂ）は本発明の一実施例を模式的に示
した要部側断面図、
第２図は本発明の一応用例を示す模式的要部側断面図、
第３図は半導体装置の実装構造を示す模式的要部側断面
図である。
図中、１はリード母材、
２は＾Ｕメッキ、
３はＳｎディップ槽、
４はＩｎ−Ｓｎディップ槽、
５は＾ｕ−Ｓｎ合金層、
６はＩｎ −Ｓｎ合金層、
９は治具、
１０は部品リード、
１１はハ′キュームノズル、
１５はパッド、
１６はバンプ、
２０は半導体装置、
４０はアーム、
５０はプリント基板、
６０は予備ハンダ装置、
をそれぞれ示す。FIGS. 1(a) and fb) are side sectional views of essential parts schematically showing an embodiment of the present invention; FIG. 2 is a schematic side sectional view of essential parts showing an application example of the present invention; FIG. 1 is a schematic side sectional view of a main part showing a mounting structure of a semiconductor device. In the figure, 1 is the lead base material, 2 is the U plating, 3 is the Sn dip bath, 4 is the In-Sn dip bath, 5 is the u-Sn alloy layer, 6 is the In-Sn alloy layer, and 9 is the jig. , 10 is a component lead, 11 is a vacuum nozzle, 15 is a pad, 16 is a bump, 20 is a semiconductor device, 40 is an arm, 50 is a printed circuit board, and 60 is a preliminary soldering device.
Claims (1)
適用される部品リードの前処理方法であって、 Ａｕメッキ（２）が施された前記部品リード（１０）を
先ずＳｎディップ槽（３）に浸漬して第１回目の予備ハ
ンダ付けを行い、次にこれをＩｎ−Ｓｎディップ槽（４
）に浸漬して第２回目の予備ハンダ付けを行うようにし
たことを特徴とする部品リードの前処理方法。[Claims] A component lead pretreatment method applied when mounting an electronic component such as a semiconductor device on a printed circuit board, the method comprising first treating the component lead (10) with Au plating (2). First preliminary soldering is performed by immersing in the Sn dip tank (3), and then it is immersed in the In-Sn dip tank (4).
) A method for pre-processing component leads, characterized in that a second preliminary soldering is performed by immersing them in a liquid solution.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63174049A JP2625924B2 (en) | 1988-07-12 | 1988-07-12 | Lead pre-processing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63174049A JP2625924B2 (en) | 1988-07-12 | 1988-07-12 | Lead pre-processing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0223643A true JPH0223643A (en) | 1990-01-25 |
| JP2625924B2 JP2625924B2 (en) | 1997-07-02 |
Family
ID=15971729
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63174049A Expired - Lifetime JP2625924B2 (en) | 1988-07-12 | 1988-07-12 | Lead pre-processing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2625924B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111151837A (en) * | 2020-02-07 | 2020-05-15 | 朱会平 | Planar circuit board tinning machine |
-
1988
- 1988-07-12 JP JP63174049A patent/JP2625924B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111151837A (en) * | 2020-02-07 | 2020-05-15 | 朱会平 | Planar circuit board tinning machine |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2625924B2 (en) | 1997-07-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Mei et al. | Brittle interfacial fracture of PBGA packages soldered on electroless nickel/immersion gold | |
| US5188280A (en) | Method of bonding metals, and method and apparatus for producing semiconductor integrated circuit device using said method of bonding metals | |
| US6307160B1 (en) | High-strength solder interconnect for copper/electroless nickel/immersion gold metallization solder pad and method | |
| AU634441B2 (en) | A fluxless soldering process | |
| US5164566A (en) | Method and apparatus for fluxless solder reflow | |
| KR19990028259A (en) | Electronic Components and Electronic Circuit Boards Mounted by Solder and Soldering | |
| WO1998009332A1 (en) | Semiconductor device provided with low melting point metal bumps and process for producing same | |
| EP0365807B1 (en) | Bonding of metallic surfaces | |
| JP3078846B2 (en) | Contact formation of parts without flux | |
| JP3400408B2 (en) | Flip chip mounting method | |
| JPH0223643A (en) | Pretreatment of component lead | |
| US5075258A (en) | Method for plating tab leads in an assembled semiconductor package | |
| JPH06232136A (en) | Electrode forming method of semiconductor element | |
| JPH0331785B2 (en) | ||
| JP4667637B2 (en) | Bonding method of electronic parts | |
| KR101939563B1 (en) | Apparatus for fluxless fabricating a flip-chip package and fabricating method using the same | |
| JP2001358458A (en) | Electronic equipment having lead-free solder connection | |
| JP2534837B2 (en) | Method of soldering parts to circuit board | |
| JPS60154698A (en) | Soldering method | |
| Yung et al. | Investigation on solder void formation mechanism after high temperatures stress by 3D CT scan and EDX analysis | |
| JPH11307585A (en) | Semiconductor device | |
| JP5439794B2 (en) | Electronic device and manufacturing method thereof | |
| JP2903711B2 (en) | Pre-soldering method for flat package | |
| Idris | Interfacial Reactions During Soldering of Sn-Ag-Cu Lead Free Solders on Immersion Silver and Electroless Nickel/Immersion Gold Surface Finishes | |
| Shang et al. | The interfacial reaction of Cu/rnultilayer Sn-Cu-Sn/Cu joint in soldering |